// This file generated automatically by rtl/scripts/csrs/csr_cdefines.pl
#define csr_RxFifoInit_ADDR 0x0
#define csr_PreSequenceReg0b0s0_ADDR 0x0
#define csr_SequenceReg0b71s2_ADDR 0x100
#define csr_AcsmSeq0x0_ADDR 0x0
#define csr_DbyteMiscMode_ADDR 0x0
#define csr_MicroContMuxSel_ADDR 0x0
#define csr_MapCAA0toDfi_ADDR 0x100
#define csr_ForceClkDisable_ADDR 0x1
#define csr_TsmByte0_ADDR 0x1
#define csr_PreSequenceReg0b0s1_ADDR 0x1
#define csr_Seq0BGPR1_ADDR 0x201
#define csr_SequenceReg0b72s0_ADDR 0x101
#define csr_AcsmSeq0x1_ADDR 0x1
#define csr_MapCAA1toDfi_ADDR 0x101
#define csr_ClockingCtrl_ADDR 0x2
#define csr_TrainingParam_ADDR 0x2
#define csr_PreSequenceReg0b0s2_ADDR 0x2
#define csr_Seq0BGPR2_ADDR 0x202
#define csr_SequenceReg0b72s1_ADDR 0x102
#define csr_AcsmSeq0x2_ADDR 0x2
#define csr_MapCAA2toDfi_ADDR 0x102
#define csr_UseDqsEnReplica_ADDR 0x3
#define csr_ForceInternalUpdate_ADDR 0x3
#define csr_PreSequenceReg0b1s0_ADDR 0x3
#define csr_Seq0BGPR3_ADDR 0x203
#define csr_SequenceReg0b72s2_ADDR 0x103
#define csr_AcsmSeq0x3_ADDR 0x3
#define csr_MapCAA3toDfi_ADDR 0x103
#define csr_PhyConfig_ADDR 0x4
#define csr_PreSequenceReg0b1s1_ADDR 0x4
#define csr_Seq0BGPR4_ADDR 0x204
#define csr_SequenceReg0b73s0_ADDR 0x104
#define csr_AcsmSeq0x4_ADDR 0x4
#define csr_DctShadowRegs_ADDR 0x4
#define csr_UctShadowRegs_ADDR 0x4
#define csr_MapCAA4toDfi_ADDR 0x104
#define csr_PGCR_ADDR 0x5
#define csr_PreSequenceReg0b1s2_ADDR 0x5
#define csr_Seq0BGPR5_ADDR 0x205
#define csr_SequenceReg0b73s1_ADDR 0x105
#define csr_AcsmSeq0x5_ADDR 0x5
#define csr_MapCAA5toDfi_ADDR 0x105
#define csr_PostSequenceReg0b0s0_ADDR 0x6
#define csr_Seq0BGPR6_ADDR 0x206
#define csr_SequenceReg0b73s2_ADDR 0x106
#define csr_AcsmSeq0x6_ADDR 0x6
#define csr_MapCAA6toDfi_ADDR 0x106
#define csr_PostSequenceReg0b0s1_ADDR 0x7
#define csr_Seq0BGPR7_ADDR 0x207
#define csr_SequenceReg0b74s0_ADDR 0x107
#define csr_TestBumpCntrl1_ADDR 0x7
#define csr_AcsmSeq0x7_ADDR 0x7
#define csr_MapCAA7toDfi_ADDR 0x107
#define csr_PostSequenceReg0b0s2_ADDR 0x8
#define csr_Seq0BGPR8_ADDR 0x208
#define csr_SequenceReg0b74s1_ADDR 0x108
#define csr_AcsmSeq0x8_ADDR 0x8
#define csr_CalUclkInfo_ADDR 0x8
#define csr_MapCAA8toDfi_ADDR 0x108
#define csr_PostSequenceReg0b1s0_ADDR 0x9
#define csr_SequenceReg0b74s2_ADDR 0x109
#define csr_AcsmSeq0x9_ADDR 0x9
#define csr_MapCAA9toDfi_ADDR 0x109
#define csr_PostSequenceReg0b1s1_ADDR 0xa
#define csr_SequenceReg0b75s0_ADDR 0x10a
#define csr_TestBumpCntrl_ADDR 0xa
#define csr_AcsmSeq0x10_ADDR 0xa
#define csr_PostSequenceReg0b1s2_ADDR 0xb
#define csr_SequenceReg0b75s1_ADDR 0x10b
#define csr_Seq0BDLY0_ADDR 0xb
#define csr_AcsmSeq0x11_ADDR 0xb
#define csr_Seq0BDisableFlag0_ADDR 0xc
#define csr_SequenceReg0b75s2_ADDR 0x10c
#define csr_Seq0BDLY1_ADDR 0xc
#define csr_AcsmSeq0x12_ADDR 0xc
#define csr_Seq0BDisableFlag1_ADDR 0xd
#define csr_SequenceReg0b76s0_ADDR 0x10d
#define csr_Seq0BDLY2_ADDR 0xd
#define csr_AcsmSeq0x13_ADDR 0xd
#define csr_Seq0BDisableFlag2_ADDR 0xe
#define csr_SequenceReg0b76s1_ADDR 0x10e
#define csr_Seq0BDLY3_ADDR 0xe
#define csr_AcsmSeq0x14_ADDR 0xe
#define csr_Seq0BDisableFlag3_ADDR 0xf
#define csr_SequenceReg0b76s2_ADDR 0x10f
#define csr_PhyAlertStatus_ADDR 0xf
#define csr_AcsmSeq0x15_ADDR 0xf
#define csr_RxTrainPatternEnable_ADDR 0x10
#define csr_Seq0BDisableFlag4_ADDR 0x10
#define csr_SequenceReg0b77s0_ADDR 0x110
#define csr_AcsmSeq0x16_ADDR 0x10
#define csr_PPTTrainSetup_ADDR 0x10
#define csr_MapCAB0toDfi_ADDR 0x110
#define csr_TsmByte1_ADDR 0x11
#define csr_Seq0BDisableFlag5_ADDR 0x11
#define csr_SequenceReg0b77s1_ADDR 0x111
#define csr_AcsmSeq0x17_ADDR 0x11
#define csr_PPGCCtrl1_ADDR 0x11
#define csr_PPTTrainSetup2_ADDR 0x11
#define csr_MapCAB1toDfi_ADDR 0x111
#define csr_TsmByte2_ADDR 0x12
#define csr_Seq0BDisableFlag6_ADDR 0x12
#define csr_SequenceReg0b77s2_ADDR 0x112
#define csr_AcsmSeq0x18_ADDR 0x12
#define csr_ATestMode_ADDR 0x12
#define csr_MapCAB2toDfi_ADDR 0x112
#define csr_TsmByte3_ADDR 0x13
#define csr_Seq0BDisableFlag7_ADDR 0x13
#define csr_SequenceReg0b78s0_ADDR 0x113
#define csr_AcsmSeq0x19_ADDR 0x13
#define csr_MapCAB3toDfi_ADDR 0x113
#define csr_TsmByte4_ADDR 0x14
#define csr_SequenceReg0b78s1_ADDR 0x114
#define csr_AcsmSeq0x20_ADDR 0x14
#define csr_TxCalBinP_ADDR 0x14
#define csr_MapCAB4toDfi_ADDR 0x114
#define csr_PpgcLane2CrcInMap0_ADDR 0x15
#define csr_SequenceReg0b78s2_ADDR 0x115
#define csr_AcsmSeq0x21_ADDR 0x15
#define csr_TxCalBinN_ADDR 0x15
#define csr_MapCAB5toDfi_ADDR 0x115
#define csr_PpgcLane2CrcInMap1_ADDR 0x16
#define csr_SequenceReg0b79s0_ADDR 0x116
#define csr_AcsmSeq0x22_ADDR 0x16
#define csr_TxCalPOvr_ADDR 0x16
#define csr_MapCAB6toDfi_ADDR 0x116
#define csr_StartVector0b0_ADDR 0x17
#define csr_SequenceReg0b79s1_ADDR 0x117
#define csr_AcsmSeq0x23_ADDR 0x17
#define csr_TestModeConfig_ADDR 0x17
#define csr_TxCalNOvr_ADDR 0x17
#define csr_MapCAB7toDfi_ADDR 0x117
#define csr_TsmByte5_ADDR 0x18
#define csr_StartVector0b1_ADDR 0x18
#define csr_SequenceReg0b79s2_ADDR 0x118
#define csr_AcsmSeq0x24_ADDR 0x18
#define csr_DfiMode_ADDR 0x18
#define csr_MapCAB8toDfi_ADDR 0x118
#define csr_TristateModeCA_ADDR 0x19
#define csr_StartVector0b2_ADDR 0x19
#define csr_SequenceReg0b80s0_ADDR 0x119
#define csr_AcsmSeq0x25_ADDR 0x19
#define csr_MapCAB9toDfi_ADDR 0x119
#define csr_MtestMuxSel_ADDR 0x1a
#define csr_StartVector0b3_ADDR 0x1a
#define csr_SequenceReg0b80s1_ADDR 0x11a
#define csr_AcsmSeq0x26_ADDR 0x1a
#define csr_MtestPgmInfo_ADDR 0x1b
#define csr_StartVector0b4_ADDR 0x1b
#define csr_SequenceReg0b80s2_ADDR 0x11b
#define csr_AcsmSeq0x27_ADDR 0x1b
#define csr_PhyInterruptEnable_ADDR 0x11b
#define csr_StartVector0b5_ADDR 0x1c
#define csr_SequenceReg0b81s0_ADDR 0x11c
#define csr_AcsmSeq0x28_ADDR 0x1c
#define csr_DynPwrDnUp_ADDR 0x1c
#define csr_PhyInterruptFWControl_ADDR 0x11c
#define csr_StartVector0b6_ADDR 0x1d
#define csr_SequenceReg0b81s1_ADDR 0x11d
#define csr_AcsmSeq0x29_ADDR 0x1d
#define csr_PMIEnable_ADDR 0x1d
#define csr_PhyInterruptMask_ADDR 0x11d
#define csr_StartVector0b7_ADDR 0x1e
#define csr_SequenceReg0b81s2_ADDR 0x11e
#define csr_AcsmSeq0x30_ADDR 0x1e
#define csr_PhyTID_ADDR 0x1e
#define csr_PhyInterruptClear_ADDR 0x11e
#define csr_DtsmTrainModeCtrl_ADDR 0x1f
#define csr_StartVector0b8_ADDR 0x1f
#define csr_SequenceReg0b82s0_ADDR 0x11f
#define csr_AcsmSeq0x31_ADDR 0x1f
#define csr_PhyInterruptStatus_ADDR 0x11f
#define csr_HwtMRL_ADDR 0x20
#define csr_DFIMRL_ADDR 0x20
#define csr_StartVector0b9_ADDR 0x20
#define csr_SequenceReg0b82s1_ADDR 0x120
#define csr_AcsmSeq1x0_ADDR 0x20
#define csr_HwtSwizzleHwtAddress0_ADDR 0x120
#define csr_DFIPHYUPD_ADDR 0x21
#define csr_StartVector0b10_ADDR 0x21
#define csr_SequenceReg0b82s2_ADDR 0x121
#define csr_AcsmSeq1x1_ADDR 0x21
#define csr_HwtSwizzleHwtAddress1_ADDR 0x121
#define csr_PdaMrsWriteMode_ADDR 0x22
#define csr_StartVector0b11_ADDR 0x22
#define csr_SequenceReg0b83s0_ADDR 0x122
#define csr_AcsmSeq1x2_ADDR 0x22
#define csr_HwtSwizzleHwtAddress2_ADDR 0x122
#define csr_DFIGEARDOWNCTL_ADDR 0x23
#define csr_StartVector0b12_ADDR 0x23
#define csr_SequenceReg0b83s1_ADDR 0x123
#define csr_AcsmSeq1x3_ADDR 0x23
#define csr_HwtSwizzleHwtAddress3_ADDR 0x123
#define csr_PrbsTapDly0_ADDR 0x24
#define csr_DqsPreambleControl_ADDR 0x24
#define csr_StartVector0b13_ADDR 0x24
#define csr_SequenceReg0b83s2_ADDR 0x124
#define csr_AcsmSeq1x4_ADDR 0x24
#define csr_AsyncDbyteMode_ADDR 0x24
#define csr_HwtSwizzleHwtAddress4_ADDR 0x124
#define csr_PrbsTapDly1_ADDR 0x25
#define csr_MasterX4Config_ADDR 0x25
#define csr_StartVector0b14_ADDR 0x25
#define csr_SequenceReg0b84s0_ADDR 0x125
#define csr_AcsmSeq1x5_ADDR 0x25
#define csr_HwtSwizzleHwtAddress5_ADDR 0x125
#define csr_PrbsTapDly2_ADDR 0x26
#define csr_WrLevBits_ADDR 0x26
#define csr_StartVector0b15_ADDR 0x26
#define csr_SequenceReg0b84s1_ADDR 0x126
#define csr_AcsmSeq1x6_ADDR 0x26
#define csr_AsyncDbyteTxEn_ADDR 0x26
#define csr_HwtSwizzleHwtAddress6_ADDR 0x126
#define csr_PrbsTapDly3_ADDR 0x27
#define csr_EnableCsMulticast_ADDR 0x27
#define csr_Seq0bWaitCondSel_ADDR 0x27
#define csr_SequenceReg0b84s2_ADDR 0x127
#define csr_AcsmSeq1x7_ADDR 0x27
#define csr_HwtSwizzleHwtAddress7_ADDR 0x127
#define csr_AForceDrvCont_ADDR 0x27
#define csr_HwtLpCsMultiCast_ADDR 0x28
#define csr_AForceTriCont_ADDR 0x28
#define csr_PhyInLP3_ADDR 0x28
#define csr_SequenceReg0b85s0_ADDR 0x128
#define csr_AcsmSeq1x8_ADDR 0x28
#define csr_AsyncDbyteTxData_ADDR 0x28
#define csr_HwtSwizzleHwtAddress8_ADDR 0x128
#define csr_SequenceReg0b0s0_ADDR 0x29
#define csr_SequenceReg0b85s1_ADDR 0x129
#define csr_AcsmSeq1x9_ADDR 0x29
#define csr_HwtSwizzleHwtAddress9_ADDR 0x129
#define csr_SequenceReg0b0s1_ADDR 0x2a
#define csr_SequenceReg0b85s2_ADDR 0x12a
#define csr_AcsmSeq1x10_ADDR 0x2a
#define csr_AsyncDbyteRxData_ADDR 0x2a
#define csr_HwtSwizzleHwtAddress10_ADDR 0x12a
#define csr_SequenceReg0b0s2_ADDR 0x2b
#define csr_SequenceReg0b86s0_ADDR 0x12b
#define csr_AcsmSeq1x11_ADDR 0x2b
#define csr_HwtSwizzleHwtAddress11_ADDR 0x12b
#define csr_SequenceReg0b1s0_ADDR 0x2c
#define csr_SequenceReg0b86s1_ADDR 0x12c
#define csr_AcsmSeq1x12_ADDR 0x2c
#define csr_Acx4AnibDis_ADDR 0x2c
#define csr_HwtSwizzleHwtAddress12_ADDR 0x12c
#define csr_DMIPinPresent_ADDR 0x2d
#define csr_SequenceReg0b1s1_ADDR 0x2d
#define csr_SequenceReg0b86s2_ADDR 0x12d
#define csr_AcsmSeq1x13_ADDR 0x2d
#define csr_HwtSwizzleHwtAddress13_ADDR 0x12d
#define csr_ARdPtrInitVal_ADDR 0x2e
#define csr_SequenceReg0b1s2_ADDR 0x2e
#define csr_SequenceReg0b87s0_ADDR 0x12e
#define csr_AcsmSeq1x14_ADDR 0x2e
#define csr_HwtSwizzleHwtAddress14_ADDR 0x12e
#define csr_SequenceReg0b2s0_ADDR 0x2f
#define csr_SequenceReg0b87s1_ADDR 0x12f
#define csr_AcsmSeq1x15_ADDR 0x2f
#define csr_HwtSwizzleHwtAddress15_ADDR 0x12f
#define csr_Db0LcdlCalPhDetOut_ADDR 0x30
#define csr_GenPrbsByte0_ADDR 0x30
#define csr_SequenceReg0b2s1_ADDR 0x30
#define csr_SequenceReg0b87s2_ADDR 0x130
#define csr_AcsmSeq1x16_ADDR 0x30
#define csr_VrefDAC1_ADDR 0x30
#define csr_DctWriteOnly_ADDR 0x30
#define csr_DctWriteOnlyShadow_ADDR 0x30
#define csr_HwtSwizzleHwtAddress17_ADDR 0x130
#define csr_Db1LcdlCalPhDetOut_ADDR 0x31
#define csr_GenPrbsByte1_ADDR 0x31
#define csr_SequenceReg0b2s2_ADDR 0x31
#define csr_SequenceReg0b88s0_ADDR 0x131
#define csr_AcsmSeq1x17_ADDR 0x31
#define csr_DctWriteProt_ADDR 0x31
#define csr_HwtSwizzleHwtActN_ADDR 0x131
#define csr_Db2LcdlCalPhDetOut_ADDR 0x32
#define csr_TrainingCntr_ADDR 0x32
#define csr_GenPrbsByte2_ADDR 0x32
#define csr_SequenceReg0b3s0_ADDR 0x32
#define csr_SequenceReg0b88s1_ADDR 0x132
#define csr_AcsmSeq1x18_ADDR 0x32
#define csr_UctWriteOnly_ADDR 0x32
#define csr_UctWriteOnlyShadow_ADDR 0x32
#define csr_HwtSwizzleHwtBank0_ADDR 0x132
#define csr_Db3LcdlCalPhDetOut_ADDR 0x33
#define csr_GenPrbsByte3_ADDR 0x33
#define csr_SequenceReg0b3s1_ADDR 0x33
#define csr_SequenceReg0b88s2_ADDR 0x133
#define csr_AcsmSeq1x19_ADDR 0x33
#define csr_UctWriteProt_ADDR 0x33
#define csr_HwtSwizzleHwtBank1_ADDR 0x133
#define csr_Db4LcdlCalPhDetOut_ADDR 0x34
#define csr_GenPrbsByte4_ADDR 0x34
#define csr_SequenceReg0b3s2_ADDR 0x34
#define csr_SequenceReg0b89s0_ADDR 0x134
#define csr_AcsmSeq1x20_ADDR 0x34
#define csr_UctDatWriteOnly_ADDR 0x34
#define csr_UctDatWriteOnlyShadow_ADDR 0x34
#define csr_HwtSwizzleHwtBank2_ADDR 0x134
#define csr_Db5LcdlCalPhDetOut_ADDR 0x35
#define csr_GenPrbsByte5_ADDR 0x35
#define csr_SequenceReg0b4s0_ADDR 0x35
#define csr_SequenceReg0b89s1_ADDR 0x135
#define csr_AcsmSeq1x21_ADDR 0x35
#define csr_NeverGateCsrClock_ADDR 0x35
#define csr_UctDatWriteProt_ADDR 0x35
#define csr_HwtSwizzleHwtBg0_ADDR 0x135
#define csr_Db6LcdlCalPhDetOut_ADDR 0x36
#define csr_GenPrbsByte6_ADDR 0x36
#define csr_SequenceReg0b4s1_ADDR 0x36
#define csr_SequenceReg0b89s2_ADDR 0x136
#define csr_AcsmSeq1x22_ADDR 0x36
#define csr_UctlErr_ADDR 0x36
#define csr_HwtSwizzleHwtBg1_ADDR 0x136
#define csr_Db7LcdlCalPhDetOut_ADDR 0x37
#define csr_GenPrbsByte7_ADDR 0x37
#define csr_SequenceReg0b4s2_ADDR 0x37
#define csr_SequenceReg0b90s0_ADDR 0x137
#define csr_AcsmSeq1x23_ADDR 0x37
#define csr_DfiCfgRdDataValidTicks_ADDR 0x37
#define csr_HwtSwizzleHwtCasN_ADDR 0x137
#define csr_Db8LcdlCalPhDetOut_ADDR 0x38
#define csr_GenPrbsByte8_ADDR 0x38
#define csr_SequenceReg0b5s0_ADDR 0x38
#define csr_SequenceReg0b90s1_ADDR 0x138
#define csr_AcsmSeq1x24_ADDR 0x38
#define csr_HwtSwizzleHwtRasN_ADDR 0x138
#define csr_Db9LcdlCalPhDetOut_ADDR 0x39
#define csr_GenPrbsByte9_ADDR 0x39
#define csr_SequenceReg0b5s1_ADDR 0x39
#define csr_SequenceReg0b90s2_ADDR 0x139
#define csr_AcsmSeq1x25_ADDR 0x39
#define csr_HwtSwizzleHwtWeN_ADDR 0x139
#define csr_GenPrbsByte10_ADDR 0x3a
#define csr_SequenceReg0b5s2_ADDR 0x3a
#define csr_SequenceReg0b91s0_ADDR 0x13a
#define csr_AcsmSeq1x26_ADDR 0x3a
#define csr_DbyteDllModeCntrl_ADDR 0x3a
#define csr_HwtSwizzleHwtParityIn_ADDR 0x13a
#define csr_GenPrbsByte11_ADDR 0x3b
#define csr_SequenceReg0b6s0_ADDR 0x3b
#define csr_SequenceReg0b91s1_ADDR 0x13b
#define csr_AcsmSeq1x27_ADDR 0x3b
#define csr_DbyteRxEnTrain_ADDR 0x3b
#define csr_GenPrbsByte12_ADDR 0x3c
#define csr_SequenceReg0b6s1_ADDR 0x3c
#define csr_SequenceReg0b91s2_ADDR 0x13c
#define csr_AcsmSeq1x28_ADDR 0x3c
#define csr_DfiHandshakeDelays0_ADDR 0x13c
#define csr_GenPrbsByte13_ADDR 0x3d
#define csr_SequenceReg0b6s2_ADDR 0x3d
#define csr_SequenceReg0b92s0_ADDR 0x13d
#define csr_AcsmSeq1x29_ADDR 0x3d
#define csr_DfiHandshakeDelays1_ADDR 0x13d
#define csr_GenPrbsByte14_ADDR 0x3e
#define csr_SequenceReg0b7s0_ADDR 0x3e
#define csr_SequenceReg0b92s1_ADDR 0x13e
#define csr_AcsmSeq1x30_ADDR 0x3e
#define csr_RemoteImpCal_ADDR 0x13e
#define csr_AnLcdlCalPhDetOut_ADDR 0x3f
#define csr_GenPrbsByte15_ADDR 0x3f
#define csr_SequenceReg0b7s1_ADDR 0x3f
#define csr_SequenceReg0b92s2_ADDR 0x13f
#define csr_AcsmSeq1x31_ADDR 0x3f
#define csr_ACLoopbackCtl_ADDR 0x13f
#define csr_SequenceReg0b7s2_ADDR 0x40
#define csr_SequenceReg0b93s0_ADDR 0x140
#define csr_AcsmSeq2x0_ADDR 0x40
#define csr_VrefDAC0_ADDR 0x40
#define csr_SequenceReg0b8s0_ADDR 0x41
#define csr_SequenceReg0b93s1_ADDR 0x141
#define csr_AcsmSeq2x1_ADDR 0x41
#define csr_TxImpedanceCtrl0_ADDR 0x41
#define csr_SequenceReg0b8s1_ADDR 0x42
#define csr_SequenceReg0b93s2_ADDR 0x142
#define csr_AcsmSeq2x2_ADDR 0x42
#define csr_SequenceReg0b8s2_ADDR 0x43
#define csr_SequenceReg0b94s0_ADDR 0x143
#define csr_AcsmSeq2x3_ADDR 0x43
#define csr_ATxImpedance_ADDR 0x43
#define csr_DqDqsRcvCntrl_ADDR 0x43
#define csr_SequenceReg0b9s0_ADDR 0x44
#define csr_SequenceReg0b94s1_ADDR 0x144
#define csr_AcsmSeq2x4_ADDR 0x44
#define csr_SequenceReg0b9s1_ADDR 0x45
#define csr_SequenceReg0b94s2_ADDR 0x145
#define csr_AcsmSeq2x5_ADDR 0x45
#define csr_CalOffsets_ADDR 0x45
#define csr_SequenceReg0b9s2_ADDR 0x46
#define csr_SequenceReg0b95s0_ADDR 0x146
#define csr_AcsmSeq2x6_ADDR 0x46
#define csr_SequenceReg0b10s0_ADDR 0x47
#define csr_SequenceReg0b95s1_ADDR 0x147
#define csr_AcsmSeq2x7_ADDR 0x47
#define csr_SarInitVals_ADDR 0x47
#define csr_SequenceReg0b10s1_ADDR 0x48
#define csr_SequenceReg0b95s2_ADDR 0x148
#define csr_AcsmSeq2x8_ADDR 0x48
#define csr_TxEqualizationMode_ADDR 0x48
#define csr_SequenceReg0b10s2_ADDR 0x49
#define csr_SequenceReg0b96s0_ADDR 0x149
#define csr_AcsmSeq2x9_ADDR 0x49
#define csr_TxImpedanceCtrl1_ADDR 0x49
#define csr_CalPExtOvr_ADDR 0x49
#define csr_SequenceReg0b11s0_ADDR 0x4a
#define csr_SequenceReg0b96s1_ADDR 0x14a
#define csr_AcsmSeq2x10_ADDR 0x4a
#define csr_DqDqsRcvCntrl1_ADDR 0x4a
#define csr_CalCmpr5Ovr_ADDR 0x4a
#define csr_SequenceReg0b11s1_ADDR 0x4b
#define csr_SequenceReg0b96s2_ADDR 0x14b
#define csr_AcsmSeq2x11_ADDR 0x4b
#define csr_TxImpedanceCtrl2_ADDR 0x4b
#define csr_CalNIntOvr_ADDR 0x4b
#define csr_SequenceReg0b11s2_ADDR 0x4c
#define csr_SequenceReg0b97s0_ADDR 0x14c
#define csr_AcsmSeq2x12_ADDR 0x4c
#define csr_DqDqsRcvCntrl2_ADDR 0x4c
#define csr_SequenceReg0b12s0_ADDR 0x4d
#define csr_SequenceReg0b97s1_ADDR 0x14d
#define csr_AcsmSeq2x13_ADDR 0x4d
#define csr_TxOdtDrvStren_ADDR 0x4d
#define csr_SequenceReg0b12s1_ADDR 0x4e
#define csr_SequenceReg0b97s2_ADDR 0x14e
#define csr_AcsmSeq2x14_ADDR 0x4e
#define csr_SequenceReg0b12s2_ADDR 0x4f
#define csr_SequenceReg0b98s0_ADDR 0x14f
#define csr_AcsmSeq2x15_ADDR 0x4f
#define csr_SequenceReg0b13s0_ADDR 0x50
#define csr_SequenceReg0b98s1_ADDR 0x150
#define csr_AcsmSeq2x16_ADDR 0x50
#define csr_CalDrvStr0_ADDR 0x50
#define csr_SequenceReg0b13s1_ADDR 0x51
#define csr_SequenceReg0b98s2_ADDR 0x151
#define csr_AcsmSeq2x17_ADDR 0x51
#define csr_SequenceReg0b13s2_ADDR 0x52
#define csr_SequenceReg0b99s0_ADDR 0x152
#define csr_AcsmSeq2x18_ADDR 0x52
#define csr_SequenceReg0b14s0_ADDR 0x53
#define csr_SequenceReg0b99s1_ADDR 0x153
#define csr_AcsmSeq2x19_ADDR 0x53
#define csr_ATestPrbsErr_ADDR 0x53
#define csr_SequenceReg0b14s1_ADDR 0x54
#define csr_SequenceReg0b99s2_ADDR 0x154
#define csr_AcsmSeq2x20_ADDR 0x54
#define csr_SequenceReg0b14s2_ADDR 0x55
#define csr_SequenceReg0b100s0_ADDR 0x155
#define csr_AcsmSeq2x21_ADDR 0x55
#define csr_ProcOdtCtl_ADDR 0x55
#define csr_ATxSlewRate_ADDR 0x55
#define csr_SequenceReg0b15s0_ADDR 0x56
#define csr_SequenceReg0b100s1_ADDR 0x156
#define csr_AcsmSeq2x22_ADDR 0x56
#define csr_ProcOdtTimeCtl_ADDR 0x56
#define csr_ATestPrbsErrCnt_ADDR 0x56
#define csr_RxFifoCheckStatus_ADDR 0x56
#define csr_SequenceReg0b15s1_ADDR 0x57
#define csr_SequenceReg0b100s2_ADDR 0x157
#define csr_AcsmSeq2x23_ADDR 0x57
#define csr_RxFifoCheckErrValues_ADDR 0x57
#define csr_SequenceReg0b15s2_ADDR 0x58
#define csr_SequenceReg0b101s0_ADDR 0x158
#define csr_AcsmSeq2x24_ADDR 0x58
#define csr_RxFifoInfo_ADDR 0x58
#define csr_SequenceReg0b16s0_ADDR 0x59
#define csr_SequenceReg0b101s1_ADDR 0x159
#define csr_AcsmSeq2x25_ADDR 0x59
#define csr_RxFifoVisibility_ADDR 0x59
#define csr_SequenceReg0b16s1_ADDR 0x5a
#define csr_SequenceReg0b101s2_ADDR 0x15a
#define csr_AcsmSeq2x26_ADDR 0x5a
#define csr_RxFifoContentsDQ3210_ADDR 0x5a
#define csr_SequenceReg0b16s2_ADDR 0x5b
#define csr_SequenceReg0b102s0_ADDR 0x15b
#define csr_MemAlertControl_ADDR 0x5b
#define csr_AcsmSeq2x27_ADDR 0x5b
#define csr_RxFifoContentsDQ7654_ADDR 0x5b
#define csr_SequenceReg0b17s0_ADDR 0x5c
#define csr_SequenceReg0b102s1_ADDR 0x15c
#define csr_MemAlertControl2_ADDR 0x5c
#define csr_AcsmSeq2x28_ADDR 0x5c
#define csr_RxFifoContentsDBI_ADDR 0x5c
#define csr_SequenceReg0b17s1_ADDR 0x5d
#define csr_SequenceReg0b102s2_ADDR 0x15d
#define csr_AcsmSeq2x29_ADDR 0x5d
#define csr_SequenceReg0b17s2_ADDR 0x5e
#define csr_SequenceReg0b103s0_ADDR 0x15e
#define csr_AcsmSeq2x30_ADDR 0x5e
#define csr_SequenceReg0b18s0_ADDR 0x5f
#define csr_SequenceReg0b103s1_ADDR 0x15f
#define csr_AcsmSeq2x31_ADDR 0x5f
#define csr_TxSlewRate_ADDR 0x5f
#define csr_PrbsGenCtl_ADDR 0x60
#define csr_SequenceReg0b18s1_ADDR 0x60
#define csr_SequenceReg0b103s2_ADDR 0x160
#define csr_MemResetL_ADDR 0x60
#define csr_AcsmSeq3x0_ADDR 0x60
#define csr_PrbsGenStateLo_ADDR 0x61
#define csr_SequenceReg0b18s2_ADDR 0x61
#define csr_SequenceReg0b104s0_ADDR 0x161
#define csr_AcsmSeq3x1_ADDR 0x61
#define csr_TrainingIncDecDtsmEn_ADDR 0x62
#define csr_PrbsGenStateHi_ADDR 0x62
#define csr_SequenceReg0b19s0_ADDR 0x62
#define csr_SequenceReg0b104s1_ADDR 0x162
#define csr_AcsmSeq3x2_ADDR 0x62
#define csr_PrbsChkStateLo_ADDR 0x63
#define csr_SequenceReg0b19s1_ADDR 0x63
#define csr_SequenceReg0b104s2_ADDR 0x163
#define csr_AcsmSeq3x3_ADDR 0x63
#define csr_PrbsChkStateHi_ADDR 0x64
#define csr_SequenceReg0b19s2_ADDR 0x64
#define csr_SequenceReg0b105s0_ADDR 0x164
#define csr_AcsmSeq3x4_ADDR 0x64
#define csr_PrbsGenCtl1_ADDR 0x65
#define csr_SequenceReg0b20s0_ADDR 0x65
#define csr_SequenceReg0b105s1_ADDR 0x165
#define csr_AcsmSeq3x5_ADDR 0x65
#define csr_PrbsGenCtl2_ADDR 0x66
#define csr_SequenceReg0b20s1_ADDR 0x66
#define csr_SequenceReg0b105s2_ADDR 0x166
#define csr_AcsmSeq3x6_ADDR 0x66
#define csr_SequenceReg0b20s2_ADDR 0x67
#define csr_SequenceReg0b106s0_ADDR 0x167
#define csr_AcsmSeq3x7_ADDR 0x67
#define csr_RxPBDlyTg0_ADDR 0x68
#define csr_SequenceReg0b21s0_ADDR 0x68
#define csr_SequenceReg0b106s1_ADDR 0x168
#define csr_AcsmSeq3x8_ADDR 0x68
#define csr_RxPBDlyTg1_ADDR 0x69
#define csr_SequenceReg0b21s1_ADDR 0x69
#define csr_SequenceReg0b106s2_ADDR 0x169
#define csr_AcsmSeq3x9_ADDR 0x69
#define csr_RxPBDlyTg2_ADDR 0x6a
#define csr_SequenceReg0b21s2_ADDR 0x6a
#define csr_SequenceReg0b107s0_ADDR 0x16a
#define csr_AcsmSeq3x10_ADDR 0x6a
#define csr_RxPBDlyTg3_ADDR 0x6b
#define csr_SequenceReg0b22s0_ADDR 0x6b
#define csr_SequenceReg0b107s1_ADDR 0x16b
#define csr_AcsmSeq3x11_ADDR 0x6b
#define csr_SequenceReg0b22s1_ADDR 0x6c
#define csr_SequenceReg0b107s2_ADDR 0x16c
#define csr_AcsmSeq3x12_ADDR 0x6c
#define csr_SequenceReg0b22s2_ADDR 0x6d
#define csr_SequenceReg0b108s0_ADDR 0x16d
#define csr_AcsmSeq3x13_ADDR 0x6d
#define csr_SequenceReg0b23s0_ADDR 0x6e
#define csr_SequenceReg0b108s1_ADDR 0x16e
#define csr_PUBMODE_ADDR 0x6e
#define csr_AcsmSeq3x14_ADDR 0x6e
#define csr_SequenceReg0b23s1_ADDR 0x6f
#define csr_SequenceReg0b108s2_ADDR 0x16f
#define csr_MiscPhyStatus_ADDR 0x6f
#define csr_AcsmSeq3x15_ADDR 0x6f
#define csr_CoreLoopbackSel_ADDR 0x70
#define csr_SequenceReg0b23s2_ADDR 0x70
#define csr_SequenceReg0b109s0_ADDR 0x170
#define csr_AcsmSeq3x16_ADDR 0x70
#define csr_DllTrainParam_ADDR 0x71
#define csr_SequenceReg0b24s0_ADDR 0x71
#define csr_SequenceReg0b109s1_ADDR 0x171
#define csr_AcsmSeq3x17_ADDR 0x71
#define csr_HwtLpCsEnA_ADDR 0x72
#define csr_SequenceReg0b24s1_ADDR 0x72
#define csr_SequenceReg0b109s2_ADDR 0x172
#define csr_AcsmSeq3x18_ADDR 0x72
#define csr_HwtLpCsEnB_ADDR 0x73
#define csr_SequenceReg0b24s2_ADDR 0x73
#define csr_SequenceReg0b110s0_ADDR 0x173
#define csr_AcsmSeq3x19_ADDR 0x73
#define csr_HwtLpCsEnBypass_ADDR 0x74
#define csr_SequenceReg0b25s0_ADDR 0x74
#define csr_SequenceReg0b110s1_ADDR 0x174
#define csr_AcsmSeq3x20_ADDR 0x74
#define csr_DfiCAMode_ADDR 0x75
#define csr_SequenceReg0b25s1_ADDR 0x75
#define csr_SequenceReg0b110s2_ADDR 0x175
#define csr_AcsmSeq3x21_ADDR 0x75
#define csr_HwtCACtl_ADDR 0x76
#define csr_SequenceReg0b25s2_ADDR 0x76
#define csr_SequenceReg0b111s0_ADDR 0x176
#define csr_AcsmSeq3x22_ADDR 0x76
#define csr_HwtCAMode_ADDR 0x77
#define csr_SequenceReg0b26s0_ADDR 0x77
#define csr_SequenceReg0b111s1_ADDR 0x177
#define csr_AcsmSeq3x23_ADDR 0x77
#define csr_SequenceReg0b26s1_ADDR 0x78
#define csr_SequenceReg0b111s2_ADDR 0x178
#define csr_AcsmSeq3x24_ADDR 0x78
#define csr_DllControl_ADDR 0x78
#define csr_SequenceReg0b26s2_ADDR 0x79
#define csr_SequenceReg0b112s0_ADDR 0x179
#define csr_AcsmSeq3x25_ADDR 0x79
#define csr_PulseDllUpdatePhase_ADDR 0x79
#define csr_HwtControlOvr0_ADDR 0x7a
#define csr_SequenceReg0b27s0_ADDR 0x7a
#define csr_SequenceReg0b112s1_ADDR 0x17a
#define csr_AcsmSeq3x26_ADDR 0x7a
#define csr_HwtControlOvr1_ADDR 0x7b
#define csr_SequenceReg0b27s1_ADDR 0x7b
#define csr_SequenceReg0b112s2_ADDR 0x17b
#define csr_AcsmSeq3x27_ADDR 0x7b
#define csr_SequenceReg0b27s2_ADDR 0x7c
#define csr_SequenceReg0b113s0_ADDR 0x17c
#define csr_AcsmSeq3x28_ADDR 0x7c
#define csr_DllGainCtl_ADDR 0x7c
#define csr_SequenceReg0b28s0_ADDR 0x7d
#define csr_SequenceReg0b113s1_ADDR 0x17d
#define csr_AcsmSeq3x29_ADDR 0x7d
#define csr_DllLockParam_ADDR 0x7d
#define csr_HwtControlVal0_ADDR 0x7e
#define csr_SequenceReg0b28s1_ADDR 0x7e
#define csr_SequenceReg0b113s2_ADDR 0x17e
#define csr_AcsmSeq3x30_ADDR 0x7e
#define csr_HwtControlVal1_ADDR 0x7f
#define csr_SequenceReg0b28s2_ADDR 0x7f
#define csr_SequenceReg0b114s0_ADDR 0x17f
#define csr_AcsmSeq3x31_ADDR 0x7f
#define csr_RxEnDlyTg0_ADDR 0x80
#define csr_ATxDly_ADDR 0x80
#define csr_SequenceReg0b29s0_ADDR 0x80
#define csr_SequenceReg0b114s1_ADDR 0x180
#define csr_AcsmPlayback0x0_ADDR 0x80
#define csr_UcclkHclkEnables_ADDR 0x80
#define csr_RxEnDlyTg1_ADDR 0x81
#define csr_SequenceReg0b29s1_ADDR 0x81
#define csr_SequenceReg0b114s2_ADDR 0x181
#define csr_CurPstate0b_ADDR 0x81
#define csr_AcsmGlblStart_ADDR 0x81
#define csr_AcsmPlayback1x0_ADDR 0x81
#define csr_RxEnDlyTg2_ADDR 0x82
#define csr_SequenceReg0b29s2_ADDR 0x82
#define csr_SequenceReg0b115s0_ADDR 0x182
#define csr_AcsmGlblSglStpCtrl_ADDR 0x82
#define csr_AcsmPlayback0x1_ADDR 0x82
#define csr_RxEnDlyTg3_ADDR 0x83
#define csr_SequenceReg0b30s0_ADDR 0x83
#define csr_SequenceReg0b115s1_ADDR 0x183
#define csr_AcsmPlayback1x1_ADDR 0x83
#define csr_SequenceReg0b30s1_ADDR 0x84
#define csr_SequenceReg0b115s2_ADDR 0x184
#define csr_AcsmPlayback0x2_ADDR 0x84
#define csr_LcdlCalPhase_ADDR 0x84
#define csr_SequenceReg0b30s2_ADDR 0x85
#define csr_SequenceReg0b116s0_ADDR 0x185
#define csr_AcsmPlayback1x2_ADDR 0x85
#define csr_LcdlCalCtrl_ADDR 0x85
#define csr_SequenceReg0b31s0_ADDR 0x86
#define csr_SequenceReg0b116s1_ADDR 0x186
#define csr_AcsmPlayback0x3_ADDR 0x86
#define csr_SequenceReg0b31s1_ADDR 0x87
#define csr_SequenceReg0b116s2_ADDR 0x187
#define csr_AcsmPlayback1x3_ADDR 0x87
#define csr_SequenceReg0b31s2_ADDR 0x88
#define csr_SequenceReg0b117s0_ADDR 0x188
#define csr_AcsmPlayback0x4_ADDR 0x88
#define csr_CalRate_ADDR 0x88
#define csr_SequenceReg0b32s0_ADDR 0x89
#define csr_SequenceReg0b117s1_ADDR 0x189
#define csr_AcsmPlayback1x4_ADDR 0x89
#define csr_CalZap_ADDR 0x89
#define csr_SequenceReg0b32s1_ADDR 0x8a
#define csr_SequenceReg0b117s2_ADDR 0x18a
#define csr_AcsmPlayback0x5_ADDR 0x8a
#define csr_SequenceReg0b32s2_ADDR 0x8b
#define csr_SequenceReg0b118s0_ADDR 0x18b
#define csr_AcsmPlayback1x5_ADDR 0x8b
#define csr_PState_ADDR 0x8b
#define csr_RxClkDlyTg0_ADDR 0x8c
#define csr_SequenceReg0b33s0_ADDR 0x8c
#define csr_SequenceReg0b118s1_ADDR 0x18c
#define csr_AcsmPlayback0x6_ADDR 0x8c
#define csr_CalPreDriverOverride_ADDR 0x8c
#define csr_RxClkDlyTg1_ADDR 0x8d
#define csr_SequenceReg0b33s1_ADDR 0x8d
#define csr_SequenceReg0b118s2_ADDR 0x18d
#define csr_AcsmPlayback1x6_ADDR 0x8d
#define csr_PllOutGateControl_ADDR 0x8d
#define csr_RxClkDlyTg2_ADDR 0x8e
#define csr_SequenceReg0b33s2_ADDR 0x8e
#define csr_SequenceReg0b119s0_ADDR 0x18e
#define csr_AcsmPlayback0x7_ADDR 0x8e
#define csr_RxClkDlyTg3_ADDR 0x8f
#define csr_SequenceReg0b34s0_ADDR 0x8f
#define csr_SequenceReg0b119s1_ADDR 0x18f
#define csr_AcsmPlayback1x7_ADDR 0x8f
#define csr_UcMemResetControl_ADDR 0x8f
#define csr_RxClkcDlyTg0_ADDR 0x90
#define csr_SequenceReg0b34s1_ADDR 0x90
#define csr_SequenceReg0b119s2_ADDR 0x190
#define csr_AcsmPStateOvrEn_ADDR 0x90
#define csr_PorControl_ADDR 0x90
#define csr_RxClkcDlyTg1_ADDR 0x91
#define csr_SequenceReg0b34s2_ADDR 0x91
#define csr_SequenceReg0b120s0_ADDR 0x191
#define csr_AcsmPStateOvrVal_ADDR 0x91
#define csr_RxClkcDlyTg2_ADDR 0x92
#define csr_SequenceReg0b35s0_ADDR 0x92
#define csr_SequenceReg0b120s1_ADDR 0x192
#define csr_RxClkcDlyTg3_ADDR 0x93
#define csr_SequenceReg0b35s1_ADDR 0x93
#define csr_SequenceReg0b120s2_ADDR 0x193
#define csr_SequenceReg0b35s2_ADDR 0x94
#define csr_SequenceReg0b121s0_ADDR 0x194
#define csr_SequenceReg0b36s0_ADDR 0x95
#define csr_SequenceReg0b121s1_ADDR 0x195
#define csr_ClrWakeupSticky_ADDR 0x95
#define csr_SequenceReg0b36s1_ADDR 0x96
#define csr_SequenceReg0b121s2_ADDR 0x196
#define csr_WakeupMask_ADDR 0x96
#define csr_SequenceReg0b36s2_ADDR 0x97
#define csr_CalBusy_ADDR 0x97
#define csr_SequenceReg0b37s0_ADDR 0x98
#define csr_CalMisc2_ADDR 0x98
#define csr_SequenceReg0b37s1_ADDR 0x99
#define csr_MicroReset_ADDR 0x99
#define csr_SequenceReg0b37s2_ADDR 0x9a
#define csr_CalMisc_ADDR 0x9a
#define csr_SequenceReg0b38s0_ADDR 0x9b
#define csr_CalVRefs_ADDR 0x9b
#define csr_SequenceReg0b38s1_ADDR 0x9c
#define csr_CalCmpr5_ADDR 0x9c
#define csr_SequenceReg0b38s2_ADDR 0x9d
#define csr_CalNInt_ADDR 0x9d
#define csr_SequenceReg0b39s0_ADDR 0x9e
#define csr_CalPExt_ADDR 0x9e
#define csr_SequenceReg0b39s1_ADDR 0x9f
#define csr_SequenceReg0b39s2_ADDR 0xa0
#define csr_Dq0LnSel_ADDR 0xa0
#define csr_SequenceReg0b40s0_ADDR 0xa1
#define csr_Dq1LnSel_ADDR 0xa1
#define csr_SequenceReg0b40s1_ADDR 0xa2
#define csr_Dq2LnSel_ADDR 0xa2
#define csr_SequenceReg0b40s2_ADDR 0xa3
#define csr_Dq3LnSel_ADDR 0xa3
#define csr_SequenceReg0b41s0_ADDR 0xa4
#define csr_Dq4LnSel_ADDR 0xa4
#define csr_SequenceReg0b41s1_ADDR 0xa5
#define csr_Dq5LnSel_ADDR 0xa5
#define csr_SequenceReg0b41s2_ADDR 0xa6
#define csr_Dq6LnSel_ADDR 0xa6
#define csr_SequenceReg0b42s0_ADDR 0xa7
#define csr_Dq7LnSel_ADDR 0xa7
#define csr_SequenceReg0b42s1_ADDR 0xa8
#define csr_CalCmpInvert_ADDR 0xa8
#define csr_SequenceReg0b42s2_ADDR 0xa9
#define csr_SequenceReg0b43s0_ADDR 0xaa
#define csr_PptCtlStatic_ADDR 0xaa
#define csr_SequenceReg0b43s1_ADDR 0xab
#define csr_PptCtlDyn_ADDR 0xab
#define csr_SequenceReg0b43s2_ADDR 0xac
#define csr_PptInfo_ADDR 0xac
#define csr_SequenceReg0b44s0_ADDR 0xad
#define csr_PptRxEnEvnt_ADDR 0xad
#define csr_SequenceReg0b44s1_ADDR 0xae
#define csr_CalCmpanaCntrl_ADDR 0xae
#define csr_PptDqsCntInvTrnTg0_ADDR 0xae
#define csr_SequenceReg0b44s2_ADDR 0xaf
#define csr_PptDqsCntInvTrnTg1_ADDR 0xaf
#define csr_SequenceReg0b45s0_ADDR 0xb0
#define csr_DfiRdDataCsDestMap_ADDR 0xb0
#define csr_DtsmBlankingCtrl_ADDR 0xb1
#define csr_SequenceReg0b45s1_ADDR 0xb1
#define csr_Tsm0_ADDR 0xb2
#define csr_SequenceReg0b45s2_ADDR 0xb2
#define csr_VrefInGlobal_ADDR 0xb2
#define csr_Tsm1_ADDR 0xb3
#define csr_SequenceReg0b46s0_ADDR 0xb3
#define csr_Tsm2_ADDR 0xb4
#define csr_SequenceReg0b46s1_ADDR 0xb4
#define csr_DfiWrDataCsDestMap_ADDR 0xb4
#define csr_Tsm3_ADDR 0xb5
#define csr_SequenceReg0b46s2_ADDR 0xb5
#define csr_MasUpdGoodCtr_ADDR 0xb5
#define csr_TxChkDataSelects_ADDR 0xb6
#define csr_SequenceReg0b47s0_ADDR 0xb6
#define csr_PhyUpd0GoodCtr_ADDR 0xb6
#define csr_DtsmUpThldXingInd_ADDR 0xb7
#define csr_SequenceReg0b47s1_ADDR 0xb7
#define csr_PhyUpd1GoodCtr_ADDR 0xb7
#define csr_DtsmLoThldXingInd_ADDR 0xb8
#define csr_SequenceReg0b47s2_ADDR 0xb8
#define csr_CtlUpd0GoodCtr_ADDR 0xb8
#define csr_DbyteAllDtsmCtrl0_ADDR 0xb9
#define csr_SequenceReg0b48s0_ADDR 0xb9
#define csr_CtlUpd1GoodCtr_ADDR 0xb9
#define csr_DbyteAllDtsmCtrl1_ADDR 0xba
#define csr_SequenceReg0b48s1_ADDR 0xba
#define csr_MasUpdFailCtr_ADDR 0xba
#define csr_DbyteAllDtsmCtrl2_ADDR 0xbb
#define csr_SequenceReg0b48s2_ADDR 0xbb
#define csr_PhyUpd0FailCtr_ADDR 0xbb
#define csr_SequenceReg0b49s0_ADDR 0xbc
#define csr_PhyUpd1FailCtr_ADDR 0xbc
#define csr_SequenceReg0b49s1_ADDR 0xbd
#define csr_PhyPerfCtrEnable_ADDR 0xbd
#define csr_SequenceReg0b49s2_ADDR 0xbe
#define csr_DfiWrRdDataCsConfig_ADDR 0xbe
#define csr_SequenceReg0b50s0_ADDR 0xbf
#define csr_TxDqDlyTg0_ADDR 0xc0
#define csr_SequenceReg0b50s1_ADDR 0xc0
#define csr_AcsmCtrl23_ADDR 0xc0
#define csr_TxDqDlyTg1_ADDR 0xc1
#define csr_SequenceReg0b50s2_ADDR 0xc1
#define csr_TxDqDlyTg2_ADDR 0xc2
#define csr_SequenceReg0b51s0_ADDR 0xc2
#define csr_AcsmCkeVal_ADDR 0xc2
#define csr_TxDqDlyTg3_ADDR 0xc3
#define csr_SequenceReg0b51s1_ADDR 0xc3
#define csr_PllPwrDn_ADDR 0xc3
#define csr_SequenceReg0b51s2_ADDR 0xc4
#define csr_PllReset_ADDR 0xc4
#define csr_SequenceReg0b52s0_ADDR 0xc5
#define csr_PllCtrl2_ADDR 0xc5
#define csr_SequenceReg0b52s1_ADDR 0xc6
#define csr_PllCtrl0_ADDR 0xc6
#define csr_SequenceReg0b52s2_ADDR 0xc7
#define csr_PllCtrl1_ADDR 0xc7
#define csr_SequenceReg0b53s0_ADDR 0xc8
#define csr_LowSpeedClockDivider_ADDR 0xc8
#define csr_PllTst_ADDR 0xc8
#define csr_SequenceReg0b53s1_ADDR 0xc9
#define csr_PllLockStatus_ADDR 0xc9
#define csr_SequenceReg0b53s2_ADDR 0xca
#define csr_PllTestMode_ADDR 0xca
#define csr_SequenceReg0b54s0_ADDR 0xcb
#define csr_PllCtrl3_ADDR 0xcb
#define csr_SequenceReg0b54s1_ADDR 0xcc
#define csr_PllCtrl4_ADDR 0xcc
#define csr_SequenceReg0b54s2_ADDR 0xcd
#define csr_PllEndofCal_ADDR 0xcd
#define csr_SequenceReg0b55s0_ADDR 0xce
#define csr_PllStandbyEff_ADDR 0xce
#define csr_SequenceReg0b55s1_ADDR 0xcf
#define csr_PllDacValOut_ADDR 0xcf
#define csr_TxDqsDlyTg0_ADDR 0xd0
#define csr_SequenceReg0b55s2_ADDR 0xd0
#define csr_DlyTestSeq_ADDR 0xd0
#define csr_AcsmCsMapCtrl0_ADDR 0xd0
#define csr_TxDqsDlyTg1_ADDR 0xd1
#define csr_SequenceReg0b56s0_ADDR 0xd1
#define csr_DlyTestRingSelDb_ADDR 0xd1
#define csr_AcsmCsMapCtrl1_ADDR 0xd1
#define csr_TxDqsDlyTg2_ADDR 0xd2
#define csr_SequenceReg0b56s1_ADDR 0xd2
#define csr_DlyTestRingSelAc_ADDR 0xd2
#define csr_AcsmCsMapCtrl2_ADDR 0xd2
#define csr_TxDqsDlyTg3_ADDR 0xd3
#define csr_SequenceReg0b56s2_ADDR 0xd3
#define csr_DlyTestCntDfiClkIV_ADDR 0xd3
#define csr_AcsmCsMapCtrl3_ADDR 0xd3
#define csr_SequenceReg0b57s0_ADDR 0xd4
#define csr_DlyTestCntDfiClk_ADDR 0xd4
#define csr_AcsmCsMapCtrl4_ADDR 0xd4
#define csr_SequenceReg0b57s1_ADDR 0xd5
#define csr_DlyTestCntRingOscDb0_ADDR 0xd5
#define csr_AcsmCsMapCtrl5_ADDR 0xd5
#define csr_SequenceReg0b57s2_ADDR 0xd6
#define csr_DlyTestCntRingOscDb1_ADDR 0xd6
#define csr_AcsmCsMapCtrl6_ADDR 0xd6
#define csr_SequenceReg0b58s0_ADDR 0xd7
#define csr_DlyTestCntRingOscDb2_ADDR 0xd7
#define csr_AcsmCsMapCtrl7_ADDR 0xd7
#define csr_SequenceReg0b58s1_ADDR 0xd8
#define csr_DlyTestCntRingOscDb3_ADDR 0xd8
#define csr_AcsmCsMapCtrl8_ADDR 0xd8
#define csr_SequenceReg0b58s2_ADDR 0xd9
#define csr_DlyTestCntRingOscDb4_ADDR 0xd9
#define csr_AcsmCsMapCtrl9_ADDR 0xd9
#define csr_SequenceReg0b59s0_ADDR 0xda
#define csr_DlyTestCntRingOscDb5_ADDR 0xda
#define csr_AcsmCsMapCtrl10_ADDR 0xda
#define csr_SequenceReg0b59s1_ADDR 0xdb
#define csr_DlyTestCntRingOscDb6_ADDR 0xdb
#define csr_AcsmCsMapCtrl11_ADDR 0xdb
#define csr_SequenceReg0b59s2_ADDR 0xdc
#define csr_DlyTestCntRingOscDb7_ADDR 0xdc
#define csr_AcsmCsMapCtrl12_ADDR 0xdc
#define csr_SequenceReg0b60s0_ADDR 0xdd
#define csr_DlyTestCntRingOscDb8_ADDR 0xdd
#define csr_AcsmCsMapCtrl13_ADDR 0xdd
#define csr_SequenceReg0b60s1_ADDR 0xde
#define csr_DlyTestCntRingOscDb9_ADDR 0xde
#define csr_AcsmCsMapCtrl14_ADDR 0xde
#define csr_SequenceReg0b60s2_ADDR 0xdf
#define csr_DlyTestCntRingOscAc_ADDR 0xdf
#define csr_AcsmCsMapCtrl15_ADDR 0xdf
#define csr_SequenceReg0b61s0_ADDR 0xe0
#define csr_MstLcdlDbgCntl_ADDR 0xe0
#define csr_AcsmOdtCtrl0_ADDR 0xe0
#define csr_SequenceReg0b61s1_ADDR 0xe1
#define csr_MstLcdl0DbgRes_ADDR 0xe1
#define csr_AcsmOdtCtrl1_ADDR 0xe1
#define csr_SequenceReg0b61s2_ADDR 0xe2
#define csr_MstLcdl1DbgRes_ADDR 0xe2
#define csr_AcsmOdtCtrl2_ADDR 0xe2
#define csr_SequenceReg0b62s0_ADDR 0xe3
#define csr_LcdlDbgCntl_ADDR 0xe3
#define csr_AcsmOdtCtrl3_ADDR 0xe3
#define csr_SequenceReg0b62s1_ADDR 0xe4
#define csr_DxLcdlStatus_ADDR 0xe4
#define csr_AcLcdlStatus_ADDR 0xe4
#define csr_AcsmOdtCtrl4_ADDR 0xe4
#define csr_SequenceReg0b62s2_ADDR 0xe5
#define csr_AcsmOdtCtrl5_ADDR 0xe5
#define csr_SequenceReg0b63s0_ADDR 0xe6
#define csr_AcsmOdtCtrl6_ADDR 0xe6
#define csr_SequenceReg0b63s1_ADDR 0xe7
#define csr_SequencerOverride_ADDR 0xe7
#define csr_AcsmOdtCtrl7_ADDR 0xe7
#define csr_SequenceReg0b63s2_ADDR 0xe8
#define csr_AcsmOdtCtrl8_ADDR 0xe8
#define csr_SequenceReg0b64s0_ADDR 0xe9
#define csr_AcsmCtrl16_ADDR 0xe9
#define csr_SequenceReg0b64s1_ADDR 0xea
#define csr_LowSpeedClockStopVal_ADDR 0xea
#define csr_SequenceReg0b64s2_ADDR 0xeb
#define csr_AcsmCtrl18_ADDR 0xeb
#define csr_SequenceReg0b65s0_ADDR 0xec
#define csr_AcsmCtrl19_ADDR 0xec
#define csr_SequenceReg0b65s1_ADDR 0xed
#define csr_AcsmCtrl20_ADDR 0xed
#define csr_CUSTPUBREV_ADDR 0xed
#define csr_CUSTPHYREV_ADDR 0xed
#define csr_SequenceReg0b65s2_ADDR 0xee
#define csr_AcsmCtrl21_ADDR 0xee
#define csr_PUBREV_ADDR 0xee
#define csr_PHYREV_ADDR 0xee
#define csr_SequenceReg0b66s0_ADDR 0xef
#define csr_LP3ExitSeq0BStartVector_ADDR 0xef
#define csr_AcsmCtrl22_ADDR 0xef
#define csr_SequenceReg0b66s1_ADDR 0xf0
#define csr_DfiFreqXlat0_ADDR 0xf0
#define csr_AcsmCtrl0_ADDR 0xf0
#define csr_SequenceReg0b66s2_ADDR 0xf1
#define csr_DfiFreqXlat1_ADDR 0xf1
#define csr_AcsmCtrl1_ADDR 0xf1
#define csr_SequenceReg0b67s0_ADDR 0xf2
#define csr_DfiFreqXlat2_ADDR 0xf2
#define csr_AcsmCtrl2_ADDR 0xf2
#define csr_SequenceReg0b67s1_ADDR 0xf3
#define csr_DfiFreqXlat3_ADDR 0xf3
#define csr_AcsmCtrl3_ADDR 0xf3
#define csr_SequenceReg0b67s2_ADDR 0xf4
#define csr_DfiFreqXlat4_ADDR 0xf4
#define csr_AcsmCtrl4_ADDR 0xf4
#define csr_SequenceReg0b68s0_ADDR 0xf5
#define csr_DfiFreqXlat5_ADDR 0xf5
#define csr_AcsmCtrl5_ADDR 0xf5
#define csr_SequenceReg0b68s1_ADDR 0xf6
#define csr_DfiFreqXlat6_ADDR 0xf6
#define csr_AcsmCtrl6_ADDR 0xf6
#define csr_SequenceReg0b68s2_ADDR 0xf7
#define csr_DfiFreqXlat7_ADDR 0xf7
#define csr_AcsmCtrl7_ADDR 0xf7
#define csr_SequenceReg0b69s0_ADDR 0xf8
#define csr_TxRdPtrInit_ADDR 0xf8
#define csr_AcsmCtrl8_ADDR 0xf8
#define csr_SequenceReg0b69s1_ADDR 0xf9
#define csr_DfiInitComplete_ADDR 0xf9
#define csr_AcsmCtrl9_ADDR 0xf9
#define csr_SequenceReg0b69s2_ADDR 0xfa
#define csr_DfiInitCompleteShadow_ADDR 0xfa
#define csr_AcsmCtrl10_ADDR 0xfa
#define csr_DfiFreqRatio_ADDR 0xfa
#define csr_SequenceReg0b70s0_ADDR 0xfb
#define csr_AcsmCtrl11_ADDR 0xfb
#define csr_RxFifoChecks_ADDR 0xfb
#define csr_SequenceReg0b70s1_ADDR 0xfc
#define csr_AcsmCtrl12_ADDR 0xfc
#define csr_SequenceReg0b70s2_ADDR 0xfd
#define csr_AcsmCtrl13_ADDR 0xfd
#define csr_SequenceReg0b71s0_ADDR 0xfe
#define csr_AcsmCtrl14_ADDR 0xfe
#define csr_MTestDtoCtrl_ADDR 0xff
#define csr_Seq0BFixedAddrBits_ADDR 0x2ff
#define csr_SequenceReg0b71s1_ADDR 0xff
#define csr_AcsmCtrl15_ADDR 0xff
#define csr_RxFifoInit_RANGE  1:0
#define csr_RxFifoInit_BITS   1:0
#define csr_RxFifoInit_MSB  1
#define csr_RxFifoInit_LSB  0
#define csr_RxFifoInit_MASK 0x3
#define csr_RxFifoInitPtr_RANGE  0:0
#define csr_RxFifoInitPtr_BITS   0:0
#define csr_RxFifoInitPtr_MSB  0
#define csr_RxFifoInitPtr_LSB  0
#define csr_RxFifoInitPtr_MASK 0x1
#define csr_InhibitRxFifoRd_RANGE  1:1
#define csr_InhibitRxFifoRd_BITS   0:0
#define csr_InhibitRxFifoRd_MSB  1
#define csr_InhibitRxFifoRd_LSB  1
#define csr_InhibitRxFifoRd_MASK 0x2
#define csr_PreSequenceReg0b0s0_RANGE  15:0
#define csr_PreSequenceReg0b0s0_BITS   15:0
#define csr_PreSequenceReg0b0s0_MSB  15
#define csr_PreSequenceReg0b0s0_LSB  0
#define csr_PreSequenceReg0b0s0_MASK 0xffff
#define csr_SequenceReg0b71s2_RANGE  8:0
#define csr_SequenceReg0b71s2_BITS   8:0
#define csr_SequenceReg0b71s2_MSB  8
#define csr_SequenceReg0b71s2_LSB  0
#define csr_SequenceReg0b71s2_MASK 0x1ff
#define csr_AcsmSeq0x0_RANGE  15:0
#define csr_AcsmSeq0x0_BITS   15:0
#define csr_AcsmSeq0x0_MSB  15
#define csr_AcsmSeq0x0_LSB  0
#define csr_AcsmSeq0x0_MASK 0xffff
#define csr_AcsmMclkDly0_RANGE  7:0
#define csr_AcsmMclkDly0_BITS   7:0
#define csr_AcsmMclkDly0_MSB  7
#define csr_AcsmMclkDly0_LSB  0
#define csr_AcsmMclkDly0_MASK 0xff
#define csr_AcsmDdrWe0_RANGE  8:8
#define csr_AcsmDdrWe0_BITS   0:0
#define csr_AcsmDdrWe0_MSB  8
#define csr_AcsmDdrWe0_LSB  8
#define csr_AcsmDdrWe0_MASK 0x100
#define csr_AcsmDdrCas0_RANGE  9:9
#define csr_AcsmDdrCas0_BITS   0:0
#define csr_AcsmDdrCas0_MSB  9
#define csr_AcsmDdrCas0_LSB  9
#define csr_AcsmDdrCas0_MASK 0x200
#define csr_AcsmDdrRas0_RANGE  10:10
#define csr_AcsmDdrRas0_BITS   0:0
#define csr_AcsmDdrRas0_MSB  10
#define csr_AcsmDdrRas0_LSB  10
#define csr_AcsmDdrRas0_MASK 0x400
#define csr_AcsmDdrCkeSet0_RANGE  11:11
#define csr_AcsmDdrCkeSet0_BITS   0:0
#define csr_AcsmDdrCkeSet0_MSB  11
#define csr_AcsmDdrCkeSet0_LSB  11
#define csr_AcsmDdrCkeSet0_MASK 0x800
#define csr_AcsmDdrCkeClr0_RANGE  12:12
#define csr_AcsmDdrCkeClr0_BITS   0:0
#define csr_AcsmDdrCkeClr0_MSB  12
#define csr_AcsmDdrCkeClr0_LSB  12
#define csr_AcsmDdrCkeClr0_MASK 0x1000
#define csr_AcsmSeqGateCmd0_RANGE  13:13
#define csr_AcsmSeqGateCmd0_BITS   0:0
#define csr_AcsmSeqGateCmd0_MSB  13
#define csr_AcsmSeqGateCmd0_LSB  13
#define csr_AcsmSeqGateCmd0_MASK 0x2000
#define csr_AcsmSeqTerm0_RANGE  14:14
#define csr_AcsmSeqTerm0_BITS   0:0
#define csr_AcsmSeqTerm0_MSB  14
#define csr_AcsmSeqTerm0_LSB  14
#define csr_AcsmSeqTerm0_MASK 0x4000
#define csr_AcsmLp3Ca30_RANGE  15:15
#define csr_AcsmLp3Ca30_BITS   0:0
#define csr_AcsmLp3Ca30_MSB  15
#define csr_AcsmLp3Ca30_LSB  15
#define csr_AcsmLp3Ca30_MASK 0x8000
#define csr_DbyteMiscMode_RANGE  2:2
#define csr_DbyteMiscMode_BITS   0:0
#define csr_DbyteMiscMode_MSB  2
#define csr_DbyteMiscMode_LSB  2
#define csr_DbyteMiscMode_MASK 0x4
#define csr_DByteDisable_RANGE  2:2
#define csr_DByteDisable_BITS   0:0
#define csr_DByteDisable_MSB  2
#define csr_DByteDisable_LSB  2
#define csr_DByteDisable_MASK 0x4
#define csr_MicroContMuxSel_RANGE  0:0
#define csr_MicroContMuxSel_BITS   0:0
#define csr_MicroContMuxSel_MSB  0
#define csr_MicroContMuxSel_LSB  0
#define csr_MicroContMuxSel_MASK 0x1
#define csr_MapCAA0toDfi_RANGE  3:0
#define csr_MapCAA0toDfi_BITS   3:0
#define csr_MapCAA0toDfi_MSB  3
#define csr_MapCAA0toDfi_LSB  0
#define csr_MapCAA0toDfi_MASK 0xf
#define csr_ForceClkDisable_RANGE  3:0
#define csr_ForceClkDisable_BITS   3:0
#define csr_ForceClkDisable_MSB  3
#define csr_ForceClkDisable_LSB  0
#define csr_ForceClkDisable_MASK 0xf
#define csr_TsmByte0_RANGE  15:0
#define csr_TsmByte0_BITS   15:0
#define csr_TsmByte0_MSB  15
#define csr_TsmByte0_LSB  0
#define csr_TsmByte0_MASK 0xffff
#define csr_PerPhTrainEn_RANGE  0:0
#define csr_PerPhTrainEn_BITS   0:0
#define csr_PerPhTrainEn_MSB  0
#define csr_PerPhTrainEn_LSB  0
#define csr_PerPhTrainEn_MASK 0x1
#define csr_EyeInc_RANGE  1:1
#define csr_EyeInc_BITS   0:0
#define csr_EyeInc_MSB  1
#define csr_EyeInc_LSB  1
#define csr_EyeInc_MASK 0x2
#define csr_EdgeInc_RANGE  2:2
#define csr_EdgeInc_BITS   0:0
#define csr_EdgeInc_MSB  2
#define csr_EdgeInc_LSB  2
#define csr_EdgeInc_MASK 0x4
#define csr_EdgeEyeMxSel_RANGE  3:3
#define csr_EdgeEyeMxSel_BITS   0:0
#define csr_EdgeEyeMxSel_MSB  3
#define csr_EdgeEyeMxSel_LSB  3
#define csr_EdgeEyeMxSel_MASK 0x8
#define csr_TsmByte0Rsvd_RANGE  5:4
#define csr_TsmByte0Rsvd_BITS   1:0
#define csr_TsmByte0Rsvd_MSB  5
#define csr_TsmByte0Rsvd_LSB  4
#define csr_TsmByte0Rsvd_MASK 0x30
#define csr_DimmBroadInc_RANGE  6:6
#define csr_DimmBroadInc_BITS   0:0
#define csr_DimmBroadInc_MSB  6
#define csr_DimmBroadInc_LSB  6
#define csr_DimmBroadInc_MASK 0x40
#define csr_DimmInc_RANGE  8:7
#define csr_DimmInc_BITS   1:0
#define csr_DimmInc_MSB  8
#define csr_DimmInc_LSB  7
#define csr_DimmInc_MASK 0x180
#define csr_CoarseInc_RANGE  9:9
#define csr_CoarseInc_BITS   0:0
#define csr_CoarseInc_MSB  9
#define csr_CoarseInc_LSB  9
#define csr_CoarseInc_MASK 0x200
#define csr_DelayInc_RANGE  10:10
#define csr_DelayInc_BITS   0:0
#define csr_DelayInc_MSB  10
#define csr_DelayInc_LSB  10
#define csr_DelayInc_MASK 0x400
#define csr_RxInc_RANGE  11:11
#define csr_RxInc_BITS   0:0
#define csr_RxInc_MSB  11
#define csr_RxInc_LSB  11
#define csr_RxInc_MASK 0x800
#define csr_RxPerTrain_RANGE  12:12
#define csr_RxPerTrain_BITS   0:0
#define csr_RxPerTrain_MSB  12
#define csr_RxPerTrain_LSB  12
#define csr_RxPerTrain_MASK 0x1000
#define csr_TxPerTrain_RANGE  13:13
#define csr_TxPerTrain_BITS   0:0
#define csr_TxPerTrain_MSB  13
#define csr_TxPerTrain_LSB  13
#define csr_TxPerTrain_MASK 0x2000
#define csr_DmTrain_RANGE  14:14
#define csr_DmTrain_BITS   0:0
#define csr_DmTrain_MSB  14
#define csr_DmTrain_LSB  14
#define csr_DmTrain_MASK 0x4000
#define csr_WrLevTrain_RANGE  15:15
#define csr_WrLevTrain_BITS   0:0
#define csr_WrLevTrain_MSB  15
#define csr_WrLevTrain_LSB  15
#define csr_WrLevTrain_MASK 0x8000
#define csr_PreSequenceReg0b0s1_RANGE  15:0
#define csr_PreSequenceReg0b0s1_BITS   15:0
#define csr_PreSequenceReg0b0s1_MSB  15
#define csr_PreSequenceReg0b0s1_LSB  0
#define csr_PreSequenceReg0b0s1_MASK 0xffff
#define csr_Seq0BGPR1_RANGE  15:0
#define csr_Seq0BGPR1_BITS   15:0
#define csr_Seq0BGPR1_MSB  15
#define csr_Seq0BGPR1_LSB  0
#define csr_Seq0BGPR1_MASK 0xffff
#define csr_SequenceReg0b72s0_RANGE  15:0
#define csr_SequenceReg0b72s0_BITS   15:0
#define csr_SequenceReg0b72s0_MSB  15
#define csr_SequenceReg0b72s0_LSB  0
#define csr_SequenceReg0b72s0_MASK 0xffff
#define csr_AcsmSeq0x1_RANGE  15:0
#define csr_AcsmSeq0x1_BITS   15:0
#define csr_AcsmSeq0x1_MSB  15
#define csr_AcsmSeq0x1_LSB  0
#define csr_AcsmSeq0x1_MASK 0xffff
#define csr_AcsmMclkDly1_RANGE  7:0
#define csr_AcsmMclkDly1_BITS   7:0
#define csr_AcsmMclkDly1_MSB  7
#define csr_AcsmMclkDly1_LSB  0
#define csr_AcsmMclkDly1_MASK 0xff
#define csr_AcsmDdrWe1_RANGE  8:8
#define csr_AcsmDdrWe1_BITS   0:0
#define csr_AcsmDdrWe1_MSB  8
#define csr_AcsmDdrWe1_LSB  8
#define csr_AcsmDdrWe1_MASK 0x100
#define csr_AcsmDdrCas1_RANGE  9:9
#define csr_AcsmDdrCas1_BITS   0:0
#define csr_AcsmDdrCas1_MSB  9
#define csr_AcsmDdrCas1_LSB  9
#define csr_AcsmDdrCas1_MASK 0x200
#define csr_AcsmDdrRas1_RANGE  10:10
#define csr_AcsmDdrRas1_BITS   0:0
#define csr_AcsmDdrRas1_MSB  10
#define csr_AcsmDdrRas1_LSB  10
#define csr_AcsmDdrRas1_MASK 0x400
#define csr_AcsmDdrCkeSet1_RANGE  11:11
#define csr_AcsmDdrCkeSet1_BITS   0:0
#define csr_AcsmDdrCkeSet1_MSB  11
#define csr_AcsmDdrCkeSet1_LSB  11
#define csr_AcsmDdrCkeSet1_MASK 0x800
#define csr_AcsmDdrCkeClr1_RANGE  12:12
#define csr_AcsmDdrCkeClr1_BITS   0:0
#define csr_AcsmDdrCkeClr1_MSB  12
#define csr_AcsmDdrCkeClr1_LSB  12
#define csr_AcsmDdrCkeClr1_MASK 0x1000
#define csr_AcsmSeqGateCmd1_RANGE  13:13
#define csr_AcsmSeqGateCmd1_BITS   0:0
#define csr_AcsmSeqGateCmd1_MSB  13
#define csr_AcsmSeqGateCmd1_LSB  13
#define csr_AcsmSeqGateCmd1_MASK 0x2000
#define csr_AcsmSeqTerm1_RANGE  14:14
#define csr_AcsmSeqTerm1_BITS   0:0
#define csr_AcsmSeqTerm1_MSB  14
#define csr_AcsmSeqTerm1_LSB  14
#define csr_AcsmSeqTerm1_MASK 0x4000
#define csr_AcsmLp3Ca31_RANGE  15:15
#define csr_AcsmLp3Ca31_BITS   0:0
#define csr_AcsmLp3Ca31_MSB  15
#define csr_AcsmLp3Ca31_LSB  15
#define csr_AcsmLp3Ca31_MASK 0x8000
#define csr_MapCAA1toDfi_RANGE  3:0
#define csr_MapCAA1toDfi_BITS   3:0
#define csr_MapCAA1toDfi_MSB  3
#define csr_MapCAA1toDfi_LSB  0
#define csr_MapCAA1toDfi_MASK 0xf
#define csr_ClockingCtrl_RANGE  1:0
#define csr_ClockingCtrl_BITS   1:0
#define csr_ClockingCtrl_MSB  1
#define csr_ClockingCtrl_LSB  0
#define csr_ClockingCtrl_MASK 0x3
#define csr_PclkEnAsyncCtrl_RANGE  0:0
#define csr_PclkEnAsyncCtrl_BITS   0:0
#define csr_PclkEnAsyncCtrl_MSB  0
#define csr_PclkEnAsyncCtrl_LSB  0
#define csr_PclkEnAsyncCtrl_MASK 0x1
#define csr_DllTrackEnCtrl_RANGE  1:1
#define csr_DllTrackEnCtrl_BITS   0:0
#define csr_DllTrackEnCtrl_MSB  1
#define csr_DllTrackEnCtrl_LSB  1
#define csr_DllTrackEnCtrl_MASK 0x2
#define csr_TrainingParam_RANGE  15:0
#define csr_TrainingParam_BITS   15:0
#define csr_TrainingParam_MSB  15
#define csr_TrainingParam_LSB  0
#define csr_TrainingParam_MASK 0xffff
#define csr_EnDynRateReduction_RANGE  0:0
#define csr_EnDynRateReduction_BITS   0:0
#define csr_EnDynRateReduction_MSB  0
#define csr_EnDynRateReduction_LSB  0
#define csr_EnDynRateReduction_MASK 0x1
#define csr_TrainingParam01Rsvd_RANGE  1:1
#define csr_TrainingParam01Rsvd_BITS   0:0
#define csr_TrainingParam01Rsvd_MSB  1
#define csr_TrainingParam01Rsvd_LSB  1
#define csr_TrainingParam01Rsvd_MASK 0x2
#define csr_TrainEnRxClk_RANGE  2:2
#define csr_TrainEnRxClk_BITS   0:0
#define csr_TrainEnRxClk_MSB  2
#define csr_TrainEnRxClk_LSB  2
#define csr_TrainEnRxClk_MASK 0x4
#define csr_TrainEnRxEn_RANGE  3:3
#define csr_TrainEnRxEn_BITS   0:0
#define csr_TrainEnRxEn_MSB  3
#define csr_TrainEnRxEn_LSB  3
#define csr_TrainEnRxEn_MASK 0x8
#define csr_TrainEnTxDqs_RANGE  4:4
#define csr_TrainEnTxDqs_BITS   0:0
#define csr_TrainEnTxDqs_MSB  4
#define csr_TrainEnTxDqs_LSB  4
#define csr_TrainEnTxDqs_MASK 0x10
#define csr_TrainEnTxDq_RANGE  5:5
#define csr_TrainEnTxDq_BITS   0:0
#define csr_TrainEnTxDq_MSB  5
#define csr_TrainEnTxDq_LSB  5
#define csr_TrainEnTxDq_MASK 0x20
#define csr_TrainEnVrefDAC1_RANGE  6:6
#define csr_TrainEnVrefDAC1_BITS   0:0
#define csr_TrainEnVrefDAC1_MSB  6
#define csr_TrainEnVrefDAC1_LSB  6
#define csr_TrainEnVrefDAC1_MASK 0x40
#define csr_TrainEnVrefDAC0_RANGE  7:7
#define csr_TrainEnVrefDAC0_BITS   0:0
#define csr_TrainEnVrefDAC0_MSB  7
#define csr_TrainEnVrefDAC0_LSB  7
#define csr_TrainEnVrefDAC0_MASK 0x80
#define csr_TrainEnRxPBD_RANGE  8:8
#define csr_TrainEnRxPBD_BITS   0:0
#define csr_TrainEnRxPBD_MSB  8
#define csr_TrainEnRxPBD_LSB  8
#define csr_TrainEnRxPBD_MASK 0x100
#define csr_RollIntoCoarse_RANGE  9:9
#define csr_RollIntoCoarse_BITS   0:0
#define csr_RollIntoCoarse_MSB  9
#define csr_RollIntoCoarse_LSB  9
#define csr_RollIntoCoarse_MASK 0x200
#define csr_TrainUsingNativeDdlCntl_RANGE  10:10
#define csr_TrainUsingNativeDdlCntl_BITS   0:0
#define csr_TrainUsingNativeDdlCntl_MSB  10
#define csr_TrainUsingNativeDdlCntl_LSB  10
#define csr_TrainUsingNativeDdlCntl_MASK 0x400
#define csr_TrainingParam11Rsvd_RANGE  11:11
#define csr_TrainingParam11Rsvd_BITS   0:0
#define csr_TrainingParam11Rsvd_MSB  11
#define csr_TrainingParam11Rsvd_LSB  11
#define csr_TrainingParam11Rsvd_MASK 0x800
#define csr_TrainingParam12Rsvd_RANGE  12:12
#define csr_TrainingParam12Rsvd_BITS   0:0
#define csr_TrainingParam12Rsvd_MSB  12
#define csr_TrainingParam12Rsvd_LSB  12
#define csr_TrainingParam12Rsvd_MASK 0x1000
#define csr_IncDecRate_RANGE  15:13
#define csr_IncDecRate_BITS   2:0
#define csr_IncDecRate_MSB  15
#define csr_IncDecRate_LSB  13
#define csr_IncDecRate_MASK 0xe000
#define csr_PreSequenceReg0b0s2_RANGE  8:0
#define csr_PreSequenceReg0b0s2_BITS   8:0
#define csr_PreSequenceReg0b0s2_MSB  8
#define csr_PreSequenceReg0b0s2_LSB  0
#define csr_PreSequenceReg0b0s2_MASK 0x1ff
#define csr_Seq0BGPR2_RANGE  15:0
#define csr_Seq0BGPR2_BITS   15:0
#define csr_Seq0BGPR2_MSB  15
#define csr_Seq0BGPR2_LSB  0
#define csr_Seq0BGPR2_MASK 0xffff
#define csr_SequenceReg0b72s1_RANGE  15:0
#define csr_SequenceReg0b72s1_BITS   15:0
#define csr_SequenceReg0b72s1_MSB  15
#define csr_SequenceReg0b72s1_LSB  0
#define csr_SequenceReg0b72s1_MASK 0xffff
#define csr_AcsmSeq0x2_RANGE  15:0
#define csr_AcsmSeq0x2_BITS   15:0
#define csr_AcsmSeq0x2_MSB  15
#define csr_AcsmSeq0x2_LSB  0
#define csr_AcsmSeq0x2_MASK 0xffff
#define csr_AcsmMclkDly2_RANGE  7:0
#define csr_AcsmMclkDly2_BITS   7:0
#define csr_AcsmMclkDly2_MSB  7
#define csr_AcsmMclkDly2_LSB  0
#define csr_AcsmMclkDly2_MASK 0xff
#define csr_AcsmDdrWe2_RANGE  8:8
#define csr_AcsmDdrWe2_BITS   0:0
#define csr_AcsmDdrWe2_MSB  8
#define csr_AcsmDdrWe2_LSB  8
#define csr_AcsmDdrWe2_MASK 0x100
#define csr_AcsmDdrCas2_RANGE  9:9
#define csr_AcsmDdrCas2_BITS   0:0
#define csr_AcsmDdrCas2_MSB  9
#define csr_AcsmDdrCas2_LSB  9
#define csr_AcsmDdrCas2_MASK 0x200
#define csr_AcsmDdrRas2_RANGE  10:10
#define csr_AcsmDdrRas2_BITS   0:0
#define csr_AcsmDdrRas2_MSB  10
#define csr_AcsmDdrRas2_LSB  10
#define csr_AcsmDdrRas2_MASK 0x400
#define csr_AcsmDdrCkeSet2_RANGE  11:11
#define csr_AcsmDdrCkeSet2_BITS   0:0
#define csr_AcsmDdrCkeSet2_MSB  11
#define csr_AcsmDdrCkeSet2_LSB  11
#define csr_AcsmDdrCkeSet2_MASK 0x800
#define csr_AcsmDdrCkeClr2_RANGE  12:12
#define csr_AcsmDdrCkeClr2_BITS   0:0
#define csr_AcsmDdrCkeClr2_MSB  12
#define csr_AcsmDdrCkeClr2_LSB  12
#define csr_AcsmDdrCkeClr2_MASK 0x1000
#define csr_AcsmSeqGateCmd2_RANGE  13:13
#define csr_AcsmSeqGateCmd2_BITS   0:0
#define csr_AcsmSeqGateCmd2_MSB  13
#define csr_AcsmSeqGateCmd2_LSB  13
#define csr_AcsmSeqGateCmd2_MASK 0x2000
#define csr_AcsmSeqTerm2_RANGE  14:14
#define csr_AcsmSeqTerm2_BITS   0:0
#define csr_AcsmSeqTerm2_MSB  14
#define csr_AcsmSeqTerm2_LSB  14
#define csr_AcsmSeqTerm2_MASK 0x4000
#define csr_AcsmLp3Ca32_RANGE  15:15
#define csr_AcsmLp3Ca32_BITS   0:0
#define csr_AcsmLp3Ca32_MSB  15
#define csr_AcsmLp3Ca32_LSB  15
#define csr_AcsmLp3Ca32_MASK 0x8000
#define csr_MapCAA2toDfi_RANGE  3:0
#define csr_MapCAA2toDfi_BITS   3:0
#define csr_MapCAA2toDfi_MSB  3
#define csr_MapCAA2toDfi_LSB  0
#define csr_MapCAA2toDfi_MASK 0xf
#define csr_UseDqsEnReplica_RANGE  0:0
#define csr_UseDqsEnReplica_BITS   0:0
#define csr_UseDqsEnReplica_MSB  0
#define csr_UseDqsEnReplica_LSB  0
#define csr_UseDqsEnReplica_MASK 0x1
#define csr_ForceInternalUpdate_RANGE  0:0
#define csr_ForceInternalUpdate_BITS   0:0
#define csr_ForceInternalUpdate_MSB  0
#define csr_ForceInternalUpdate_LSB  0
#define csr_ForceInternalUpdate_MASK 0x1
#define csr_PreSequenceReg0b1s0_RANGE  15:0
#define csr_PreSequenceReg0b1s0_BITS   15:0
#define csr_PreSequenceReg0b1s0_MSB  15
#define csr_PreSequenceReg0b1s0_LSB  0
#define csr_PreSequenceReg0b1s0_MASK 0xffff
#define csr_Seq0BGPR3_RANGE  15:0
#define csr_Seq0BGPR3_BITS   15:0
#define csr_Seq0BGPR3_MSB  15
#define csr_Seq0BGPR3_LSB  0
#define csr_Seq0BGPR3_MASK 0xffff
#define csr_SequenceReg0b72s2_RANGE  8:0
#define csr_SequenceReg0b72s2_BITS   8:0
#define csr_SequenceReg0b72s2_MSB  8
#define csr_SequenceReg0b72s2_LSB  0
#define csr_SequenceReg0b72s2_MASK 0x1ff
#define csr_AcsmSeq0x3_RANGE  15:0
#define csr_AcsmSeq0x3_BITS   15:0
#define csr_AcsmSeq0x3_MSB  15
#define csr_AcsmSeq0x3_LSB  0
#define csr_AcsmSeq0x3_MASK 0xffff
#define csr_AcsmMclkDly3_RANGE  7:0
#define csr_AcsmMclkDly3_BITS   7:0
#define csr_AcsmMclkDly3_MSB  7
#define csr_AcsmMclkDly3_LSB  0
#define csr_AcsmMclkDly3_MASK 0xff
#define csr_AcsmDdrWe3_RANGE  8:8
#define csr_AcsmDdrWe3_BITS   0:0
#define csr_AcsmDdrWe3_MSB  8
#define csr_AcsmDdrWe3_LSB  8
#define csr_AcsmDdrWe3_MASK 0x100
#define csr_AcsmDdrCas3_RANGE  9:9
#define csr_AcsmDdrCas3_BITS   0:0
#define csr_AcsmDdrCas3_MSB  9
#define csr_AcsmDdrCas3_LSB  9
#define csr_AcsmDdrCas3_MASK 0x200
#define csr_AcsmDdrRas3_RANGE  10:10
#define csr_AcsmDdrRas3_BITS   0:0
#define csr_AcsmDdrRas3_MSB  10
#define csr_AcsmDdrRas3_LSB  10
#define csr_AcsmDdrRas3_MASK 0x400
#define csr_AcsmDdrCkeSet3_RANGE  11:11
#define csr_AcsmDdrCkeSet3_BITS   0:0
#define csr_AcsmDdrCkeSet3_MSB  11
#define csr_AcsmDdrCkeSet3_LSB  11
#define csr_AcsmDdrCkeSet3_MASK 0x800
#define csr_AcsmDdrCkeClr3_RANGE  12:12
#define csr_AcsmDdrCkeClr3_BITS   0:0
#define csr_AcsmDdrCkeClr3_MSB  12
#define csr_AcsmDdrCkeClr3_LSB  12
#define csr_AcsmDdrCkeClr3_MASK 0x1000
#define csr_AcsmSeqGateCmd3_RANGE  13:13
#define csr_AcsmSeqGateCmd3_BITS   0:0
#define csr_AcsmSeqGateCmd3_MSB  13
#define csr_AcsmSeqGateCmd3_LSB  13
#define csr_AcsmSeqGateCmd3_MASK 0x2000
#define csr_AcsmSeqTerm3_RANGE  14:14
#define csr_AcsmSeqTerm3_BITS   0:0
#define csr_AcsmSeqTerm3_MSB  14
#define csr_AcsmSeqTerm3_LSB  14
#define csr_AcsmSeqTerm3_MASK 0x4000
#define csr_AcsmLp3Ca33_RANGE  15:15
#define csr_AcsmLp3Ca33_BITS   0:0
#define csr_AcsmLp3Ca33_MSB  15
#define csr_AcsmLp3Ca33_LSB  15
#define csr_AcsmLp3Ca33_MASK 0x8000
#define csr_MapCAA3toDfi_RANGE  3:0
#define csr_MapCAA3toDfi_BITS   3:0
#define csr_MapCAA3toDfi_MSB  3
#define csr_MapCAA3toDfi_LSB  0
#define csr_MapCAA3toDfi_MASK 0xf
#define csr_PhyConfig_RANGE  9:0
#define csr_PhyConfig_BITS   9:0
#define csr_PhyConfig_MSB  9
#define csr_PhyConfig_LSB  0
#define csr_PhyConfig_MASK 0x3ff
#define csr_PhyConfigAnibs_RANGE  3:0
#define csr_PhyConfigAnibs_BITS   3:0
#define csr_PhyConfigAnibs_MSB  3
#define csr_PhyConfigAnibs_LSB  0
#define csr_PhyConfigAnibs_MASK 0xf
#define csr_PhyConfigDbytes_RANGE  7:4
#define csr_PhyConfigDbytes_BITS   3:0
#define csr_PhyConfigDbytes_MSB  7
#define csr_PhyConfigDbytes_LSB  4
#define csr_PhyConfigDbytes_MASK 0xf0
#define csr_PhyConfigDfi_RANGE  9:8
#define csr_PhyConfigDfi_BITS   1:0
#define csr_PhyConfigDfi_MSB  9
#define csr_PhyConfigDfi_LSB  8
#define csr_PhyConfigDfi_MASK 0x300
#define csr_PreSequenceReg0b1s1_RANGE  15:0
#define csr_PreSequenceReg0b1s1_BITS   15:0
#define csr_PreSequenceReg0b1s1_MSB  15
#define csr_PreSequenceReg0b1s1_LSB  0
#define csr_PreSequenceReg0b1s1_MASK 0xffff
#define csr_Seq0BGPR4_RANGE  15:0
#define csr_Seq0BGPR4_BITS   15:0
#define csr_Seq0BGPR4_MSB  15
#define csr_Seq0BGPR4_LSB  0
#define csr_Seq0BGPR4_MASK 0xffff
#define csr_SequenceReg0b73s0_RANGE  15:0
#define csr_SequenceReg0b73s0_BITS   15:0
#define csr_SequenceReg0b73s0_MSB  15
#define csr_SequenceReg0b73s0_LSB  0
#define csr_SequenceReg0b73s0_MASK 0xffff
#define csr_AcsmSeq0x4_RANGE  15:0
#define csr_AcsmSeq0x4_BITS   15:0
#define csr_AcsmSeq0x4_MSB  15
#define csr_AcsmSeq0x4_LSB  0
#define csr_AcsmSeq0x4_MASK 0xffff
#define csr_AcsmMclkDly4_RANGE  7:0
#define csr_AcsmMclkDly4_BITS   7:0
#define csr_AcsmMclkDly4_MSB  7
#define csr_AcsmMclkDly4_LSB  0
#define csr_AcsmMclkDly4_MASK 0xff
#define csr_AcsmDdrWe4_RANGE  8:8
#define csr_AcsmDdrWe4_BITS   0:0
#define csr_AcsmDdrWe4_MSB  8
#define csr_AcsmDdrWe4_LSB  8
#define csr_AcsmDdrWe4_MASK 0x100
#define csr_AcsmDdrCas4_RANGE  9:9
#define csr_AcsmDdrCas4_BITS   0:0
#define csr_AcsmDdrCas4_MSB  9
#define csr_AcsmDdrCas4_LSB  9
#define csr_AcsmDdrCas4_MASK 0x200
#define csr_AcsmDdrRas4_RANGE  10:10
#define csr_AcsmDdrRas4_BITS   0:0
#define csr_AcsmDdrRas4_MSB  10
#define csr_AcsmDdrRas4_LSB  10
#define csr_AcsmDdrRas4_MASK 0x400
#define csr_AcsmDdrCkeSet4_RANGE  11:11
#define csr_AcsmDdrCkeSet4_BITS   0:0
#define csr_AcsmDdrCkeSet4_MSB  11
#define csr_AcsmDdrCkeSet4_LSB  11
#define csr_AcsmDdrCkeSet4_MASK 0x800
#define csr_AcsmDdrCkeClr4_RANGE  12:12
#define csr_AcsmDdrCkeClr4_BITS   0:0
#define csr_AcsmDdrCkeClr4_MSB  12
#define csr_AcsmDdrCkeClr4_LSB  12
#define csr_AcsmDdrCkeClr4_MASK 0x1000
#define csr_AcsmSeqGateCmd4_RANGE  13:13
#define csr_AcsmSeqGateCmd4_BITS   0:0
#define csr_AcsmSeqGateCmd4_MSB  13
#define csr_AcsmSeqGateCmd4_LSB  13
#define csr_AcsmSeqGateCmd4_MASK 0x2000
#define csr_AcsmSeqTerm4_RANGE  14:14
#define csr_AcsmSeqTerm4_BITS   0:0
#define csr_AcsmSeqTerm4_MSB  14
#define csr_AcsmSeqTerm4_LSB  14
#define csr_AcsmSeqTerm4_MASK 0x4000
#define csr_AcsmLp3Ca34_RANGE  15:15
#define csr_AcsmLp3Ca34_BITS   0:0
#define csr_AcsmLp3Ca34_MSB  15
#define csr_AcsmLp3Ca34_LSB  15
#define csr_AcsmLp3Ca34_MASK 0x8000
#define csr_DctShadowRegs_RANGE  0:0
#define csr_DctShadowRegs_BITS   0:0
#define csr_DctShadowRegs_MSB  0
#define csr_DctShadowRegs_LSB  0
#define csr_DctShadowRegs_MASK 0x1
#define csr_DctWriteProtShadow_RANGE  0:0
#define csr_DctWriteProtShadow_BITS   0:0
#define csr_DctWriteProtShadow_MSB  0
#define csr_DctWriteProtShadow_LSB  0
#define csr_DctWriteProtShadow_MASK 0x1
#define csr_UctShadowRegs_RANGE  1:0
#define csr_UctShadowRegs_BITS   1:0
#define csr_UctShadowRegs_MSB  1
#define csr_UctShadowRegs_LSB  0
#define csr_UctShadowRegs_MASK 0x3
#define csr_UctWriteProtShadow_RANGE  0:0
#define csr_UctWriteProtShadow_BITS   0:0
#define csr_UctWriteProtShadow_MSB  0
#define csr_UctWriteProtShadow_LSB  0
#define csr_UctWriteProtShadow_MASK 0x1
#define csr_UctDatWriteProtShadow_RANGE  1:1
#define csr_UctDatWriteProtShadow_BITS   0:0
#define csr_UctDatWriteProtShadow_MSB  1
#define csr_UctDatWriteProtShadow_LSB  1
#define csr_UctDatWriteProtShadow_MASK 0x2
#define csr_MapCAA4toDfi_RANGE  3:0
#define csr_MapCAA4toDfi_BITS   3:0
#define csr_MapCAA4toDfi_MSB  3
#define csr_MapCAA4toDfi_LSB  0
#define csr_MapCAA4toDfi_MASK 0xf
#define csr_PGCR_RANGE  0:0
#define csr_PGCR_BITS   0:0
#define csr_PGCR_MSB  0
#define csr_PGCR_LSB  0
#define csr_PGCR_MASK 0x1
#define csr_RxClkRiseFallMode_RANGE  0:0
#define csr_RxClkRiseFallMode_BITS   0:0
#define csr_RxClkRiseFallMode_MSB  0
#define csr_RxClkRiseFallMode_LSB  0
#define csr_RxClkRiseFallMode_MASK 0x1
#define csr_PreSequenceReg0b1s2_RANGE  8:0
#define csr_PreSequenceReg0b1s2_BITS   8:0
#define csr_PreSequenceReg0b1s2_MSB  8
#define csr_PreSequenceReg0b1s2_LSB  0
#define csr_PreSequenceReg0b1s2_MASK 0x1ff
#define csr_Seq0BGPR5_RANGE  15:0
#define csr_Seq0BGPR5_BITS   15:0
#define csr_Seq0BGPR5_MSB  15
#define csr_Seq0BGPR5_LSB  0
#define csr_Seq0BGPR5_MASK 0xffff
#define csr_SequenceReg0b73s1_RANGE  15:0
#define csr_SequenceReg0b73s1_BITS   15:0
#define csr_SequenceReg0b73s1_MSB  15
#define csr_SequenceReg0b73s1_LSB  0
#define csr_SequenceReg0b73s1_MASK 0xffff
#define csr_AcsmSeq0x5_RANGE  15:0
#define csr_AcsmSeq0x5_BITS   15:0
#define csr_AcsmSeq0x5_MSB  15
#define csr_AcsmSeq0x5_LSB  0
#define csr_AcsmSeq0x5_MASK 0xffff
#define csr_AcsmMclkDly5_RANGE  7:0
#define csr_AcsmMclkDly5_BITS   7:0
#define csr_AcsmMclkDly5_MSB  7
#define csr_AcsmMclkDly5_LSB  0
#define csr_AcsmMclkDly5_MASK 0xff
#define csr_AcsmDdrWe5_RANGE  8:8
#define csr_AcsmDdrWe5_BITS   0:0
#define csr_AcsmDdrWe5_MSB  8
#define csr_AcsmDdrWe5_LSB  8
#define csr_AcsmDdrWe5_MASK 0x100
#define csr_AcsmDdrCas5_RANGE  9:9
#define csr_AcsmDdrCas5_BITS   0:0
#define csr_AcsmDdrCas5_MSB  9
#define csr_AcsmDdrCas5_LSB  9
#define csr_AcsmDdrCas5_MASK 0x200
#define csr_AcsmDdrRas5_RANGE  10:10
#define csr_AcsmDdrRas5_BITS   0:0
#define csr_AcsmDdrRas5_MSB  10
#define csr_AcsmDdrRas5_LSB  10
#define csr_AcsmDdrRas5_MASK 0x400
#define csr_AcsmDdrCkeSet5_RANGE  11:11
#define csr_AcsmDdrCkeSet5_BITS   0:0
#define csr_AcsmDdrCkeSet5_MSB  11
#define csr_AcsmDdrCkeSet5_LSB  11
#define csr_AcsmDdrCkeSet5_MASK 0x800
#define csr_AcsmDdrCkeClr5_RANGE  12:12
#define csr_AcsmDdrCkeClr5_BITS   0:0
#define csr_AcsmDdrCkeClr5_MSB  12
#define csr_AcsmDdrCkeClr5_LSB  12
#define csr_AcsmDdrCkeClr5_MASK 0x1000
#define csr_AcsmSeqGateCmd5_RANGE  13:13
#define csr_AcsmSeqGateCmd5_BITS   0:0
#define csr_AcsmSeqGateCmd5_MSB  13
#define csr_AcsmSeqGateCmd5_LSB  13
#define csr_AcsmSeqGateCmd5_MASK 0x2000
#define csr_AcsmSeqTerm5_RANGE  14:14
#define csr_AcsmSeqTerm5_BITS   0:0
#define csr_AcsmSeqTerm5_MSB  14
#define csr_AcsmSeqTerm5_LSB  14
#define csr_AcsmSeqTerm5_MASK 0x4000
#define csr_AcsmLp3Ca35_RANGE  15:15
#define csr_AcsmLp3Ca35_BITS   0:0
#define csr_AcsmLp3Ca35_MSB  15
#define csr_AcsmLp3Ca35_LSB  15
#define csr_AcsmLp3Ca35_MASK 0x8000
#define csr_MapCAA5toDfi_RANGE  3:0
#define csr_MapCAA5toDfi_BITS   3:0
#define csr_MapCAA5toDfi_MSB  3
#define csr_MapCAA5toDfi_LSB  0
#define csr_MapCAA5toDfi_MASK 0xf
#define csr_PostSequenceReg0b0s0_RANGE  15:0
#define csr_PostSequenceReg0b0s0_BITS   15:0
#define csr_PostSequenceReg0b0s0_MSB  15
#define csr_PostSequenceReg0b0s0_LSB  0
#define csr_PostSequenceReg0b0s0_MASK 0xffff
#define csr_Seq0BGPR6_RANGE  15:0
#define csr_Seq0BGPR6_BITS   15:0
#define csr_Seq0BGPR6_MSB  15
#define csr_Seq0BGPR6_LSB  0
#define csr_Seq0BGPR6_MASK 0xffff
#define csr_SequenceReg0b73s2_RANGE  8:0
#define csr_SequenceReg0b73s2_BITS   8:0
#define csr_SequenceReg0b73s2_MSB  8
#define csr_SequenceReg0b73s2_LSB  0
#define csr_SequenceReg0b73s2_MASK 0x1ff
#define csr_AcsmSeq0x6_RANGE  15:0
#define csr_AcsmSeq0x6_BITS   15:0
#define csr_AcsmSeq0x6_MSB  15
#define csr_AcsmSeq0x6_LSB  0
#define csr_AcsmSeq0x6_MASK 0xffff
#define csr_AcsmMclkDly6_RANGE  7:0
#define csr_AcsmMclkDly6_BITS   7:0
#define csr_AcsmMclkDly6_MSB  7
#define csr_AcsmMclkDly6_LSB  0
#define csr_AcsmMclkDly6_MASK 0xff
#define csr_AcsmDdrWe6_RANGE  8:8
#define csr_AcsmDdrWe6_BITS   0:0
#define csr_AcsmDdrWe6_MSB  8
#define csr_AcsmDdrWe6_LSB  8
#define csr_AcsmDdrWe6_MASK 0x100
#define csr_AcsmDdrCas6_RANGE  9:9
#define csr_AcsmDdrCas6_BITS   0:0
#define csr_AcsmDdrCas6_MSB  9
#define csr_AcsmDdrCas6_LSB  9
#define csr_AcsmDdrCas6_MASK 0x200
#define csr_AcsmDdrRas6_RANGE  10:10
#define csr_AcsmDdrRas6_BITS   0:0
#define csr_AcsmDdrRas6_MSB  10
#define csr_AcsmDdrRas6_LSB  10
#define csr_AcsmDdrRas6_MASK 0x400
#define csr_AcsmDdrCkeSet6_RANGE  11:11
#define csr_AcsmDdrCkeSet6_BITS   0:0
#define csr_AcsmDdrCkeSet6_MSB  11
#define csr_AcsmDdrCkeSet6_LSB  11
#define csr_AcsmDdrCkeSet6_MASK 0x800
#define csr_AcsmDdrCkeClr6_RANGE  12:12
#define csr_AcsmDdrCkeClr6_BITS   0:0
#define csr_AcsmDdrCkeClr6_MSB  12
#define csr_AcsmDdrCkeClr6_LSB  12
#define csr_AcsmDdrCkeClr6_MASK 0x1000
#define csr_AcsmSeqGateCmd6_RANGE  13:13
#define csr_AcsmSeqGateCmd6_BITS   0:0
#define csr_AcsmSeqGateCmd6_MSB  13
#define csr_AcsmSeqGateCmd6_LSB  13
#define csr_AcsmSeqGateCmd6_MASK 0x2000
#define csr_AcsmSeqTerm6_RANGE  14:14
#define csr_AcsmSeqTerm6_BITS   0:0
#define csr_AcsmSeqTerm6_MSB  14
#define csr_AcsmSeqTerm6_LSB  14
#define csr_AcsmSeqTerm6_MASK 0x4000
#define csr_AcsmLp3Ca36_RANGE  15:15
#define csr_AcsmLp3Ca36_BITS   0:0
#define csr_AcsmLp3Ca36_MSB  15
#define csr_AcsmLp3Ca36_LSB  15
#define csr_AcsmLp3Ca36_MASK 0x8000
#define csr_MapCAA6toDfi_RANGE  3:0
#define csr_MapCAA6toDfi_BITS   3:0
#define csr_MapCAA6toDfi_MSB  3
#define csr_MapCAA6toDfi_LSB  0
#define csr_MapCAA6toDfi_MASK 0xf
#define csr_PostSequenceReg0b0s1_RANGE  15:0
#define csr_PostSequenceReg0b0s1_BITS   15:0
#define csr_PostSequenceReg0b0s1_MSB  15
#define csr_PostSequenceReg0b0s1_LSB  0
#define csr_PostSequenceReg0b0s1_MASK 0xffff
#define csr_Seq0BGPR7_RANGE  15:0
#define csr_Seq0BGPR7_BITS   15:0
#define csr_Seq0BGPR7_MSB  15
#define csr_Seq0BGPR7_LSB  0
#define csr_Seq0BGPR7_MASK 0xffff
#define csr_SequenceReg0b74s0_RANGE  15:0
#define csr_SequenceReg0b74s0_BITS   15:0
#define csr_SequenceReg0b74s0_MSB  15
#define csr_SequenceReg0b74s0_LSB  0
#define csr_SequenceReg0b74s0_MASK 0xffff
#define csr_TestBumpCntrl1_RANGE  15:0
#define csr_TestBumpCntrl1_BITS   15:0
#define csr_TestBumpCntrl1_MSB  15
#define csr_TestBumpCntrl1_LSB  0
#define csr_TestBumpCntrl1_MASK 0xffff
#define csr_TestMajorMode_RANGE  2:0
#define csr_TestMajorMode_BITS   2:0
#define csr_TestMajorMode_MSB  2
#define csr_TestMajorMode_LSB  0
#define csr_TestMajorMode_MASK 0x7
#define csr_TestBiasBypassEn_RANGE  3:3
#define csr_TestBiasBypassEn_BITS   0:0
#define csr_TestBiasBypassEn_MSB  3
#define csr_TestBiasBypassEn_LSB  3
#define csr_TestBiasBypassEn_MASK 0x8
#define csr_TestAnalogOutCtrl_RANGE  7:4
#define csr_TestAnalogOutCtrl_BITS   3:0
#define csr_TestAnalogOutCtrl_MSB  7
#define csr_TestAnalogOutCtrl_LSB  4
#define csr_TestAnalogOutCtrl_MASK 0xf0
#define csr_TestGainCurrAdj_RANGE  12:8
#define csr_TestGainCurrAdj_BITS   4:0
#define csr_TestGainCurrAdj_MSB  12
#define csr_TestGainCurrAdj_LSB  8
#define csr_TestGainCurrAdj_MASK 0x1f00
#define csr_TestSelExternalVref_RANGE  13:13
#define csr_TestSelExternalVref_BITS   0:0
#define csr_TestSelExternalVref_MSB  13
#define csr_TestSelExternalVref_LSB  13
#define csr_TestSelExternalVref_MASK 0x2000
#define csr_TestExtVrefRange_RANGE  14:14
#define csr_TestExtVrefRange_BITS   0:0
#define csr_TestExtVrefRange_MSB  14
#define csr_TestExtVrefRange_LSB  14
#define csr_TestExtVrefRange_MASK 0x4000
#define csr_TestPowerGateEn_RANGE  15:15
#define csr_TestPowerGateEn_BITS   0:0
#define csr_TestPowerGateEn_MSB  15
#define csr_TestPowerGateEn_LSB  15
#define csr_TestPowerGateEn_MASK 0x8000
#define csr_AcsmSeq0x7_RANGE  15:0
#define csr_AcsmSeq0x7_BITS   15:0
#define csr_AcsmSeq0x7_MSB  15
#define csr_AcsmSeq0x7_LSB  0
#define csr_AcsmSeq0x7_MASK 0xffff
#define csr_AcsmMclkDly7_RANGE  7:0
#define csr_AcsmMclkDly7_BITS   7:0
#define csr_AcsmMclkDly7_MSB  7
#define csr_AcsmMclkDly7_LSB  0
#define csr_AcsmMclkDly7_MASK 0xff
#define csr_AcsmDdrWe7_RANGE  8:8
#define csr_AcsmDdrWe7_BITS   0:0
#define csr_AcsmDdrWe7_MSB  8
#define csr_AcsmDdrWe7_LSB  8
#define csr_AcsmDdrWe7_MASK 0x100
#define csr_AcsmDdrCas7_RANGE  9:9
#define csr_AcsmDdrCas7_BITS   0:0
#define csr_AcsmDdrCas7_MSB  9
#define csr_AcsmDdrCas7_LSB  9
#define csr_AcsmDdrCas7_MASK 0x200
#define csr_AcsmDdrRas7_RANGE  10:10
#define csr_AcsmDdrRas7_BITS   0:0
#define csr_AcsmDdrRas7_MSB  10
#define csr_AcsmDdrRas7_LSB  10
#define csr_AcsmDdrRas7_MASK 0x400
#define csr_AcsmDdrCkeSet7_RANGE  11:11
#define csr_AcsmDdrCkeSet7_BITS   0:0
#define csr_AcsmDdrCkeSet7_MSB  11
#define csr_AcsmDdrCkeSet7_LSB  11
#define csr_AcsmDdrCkeSet7_MASK 0x800
#define csr_AcsmDdrCkeClr7_RANGE  12:12
#define csr_AcsmDdrCkeClr7_BITS   0:0
#define csr_AcsmDdrCkeClr7_MSB  12
#define csr_AcsmDdrCkeClr7_LSB  12
#define csr_AcsmDdrCkeClr7_MASK 0x1000
#define csr_AcsmSeqGateCmd7_RANGE  13:13
#define csr_AcsmSeqGateCmd7_BITS   0:0
#define csr_AcsmSeqGateCmd7_MSB  13
#define csr_AcsmSeqGateCmd7_LSB  13
#define csr_AcsmSeqGateCmd7_MASK 0x2000
#define csr_AcsmSeqTerm7_RANGE  14:14
#define csr_AcsmSeqTerm7_BITS   0:0
#define csr_AcsmSeqTerm7_MSB  14
#define csr_AcsmSeqTerm7_LSB  14
#define csr_AcsmSeqTerm7_MASK 0x4000
#define csr_AcsmLp3Ca37_RANGE  15:15
#define csr_AcsmLp3Ca37_BITS   0:0
#define csr_AcsmLp3Ca37_MSB  15
#define csr_AcsmLp3Ca37_LSB  15
#define csr_AcsmLp3Ca37_MASK 0x8000
#define csr_MapCAA7toDfi_RANGE  3:0
#define csr_MapCAA7toDfi_BITS   3:0
#define csr_MapCAA7toDfi_MSB  3
#define csr_MapCAA7toDfi_LSB  0
#define csr_MapCAA7toDfi_MASK 0xf
#define csr_PostSequenceReg0b0s2_RANGE  8:0
#define csr_PostSequenceReg0b0s2_BITS   8:0
#define csr_PostSequenceReg0b0s2_MSB  8
#define csr_PostSequenceReg0b0s2_LSB  0
#define csr_PostSequenceReg0b0s2_MASK 0x1ff
#define csr_Seq0BGPR8_RANGE  15:0
#define csr_Seq0BGPR8_BITS   15:0
#define csr_Seq0BGPR8_MSB  15
#define csr_Seq0BGPR8_LSB  0
#define csr_Seq0BGPR8_MASK 0xffff
#define csr_SequenceReg0b74s1_RANGE  15:0
#define csr_SequenceReg0b74s1_BITS   15:0
#define csr_SequenceReg0b74s1_MSB  15
#define csr_SequenceReg0b74s1_LSB  0
#define csr_SequenceReg0b74s1_MASK 0xffff
#define csr_AcsmSeq0x8_RANGE  15:0
#define csr_AcsmSeq0x8_BITS   15:0
#define csr_AcsmSeq0x8_MSB  15
#define csr_AcsmSeq0x8_LSB  0
#define csr_AcsmSeq0x8_MASK 0xffff
#define csr_AcsmMclkDly8_RANGE  7:0
#define csr_AcsmMclkDly8_BITS   7:0
#define csr_AcsmMclkDly8_MSB  7
#define csr_AcsmMclkDly8_LSB  0
#define csr_AcsmMclkDly8_MASK 0xff
#define csr_AcsmDdrWe8_RANGE  8:8
#define csr_AcsmDdrWe8_BITS   0:0
#define csr_AcsmDdrWe8_MSB  8
#define csr_AcsmDdrWe8_LSB  8
#define csr_AcsmDdrWe8_MASK 0x100
#define csr_AcsmDdrCas8_RANGE  9:9
#define csr_AcsmDdrCas8_BITS   0:0
#define csr_AcsmDdrCas8_MSB  9
#define csr_AcsmDdrCas8_LSB  9
#define csr_AcsmDdrCas8_MASK 0x200
#define csr_AcsmDdrRas8_RANGE  10:10
#define csr_AcsmDdrRas8_BITS   0:0
#define csr_AcsmDdrRas8_MSB  10
#define csr_AcsmDdrRas8_LSB  10
#define csr_AcsmDdrRas8_MASK 0x400
#define csr_AcsmDdrCkeSet8_RANGE  11:11
#define csr_AcsmDdrCkeSet8_BITS   0:0
#define csr_AcsmDdrCkeSet8_MSB  11
#define csr_AcsmDdrCkeSet8_LSB  11
#define csr_AcsmDdrCkeSet8_MASK 0x800
#define csr_AcsmDdrCkeClr8_RANGE  12:12
#define csr_AcsmDdrCkeClr8_BITS   0:0
#define csr_AcsmDdrCkeClr8_MSB  12
#define csr_AcsmDdrCkeClr8_LSB  12
#define csr_AcsmDdrCkeClr8_MASK 0x1000
#define csr_AcsmSeqGateCmd8_RANGE  13:13
#define csr_AcsmSeqGateCmd8_BITS   0:0
#define csr_AcsmSeqGateCmd8_MSB  13
#define csr_AcsmSeqGateCmd8_LSB  13
#define csr_AcsmSeqGateCmd8_MASK 0x2000
#define csr_AcsmSeqTerm8_RANGE  14:14
#define csr_AcsmSeqTerm8_BITS   0:0
#define csr_AcsmSeqTerm8_MSB  14
#define csr_AcsmSeqTerm8_LSB  14
#define csr_AcsmSeqTerm8_MASK 0x4000
#define csr_AcsmLp3Ca38_RANGE  15:15
#define csr_AcsmLp3Ca38_BITS   0:0
#define csr_AcsmLp3Ca38_MSB  15
#define csr_AcsmLp3Ca38_LSB  15
#define csr_AcsmLp3Ca38_MASK 0x8000
#define csr_CalUclkInfo_RANGE  10:0
#define csr_CalUclkInfo_BITS   10:0
#define csr_CalUclkInfo_MSB  10
#define csr_CalUclkInfo_LSB  0
#define csr_CalUclkInfo_MASK 0x7ff
#define csr_CalUClkTicksPer1uS_RANGE  10:0
#define csr_CalUClkTicksPer1uS_BITS   10:0
#define csr_CalUClkTicksPer1uS_MSB  10
#define csr_CalUClkTicksPer1uS_LSB  0
#define csr_CalUClkTicksPer1uS_MASK 0x7ff
#define csr_MapCAA8toDfi_RANGE  3:0
#define csr_MapCAA8toDfi_BITS   3:0
#define csr_MapCAA8toDfi_MSB  3
#define csr_MapCAA8toDfi_LSB  0
#define csr_MapCAA8toDfi_MASK 0xf
#define csr_PostSequenceReg0b1s0_RANGE  15:0
#define csr_PostSequenceReg0b1s0_BITS   15:0
#define csr_PostSequenceReg0b1s0_MSB  15
#define csr_PostSequenceReg0b1s0_LSB  0
#define csr_PostSequenceReg0b1s0_MASK 0xffff
#define csr_SequenceReg0b74s2_RANGE  8:0
#define csr_SequenceReg0b74s2_BITS   8:0
#define csr_SequenceReg0b74s2_MSB  8
#define csr_SequenceReg0b74s2_LSB  0
#define csr_SequenceReg0b74s2_MASK 0x1ff
#define csr_AcsmSeq0x9_RANGE  15:0
#define csr_AcsmSeq0x9_BITS   15:0
#define csr_AcsmSeq0x9_MSB  15
#define csr_AcsmSeq0x9_LSB  0
#define csr_AcsmSeq0x9_MASK 0xffff
#define csr_AcsmMclkDly9_RANGE  7:0
#define csr_AcsmMclkDly9_BITS   7:0
#define csr_AcsmMclkDly9_MSB  7
#define csr_AcsmMclkDly9_LSB  0
#define csr_AcsmMclkDly9_MASK 0xff
#define csr_AcsmDdrWe9_RANGE  8:8
#define csr_AcsmDdrWe9_BITS   0:0
#define csr_AcsmDdrWe9_MSB  8
#define csr_AcsmDdrWe9_LSB  8
#define csr_AcsmDdrWe9_MASK 0x100
#define csr_AcsmDdrCas9_RANGE  9:9
#define csr_AcsmDdrCas9_BITS   0:0
#define csr_AcsmDdrCas9_MSB  9
#define csr_AcsmDdrCas9_LSB  9
#define csr_AcsmDdrCas9_MASK 0x200
#define csr_AcsmDdrRas9_RANGE  10:10
#define csr_AcsmDdrRas9_BITS   0:0
#define csr_AcsmDdrRas9_MSB  10
#define csr_AcsmDdrRas9_LSB  10
#define csr_AcsmDdrRas9_MASK 0x400
#define csr_AcsmDdrCkeSet9_RANGE  11:11
#define csr_AcsmDdrCkeSet9_BITS   0:0
#define csr_AcsmDdrCkeSet9_MSB  11
#define csr_AcsmDdrCkeSet9_LSB  11
#define csr_AcsmDdrCkeSet9_MASK 0x800
#define csr_AcsmDdrCkeClr9_RANGE  12:12
#define csr_AcsmDdrCkeClr9_BITS   0:0
#define csr_AcsmDdrCkeClr9_MSB  12
#define csr_AcsmDdrCkeClr9_LSB  12
#define csr_AcsmDdrCkeClr9_MASK 0x1000
#define csr_AcsmSeqGateCmd9_RANGE  13:13
#define csr_AcsmSeqGateCmd9_BITS   0:0
#define csr_AcsmSeqGateCmd9_MSB  13
#define csr_AcsmSeqGateCmd9_LSB  13
#define csr_AcsmSeqGateCmd9_MASK 0x2000
#define csr_AcsmSeqTerm9_RANGE  14:14
#define csr_AcsmSeqTerm9_BITS   0:0
#define csr_AcsmSeqTerm9_MSB  14
#define csr_AcsmSeqTerm9_LSB  14
#define csr_AcsmSeqTerm9_MASK 0x4000
#define csr_AcsmLp3Ca39_RANGE  15:15
#define csr_AcsmLp3Ca39_BITS   0:0
#define csr_AcsmLp3Ca39_MSB  15
#define csr_AcsmLp3Ca39_LSB  15
#define csr_AcsmLp3Ca39_MASK 0x8000
#define csr_MapCAA9toDfi_RANGE  3:0
#define csr_MapCAA9toDfi_BITS   3:0
#define csr_MapCAA9toDfi_MSB  3
#define csr_MapCAA9toDfi_LSB  0
#define csr_MapCAA9toDfi_MASK 0xf
#define csr_PostSequenceReg0b1s1_RANGE  15:0
#define csr_PostSequenceReg0b1s1_BITS   15:0
#define csr_PostSequenceReg0b1s1_MSB  15
#define csr_PostSequenceReg0b1s1_LSB  0
#define csr_PostSequenceReg0b1s1_MASK 0xffff
#define csr_SequenceReg0b75s0_RANGE  15:0
#define csr_SequenceReg0b75s0_BITS   15:0
#define csr_SequenceReg0b75s0_MSB  15
#define csr_SequenceReg0b75s0_LSB  0
#define csr_SequenceReg0b75s0_MASK 0xffff
#define csr_TestBumpCntrl_RANGE  9:0
#define csr_TestBumpCntrl_BITS   9:0
#define csr_TestBumpCntrl_MSB  9
#define csr_TestBumpCntrl_LSB  0
#define csr_TestBumpCntrl_MASK 0x3ff
#define csr_TestBumpEn_RANGE  1:0
#define csr_TestBumpEn_BITS   1:0
#define csr_TestBumpEn_MSB  1
#define csr_TestBumpEn_LSB  0
#define csr_TestBumpEn_MASK 0x3
#define csr_TestBumpToggle_RANGE  2:2
#define csr_TestBumpToggle_BITS   0:0
#define csr_TestBumpToggle_MSB  2
#define csr_TestBumpToggle_LSB  2
#define csr_TestBumpToggle_MASK 0x4
#define csr_TestBumpDataSel_RANGE  8:3
#define csr_TestBumpDataSel_BITS   5:0
#define csr_TestBumpDataSel_MSB  8
#define csr_TestBumpDataSel_LSB  3
#define csr_TestBumpDataSel_MASK 0x1f8
#define csr_ForceMtestOnAlert_RANGE  9:9
#define csr_ForceMtestOnAlert_BITS   0:0
#define csr_ForceMtestOnAlert_MSB  9
#define csr_ForceMtestOnAlert_LSB  9
#define csr_ForceMtestOnAlert_MASK 0x200
#define csr_AcsmSeq0x10_RANGE  15:0
#define csr_AcsmSeq0x10_BITS   15:0
#define csr_AcsmSeq0x10_MSB  15
#define csr_AcsmSeq0x10_LSB  0
#define csr_AcsmSeq0x10_MASK 0xffff
#define csr_AcsmMclkDly10_RANGE  7:0
#define csr_AcsmMclkDly10_BITS   7:0
#define csr_AcsmMclkDly10_MSB  7
#define csr_AcsmMclkDly10_LSB  0
#define csr_AcsmMclkDly10_MASK 0xff
#define csr_AcsmDdrWe10_RANGE  8:8
#define csr_AcsmDdrWe10_BITS   0:0
#define csr_AcsmDdrWe10_MSB  8
#define csr_AcsmDdrWe10_LSB  8
#define csr_AcsmDdrWe10_MASK 0x100
#define csr_AcsmDdrCas10_RANGE  9:9
#define csr_AcsmDdrCas10_BITS   0:0
#define csr_AcsmDdrCas10_MSB  9
#define csr_AcsmDdrCas10_LSB  9
#define csr_AcsmDdrCas10_MASK 0x200
#define csr_AcsmDdrRas10_RANGE  10:10
#define csr_AcsmDdrRas10_BITS   0:0
#define csr_AcsmDdrRas10_MSB  10
#define csr_AcsmDdrRas10_LSB  10
#define csr_AcsmDdrRas10_MASK 0x400
#define csr_AcsmDdrCkeSet10_RANGE  11:11
#define csr_AcsmDdrCkeSet10_BITS   0:0
#define csr_AcsmDdrCkeSet10_MSB  11
#define csr_AcsmDdrCkeSet10_LSB  11
#define csr_AcsmDdrCkeSet10_MASK 0x800
#define csr_AcsmDdrCkeClr10_RANGE  12:12
#define csr_AcsmDdrCkeClr10_BITS   0:0
#define csr_AcsmDdrCkeClr10_MSB  12
#define csr_AcsmDdrCkeClr10_LSB  12
#define csr_AcsmDdrCkeClr10_MASK 0x1000
#define csr_AcsmSeqGateCmd10_RANGE  13:13
#define csr_AcsmSeqGateCmd10_BITS   0:0
#define csr_AcsmSeqGateCmd10_MSB  13
#define csr_AcsmSeqGateCmd10_LSB  13
#define csr_AcsmSeqGateCmd10_MASK 0x2000
#define csr_AcsmSeqTerm10_RANGE  14:14
#define csr_AcsmSeqTerm10_BITS   0:0
#define csr_AcsmSeqTerm10_MSB  14
#define csr_AcsmSeqTerm10_LSB  14
#define csr_AcsmSeqTerm10_MASK 0x4000
#define csr_AcsmLp3Ca310_RANGE  15:15
#define csr_AcsmLp3Ca310_BITS   0:0
#define csr_AcsmLp3Ca310_MSB  15
#define csr_AcsmLp3Ca310_LSB  15
#define csr_AcsmLp3Ca310_MASK 0x8000
#define csr_PostSequenceReg0b1s2_RANGE  8:0
#define csr_PostSequenceReg0b1s2_BITS   8:0
#define csr_PostSequenceReg0b1s2_MSB  8
#define csr_PostSequenceReg0b1s2_LSB  0
#define csr_PostSequenceReg0b1s2_MASK 0x1ff
#define csr_SequenceReg0b75s1_RANGE  15:0
#define csr_SequenceReg0b75s1_BITS   15:0
#define csr_SequenceReg0b75s1_MSB  15
#define csr_SequenceReg0b75s1_LSB  0
#define csr_SequenceReg0b75s1_MASK 0xffff
#define csr_Seq0BDLY0_RANGE  15:0
#define csr_Seq0BDLY0_BITS   15:0
#define csr_Seq0BDLY0_MSB  15
#define csr_Seq0BDLY0_LSB  0
#define csr_Seq0BDLY0_MASK 0xffff
#define csr_AcsmSeq0x11_RANGE  15:0
#define csr_AcsmSeq0x11_BITS   15:0
#define csr_AcsmSeq0x11_MSB  15
#define csr_AcsmSeq0x11_LSB  0
#define csr_AcsmSeq0x11_MASK 0xffff
#define csr_AcsmMclkDly11_RANGE  7:0
#define csr_AcsmMclkDly11_BITS   7:0
#define csr_AcsmMclkDly11_MSB  7
#define csr_AcsmMclkDly11_LSB  0
#define csr_AcsmMclkDly11_MASK 0xff
#define csr_AcsmDdrWe11_RANGE  8:8
#define csr_AcsmDdrWe11_BITS   0:0
#define csr_AcsmDdrWe11_MSB  8
#define csr_AcsmDdrWe11_LSB  8
#define csr_AcsmDdrWe11_MASK 0x100
#define csr_AcsmDdrCas11_RANGE  9:9
#define csr_AcsmDdrCas11_BITS   0:0
#define csr_AcsmDdrCas11_MSB  9
#define csr_AcsmDdrCas11_LSB  9
#define csr_AcsmDdrCas11_MASK 0x200
#define csr_AcsmDdrRas11_RANGE  10:10
#define csr_AcsmDdrRas11_BITS   0:0
#define csr_AcsmDdrRas11_MSB  10
#define csr_AcsmDdrRas11_LSB  10
#define csr_AcsmDdrRas11_MASK 0x400
#define csr_AcsmDdrCkeSet11_RANGE  11:11
#define csr_AcsmDdrCkeSet11_BITS   0:0
#define csr_AcsmDdrCkeSet11_MSB  11
#define csr_AcsmDdrCkeSet11_LSB  11
#define csr_AcsmDdrCkeSet11_MASK 0x800
#define csr_AcsmDdrCkeClr11_RANGE  12:12
#define csr_AcsmDdrCkeClr11_BITS   0:0
#define csr_AcsmDdrCkeClr11_MSB  12
#define csr_AcsmDdrCkeClr11_LSB  12
#define csr_AcsmDdrCkeClr11_MASK 0x1000
#define csr_AcsmSeqGateCmd11_RANGE  13:13
#define csr_AcsmSeqGateCmd11_BITS   0:0
#define csr_AcsmSeqGateCmd11_MSB  13
#define csr_AcsmSeqGateCmd11_LSB  13
#define csr_AcsmSeqGateCmd11_MASK 0x2000
#define csr_AcsmSeqTerm11_RANGE  14:14
#define csr_AcsmSeqTerm11_BITS   0:0
#define csr_AcsmSeqTerm11_MSB  14
#define csr_AcsmSeqTerm11_LSB  14
#define csr_AcsmSeqTerm11_MASK 0x4000
#define csr_AcsmLp3Ca311_RANGE  15:15
#define csr_AcsmLp3Ca311_BITS   0:0
#define csr_AcsmLp3Ca311_MSB  15
#define csr_AcsmLp3Ca311_LSB  15
#define csr_AcsmLp3Ca311_MASK 0x8000
#define csr_Seq0BDisableFlag0_RANGE  15:0
#define csr_Seq0BDisableFlag0_BITS   15:0
#define csr_Seq0BDisableFlag0_MSB  15
#define csr_Seq0BDisableFlag0_LSB  0
#define csr_Seq0BDisableFlag0_MASK 0xffff
#define csr_SequenceReg0b75s2_RANGE  8:0
#define csr_SequenceReg0b75s2_BITS   8:0
#define csr_SequenceReg0b75s2_MSB  8
#define csr_SequenceReg0b75s2_LSB  0
#define csr_SequenceReg0b75s2_MASK 0x1ff
#define csr_Seq0BDLY1_RANGE  15:0
#define csr_Seq0BDLY1_BITS   15:0
#define csr_Seq0BDLY1_MSB  15
#define csr_Seq0BDLY1_LSB  0
#define csr_Seq0BDLY1_MASK 0xffff
#define csr_AcsmSeq0x12_RANGE  15:0
#define csr_AcsmSeq0x12_BITS   15:0
#define csr_AcsmSeq0x12_MSB  15
#define csr_AcsmSeq0x12_LSB  0
#define csr_AcsmSeq0x12_MASK 0xffff
#define csr_AcsmMclkDly12_RANGE  7:0
#define csr_AcsmMclkDly12_BITS   7:0
#define csr_AcsmMclkDly12_MSB  7
#define csr_AcsmMclkDly12_LSB  0
#define csr_AcsmMclkDly12_MASK 0xff
#define csr_AcsmDdrWe12_RANGE  8:8
#define csr_AcsmDdrWe12_BITS   0:0
#define csr_AcsmDdrWe12_MSB  8
#define csr_AcsmDdrWe12_LSB  8
#define csr_AcsmDdrWe12_MASK 0x100
#define csr_AcsmDdrCas12_RANGE  9:9
#define csr_AcsmDdrCas12_BITS   0:0
#define csr_AcsmDdrCas12_MSB  9
#define csr_AcsmDdrCas12_LSB  9
#define csr_AcsmDdrCas12_MASK 0x200
#define csr_AcsmDdrRas12_RANGE  10:10
#define csr_AcsmDdrRas12_BITS   0:0
#define csr_AcsmDdrRas12_MSB  10
#define csr_AcsmDdrRas12_LSB  10
#define csr_AcsmDdrRas12_MASK 0x400
#define csr_AcsmDdrCkeSet12_RANGE  11:11
#define csr_AcsmDdrCkeSet12_BITS   0:0
#define csr_AcsmDdrCkeSet12_MSB  11
#define csr_AcsmDdrCkeSet12_LSB  11
#define csr_AcsmDdrCkeSet12_MASK 0x800
#define csr_AcsmDdrCkeClr12_RANGE  12:12
#define csr_AcsmDdrCkeClr12_BITS   0:0
#define csr_AcsmDdrCkeClr12_MSB  12
#define csr_AcsmDdrCkeClr12_LSB  12
#define csr_AcsmDdrCkeClr12_MASK 0x1000
#define csr_AcsmSeqGateCmd12_RANGE  13:13
#define csr_AcsmSeqGateCmd12_BITS   0:0
#define csr_AcsmSeqGateCmd12_MSB  13
#define csr_AcsmSeqGateCmd12_LSB  13
#define csr_AcsmSeqGateCmd12_MASK 0x2000
#define csr_AcsmSeqTerm12_RANGE  14:14
#define csr_AcsmSeqTerm12_BITS   0:0
#define csr_AcsmSeqTerm12_MSB  14
#define csr_AcsmSeqTerm12_LSB  14
#define csr_AcsmSeqTerm12_MASK 0x4000
#define csr_AcsmLp3Ca312_RANGE  15:15
#define csr_AcsmLp3Ca312_BITS   0:0
#define csr_AcsmLp3Ca312_MSB  15
#define csr_AcsmLp3Ca312_LSB  15
#define csr_AcsmLp3Ca312_MASK 0x8000
#define csr_Seq0BDisableFlag1_RANGE  15:0
#define csr_Seq0BDisableFlag1_BITS   15:0
#define csr_Seq0BDisableFlag1_MSB  15
#define csr_Seq0BDisableFlag1_LSB  0
#define csr_Seq0BDisableFlag1_MASK 0xffff
#define csr_SequenceReg0b76s0_RANGE  15:0
#define csr_SequenceReg0b76s0_BITS   15:0
#define csr_SequenceReg0b76s0_MSB  15
#define csr_SequenceReg0b76s0_LSB  0
#define csr_SequenceReg0b76s0_MASK 0xffff
#define csr_Seq0BDLY2_RANGE  15:0
#define csr_Seq0BDLY2_BITS   15:0
#define csr_Seq0BDLY2_MSB  15
#define csr_Seq0BDLY2_LSB  0
#define csr_Seq0BDLY2_MASK 0xffff
#define csr_AcsmSeq0x13_RANGE  15:0
#define csr_AcsmSeq0x13_BITS   15:0
#define csr_AcsmSeq0x13_MSB  15
#define csr_AcsmSeq0x13_LSB  0
#define csr_AcsmSeq0x13_MASK 0xffff
#define csr_AcsmMclkDly13_RANGE  7:0
#define csr_AcsmMclkDly13_BITS   7:0
#define csr_AcsmMclkDly13_MSB  7
#define csr_AcsmMclkDly13_LSB  0
#define csr_AcsmMclkDly13_MASK 0xff
#define csr_AcsmDdrWe13_RANGE  8:8
#define csr_AcsmDdrWe13_BITS   0:0
#define csr_AcsmDdrWe13_MSB  8
#define csr_AcsmDdrWe13_LSB  8
#define csr_AcsmDdrWe13_MASK 0x100
#define csr_AcsmDdrCas13_RANGE  9:9
#define csr_AcsmDdrCas13_BITS   0:0
#define csr_AcsmDdrCas13_MSB  9
#define csr_AcsmDdrCas13_LSB  9
#define csr_AcsmDdrCas13_MASK 0x200
#define csr_AcsmDdrRas13_RANGE  10:10
#define csr_AcsmDdrRas13_BITS   0:0
#define csr_AcsmDdrRas13_MSB  10
#define csr_AcsmDdrRas13_LSB  10
#define csr_AcsmDdrRas13_MASK 0x400
#define csr_AcsmDdrCkeSet13_RANGE  11:11
#define csr_AcsmDdrCkeSet13_BITS   0:0
#define csr_AcsmDdrCkeSet13_MSB  11
#define csr_AcsmDdrCkeSet13_LSB  11
#define csr_AcsmDdrCkeSet13_MASK 0x800
#define csr_AcsmDdrCkeClr13_RANGE  12:12
#define csr_AcsmDdrCkeClr13_BITS   0:0
#define csr_AcsmDdrCkeClr13_MSB  12
#define csr_AcsmDdrCkeClr13_LSB  12
#define csr_AcsmDdrCkeClr13_MASK 0x1000
#define csr_AcsmSeqGateCmd13_RANGE  13:13
#define csr_AcsmSeqGateCmd13_BITS   0:0
#define csr_AcsmSeqGateCmd13_MSB  13
#define csr_AcsmSeqGateCmd13_LSB  13
#define csr_AcsmSeqGateCmd13_MASK 0x2000
#define csr_AcsmSeqTerm13_RANGE  14:14
#define csr_AcsmSeqTerm13_BITS   0:0
#define csr_AcsmSeqTerm13_MSB  14
#define csr_AcsmSeqTerm13_LSB  14
#define csr_AcsmSeqTerm13_MASK 0x4000
#define csr_AcsmLp3Ca313_RANGE  15:15
#define csr_AcsmLp3Ca313_BITS   0:0
#define csr_AcsmLp3Ca313_MSB  15
#define csr_AcsmLp3Ca313_LSB  15
#define csr_AcsmLp3Ca313_MASK 0x8000
#define csr_Seq0BDisableFlag2_RANGE  15:0
#define csr_Seq0BDisableFlag2_BITS   15:0
#define csr_Seq0BDisableFlag2_MSB  15
#define csr_Seq0BDisableFlag2_LSB  0
#define csr_Seq0BDisableFlag2_MASK 0xffff
#define csr_SequenceReg0b76s1_RANGE  15:0
#define csr_SequenceReg0b76s1_BITS   15:0
#define csr_SequenceReg0b76s1_MSB  15
#define csr_SequenceReg0b76s1_LSB  0
#define csr_SequenceReg0b76s1_MASK 0xffff
#define csr_Seq0BDLY3_RANGE  15:0
#define csr_Seq0BDLY3_BITS   15:0
#define csr_Seq0BDLY3_MSB  15
#define csr_Seq0BDLY3_LSB  0
#define csr_Seq0BDLY3_MASK 0xffff
#define csr_AcsmSeq0x14_RANGE  15:0
#define csr_AcsmSeq0x14_BITS   15:0
#define csr_AcsmSeq0x14_MSB  15
#define csr_AcsmSeq0x14_LSB  0
#define csr_AcsmSeq0x14_MASK 0xffff
#define csr_AcsmMclkDly14_RANGE  7:0
#define csr_AcsmMclkDly14_BITS   7:0
#define csr_AcsmMclkDly14_MSB  7
#define csr_AcsmMclkDly14_LSB  0
#define csr_AcsmMclkDly14_MASK 0xff
#define csr_AcsmDdrWe14_RANGE  8:8
#define csr_AcsmDdrWe14_BITS   0:0
#define csr_AcsmDdrWe14_MSB  8
#define csr_AcsmDdrWe14_LSB  8
#define csr_AcsmDdrWe14_MASK 0x100
#define csr_AcsmDdrCas14_RANGE  9:9
#define csr_AcsmDdrCas14_BITS   0:0
#define csr_AcsmDdrCas14_MSB  9
#define csr_AcsmDdrCas14_LSB  9
#define csr_AcsmDdrCas14_MASK 0x200
#define csr_AcsmDdrRas14_RANGE  10:10
#define csr_AcsmDdrRas14_BITS   0:0
#define csr_AcsmDdrRas14_MSB  10
#define csr_AcsmDdrRas14_LSB  10
#define csr_AcsmDdrRas14_MASK 0x400
#define csr_AcsmDdrCkeSet14_RANGE  11:11
#define csr_AcsmDdrCkeSet14_BITS   0:0
#define csr_AcsmDdrCkeSet14_MSB  11
#define csr_AcsmDdrCkeSet14_LSB  11
#define csr_AcsmDdrCkeSet14_MASK 0x800
#define csr_AcsmDdrCkeClr14_RANGE  12:12
#define csr_AcsmDdrCkeClr14_BITS   0:0
#define csr_AcsmDdrCkeClr14_MSB  12
#define csr_AcsmDdrCkeClr14_LSB  12
#define csr_AcsmDdrCkeClr14_MASK 0x1000
#define csr_AcsmSeqGateCmd14_RANGE  13:13
#define csr_AcsmSeqGateCmd14_BITS   0:0
#define csr_AcsmSeqGateCmd14_MSB  13
#define csr_AcsmSeqGateCmd14_LSB  13
#define csr_AcsmSeqGateCmd14_MASK 0x2000
#define csr_AcsmSeqTerm14_RANGE  14:14
#define csr_AcsmSeqTerm14_BITS   0:0
#define csr_AcsmSeqTerm14_MSB  14
#define csr_AcsmSeqTerm14_LSB  14
#define csr_AcsmSeqTerm14_MASK 0x4000
#define csr_AcsmLp3Ca314_RANGE  15:15
#define csr_AcsmLp3Ca314_BITS   0:0
#define csr_AcsmLp3Ca314_MSB  15
#define csr_AcsmLp3Ca314_LSB  15
#define csr_AcsmLp3Ca314_MASK 0x8000
#define csr_Seq0BDisableFlag3_RANGE  15:0
#define csr_Seq0BDisableFlag3_BITS   15:0
#define csr_Seq0BDisableFlag3_MSB  15
#define csr_Seq0BDisableFlag3_LSB  0
#define csr_Seq0BDisableFlag3_MASK 0xffff
#define csr_SequenceReg0b76s2_RANGE  8:0
#define csr_SequenceReg0b76s2_BITS   8:0
#define csr_SequenceReg0b76s2_MSB  8
#define csr_SequenceReg0b76s2_LSB  0
#define csr_SequenceReg0b76s2_MASK 0x1ff
#define csr_PhyAlertStatus_RANGE  0:0
#define csr_PhyAlertStatus_BITS   0:0
#define csr_PhyAlertStatus_MSB  0
#define csr_PhyAlertStatus_LSB  0
#define csr_PhyAlertStatus_MASK 0x1
#define csr_PhyAlert_RANGE  0:0
#define csr_PhyAlert_BITS   0:0
#define csr_PhyAlert_MSB  0
#define csr_PhyAlert_LSB  0
#define csr_PhyAlert_MASK 0x1
#define csr_AcsmSeq0x15_RANGE  15:0
#define csr_AcsmSeq0x15_BITS   15:0
#define csr_AcsmSeq0x15_MSB  15
#define csr_AcsmSeq0x15_LSB  0
#define csr_AcsmSeq0x15_MASK 0xffff
#define csr_AcsmMclkDly15_RANGE  7:0
#define csr_AcsmMclkDly15_BITS   7:0
#define csr_AcsmMclkDly15_MSB  7
#define csr_AcsmMclkDly15_LSB  0
#define csr_AcsmMclkDly15_MASK 0xff
#define csr_AcsmDdrWe15_RANGE  8:8
#define csr_AcsmDdrWe15_BITS   0:0
#define csr_AcsmDdrWe15_MSB  8
#define csr_AcsmDdrWe15_LSB  8
#define csr_AcsmDdrWe15_MASK 0x100
#define csr_AcsmDdrCas15_RANGE  9:9
#define csr_AcsmDdrCas15_BITS   0:0
#define csr_AcsmDdrCas15_MSB  9
#define csr_AcsmDdrCas15_LSB  9
#define csr_AcsmDdrCas15_MASK 0x200
#define csr_AcsmDdrRas15_RANGE  10:10
#define csr_AcsmDdrRas15_BITS   0:0
#define csr_AcsmDdrRas15_MSB  10
#define csr_AcsmDdrRas15_LSB  10
#define csr_AcsmDdrRas15_MASK 0x400
#define csr_AcsmDdrCkeSet15_RANGE  11:11
#define csr_AcsmDdrCkeSet15_BITS   0:0
#define csr_AcsmDdrCkeSet15_MSB  11
#define csr_AcsmDdrCkeSet15_LSB  11
#define csr_AcsmDdrCkeSet15_MASK 0x800
#define csr_AcsmDdrCkeClr15_RANGE  12:12
#define csr_AcsmDdrCkeClr15_BITS   0:0
#define csr_AcsmDdrCkeClr15_MSB  12
#define csr_AcsmDdrCkeClr15_LSB  12
#define csr_AcsmDdrCkeClr15_MASK 0x1000
#define csr_AcsmSeqGateCmd15_RANGE  13:13
#define csr_AcsmSeqGateCmd15_BITS   0:0
#define csr_AcsmSeqGateCmd15_MSB  13
#define csr_AcsmSeqGateCmd15_LSB  13
#define csr_AcsmSeqGateCmd15_MASK 0x2000
#define csr_AcsmSeqTerm15_RANGE  14:14
#define csr_AcsmSeqTerm15_BITS   0:0
#define csr_AcsmSeqTerm15_MSB  14
#define csr_AcsmSeqTerm15_LSB  14
#define csr_AcsmSeqTerm15_MASK 0x4000
#define csr_AcsmLp3Ca315_RANGE  15:15
#define csr_AcsmLp3Ca315_BITS   0:0
#define csr_AcsmLp3Ca315_MSB  15
#define csr_AcsmLp3Ca315_LSB  15
#define csr_AcsmLp3Ca315_MASK 0x8000
#define csr_RxTrainPatternEnable_RANGE  0:0
#define csr_RxTrainPatternEnable_BITS   0:0
#define csr_RxTrainPatternEnable_MSB  0
#define csr_RxTrainPatternEnable_LSB  0
#define csr_RxTrainPatternEnable_MASK 0x1
#define csr_Seq0BDisableFlag4_RANGE  15:0
#define csr_Seq0BDisableFlag4_BITS   15:0
#define csr_Seq0BDisableFlag4_MSB  15
#define csr_Seq0BDisableFlag4_LSB  0
#define csr_Seq0BDisableFlag4_MASK 0xffff
#define csr_SequenceReg0b77s0_RANGE  15:0
#define csr_SequenceReg0b77s0_BITS   15:0
#define csr_SequenceReg0b77s0_MSB  15
#define csr_SequenceReg0b77s0_LSB  0
#define csr_SequenceReg0b77s0_MASK 0xffff
#define csr_AcsmSeq0x16_RANGE  15:0
#define csr_AcsmSeq0x16_BITS   15:0
#define csr_AcsmSeq0x16_MSB  15
#define csr_AcsmSeq0x16_LSB  0
#define csr_AcsmSeq0x16_MASK 0xffff
#define csr_AcsmMclkDly16_RANGE  7:0
#define csr_AcsmMclkDly16_BITS   7:0
#define csr_AcsmMclkDly16_MSB  7
#define csr_AcsmMclkDly16_LSB  0
#define csr_AcsmMclkDly16_MASK 0xff
#define csr_AcsmDdrWe16_RANGE  8:8
#define csr_AcsmDdrWe16_BITS   0:0
#define csr_AcsmDdrWe16_MSB  8
#define csr_AcsmDdrWe16_LSB  8
#define csr_AcsmDdrWe16_MASK 0x100
#define csr_AcsmDdrCas16_RANGE  9:9
#define csr_AcsmDdrCas16_BITS   0:0
#define csr_AcsmDdrCas16_MSB  9
#define csr_AcsmDdrCas16_LSB  9
#define csr_AcsmDdrCas16_MASK 0x200
#define csr_AcsmDdrRas16_RANGE  10:10
#define csr_AcsmDdrRas16_BITS   0:0
#define csr_AcsmDdrRas16_MSB  10
#define csr_AcsmDdrRas16_LSB  10
#define csr_AcsmDdrRas16_MASK 0x400
#define csr_AcsmDdrCkeSet16_RANGE  11:11
#define csr_AcsmDdrCkeSet16_BITS   0:0
#define csr_AcsmDdrCkeSet16_MSB  11
#define csr_AcsmDdrCkeSet16_LSB  11
#define csr_AcsmDdrCkeSet16_MASK 0x800
#define csr_AcsmDdrCkeClr16_RANGE  12:12
#define csr_AcsmDdrCkeClr16_BITS   0:0
#define csr_AcsmDdrCkeClr16_MSB  12
#define csr_AcsmDdrCkeClr16_LSB  12
#define csr_AcsmDdrCkeClr16_MASK 0x1000
#define csr_AcsmSeqGateCmd16_RANGE  13:13
#define csr_AcsmSeqGateCmd16_BITS   0:0
#define csr_AcsmSeqGateCmd16_MSB  13
#define csr_AcsmSeqGateCmd16_LSB  13
#define csr_AcsmSeqGateCmd16_MASK 0x2000
#define csr_AcsmSeqTerm16_RANGE  14:14
#define csr_AcsmSeqTerm16_BITS   0:0
#define csr_AcsmSeqTerm16_MSB  14
#define csr_AcsmSeqTerm16_LSB  14
#define csr_AcsmSeqTerm16_MASK 0x4000
#define csr_AcsmLp3Ca316_RANGE  15:15
#define csr_AcsmLp3Ca316_BITS   0:0
#define csr_AcsmLp3Ca316_MSB  15
#define csr_AcsmLp3Ca316_LSB  15
#define csr_AcsmLp3Ca316_MASK 0x8000
#define csr_PPTTrainSetup_RANGE  6:0
#define csr_PPTTrainSetup_BITS   6:0
#define csr_PPTTrainSetup_MSB  6
#define csr_PPTTrainSetup_LSB  0
#define csr_PPTTrainSetup_MASK 0x7f
#define csr_PhyMstrTrainInterval_RANGE  3:0
#define csr_PhyMstrTrainInterval_BITS   3:0
#define csr_PhyMstrTrainInterval_MSB  3
#define csr_PhyMstrTrainInterval_LSB  0
#define csr_PhyMstrTrainInterval_MASK 0xf
#define csr_PhyMstrMaxReqToAck_RANGE  6:4
#define csr_PhyMstrMaxReqToAck_BITS   2:0
#define csr_PhyMstrMaxReqToAck_MSB  6
#define csr_PhyMstrMaxReqToAck_LSB  4
#define csr_PhyMstrMaxReqToAck_MASK 0x70
#define csr_MapCAB0toDfi_RANGE  3:0
#define csr_MapCAB0toDfi_BITS   3:0
#define csr_MapCAB0toDfi_MSB  3
#define csr_MapCAB0toDfi_LSB  0
#define csr_MapCAB0toDfi_MASK 0xf
#define csr_TsmByte1_RANGE  15:0
#define csr_TsmByte1_BITS   15:0
#define csr_TsmByte1_MSB  15
#define csr_TsmByte1_LSB  0
#define csr_TsmByte1_MASK 0xffff
#define csr_DtsmBdStp_RANGE  7:0
#define csr_DtsmBdStp_BITS   7:0
#define csr_DtsmBdStp_MSB  7
#define csr_DtsmBdStp_LSB  0
#define csr_DtsmBdStp_MASK 0xff
#define csr_DtsmGdStp_RANGE  15:8
#define csr_DtsmGdStp_BITS   7:0
#define csr_DtsmGdStp_MSB  15
#define csr_DtsmGdStp_LSB  8
#define csr_DtsmGdStp_MASK 0xff00
#define csr_Seq0BDisableFlag5_RANGE  15:0
#define csr_Seq0BDisableFlag5_BITS   15:0
#define csr_Seq0BDisableFlag5_MSB  15
#define csr_Seq0BDisableFlag5_LSB  0
#define csr_Seq0BDisableFlag5_MASK 0xffff
#define csr_SequenceReg0b77s1_RANGE  15:0
#define csr_SequenceReg0b77s1_BITS   15:0
#define csr_SequenceReg0b77s1_MSB  15
#define csr_SequenceReg0b77s1_LSB  0
#define csr_SequenceReg0b77s1_MASK 0xffff
#define csr_AcsmSeq0x17_RANGE  15:0
#define csr_AcsmSeq0x17_BITS   15:0
#define csr_AcsmSeq0x17_MSB  15
#define csr_AcsmSeq0x17_LSB  0
#define csr_AcsmSeq0x17_MASK 0xffff
#define csr_AcsmMclkDly17_RANGE  7:0
#define csr_AcsmMclkDly17_BITS   7:0
#define csr_AcsmMclkDly17_MSB  7
#define csr_AcsmMclkDly17_LSB  0
#define csr_AcsmMclkDly17_MASK 0xff
#define csr_AcsmDdrWe17_RANGE  8:8
#define csr_AcsmDdrWe17_BITS   0:0
#define csr_AcsmDdrWe17_MSB  8
#define csr_AcsmDdrWe17_LSB  8
#define csr_AcsmDdrWe17_MASK 0x100
#define csr_AcsmDdrCas17_RANGE  9:9
#define csr_AcsmDdrCas17_BITS   0:0
#define csr_AcsmDdrCas17_MSB  9
#define csr_AcsmDdrCas17_LSB  9
#define csr_AcsmDdrCas17_MASK 0x200
#define csr_AcsmDdrRas17_RANGE  10:10
#define csr_AcsmDdrRas17_BITS   0:0
#define csr_AcsmDdrRas17_MSB  10
#define csr_AcsmDdrRas17_LSB  10
#define csr_AcsmDdrRas17_MASK 0x400
#define csr_AcsmDdrCkeSet17_RANGE  11:11
#define csr_AcsmDdrCkeSet17_BITS   0:0
#define csr_AcsmDdrCkeSet17_MSB  11
#define csr_AcsmDdrCkeSet17_LSB  11
#define csr_AcsmDdrCkeSet17_MASK 0x800
#define csr_AcsmDdrCkeClr17_RANGE  12:12
#define csr_AcsmDdrCkeClr17_BITS   0:0
#define csr_AcsmDdrCkeClr17_MSB  12
#define csr_AcsmDdrCkeClr17_LSB  12
#define csr_AcsmDdrCkeClr17_MASK 0x1000
#define csr_AcsmSeqGateCmd17_RANGE  13:13
#define csr_AcsmSeqGateCmd17_BITS   0:0
#define csr_AcsmSeqGateCmd17_MSB  13
#define csr_AcsmSeqGateCmd17_LSB  13
#define csr_AcsmSeqGateCmd17_MASK 0x2000
#define csr_AcsmSeqTerm17_RANGE  14:14
#define csr_AcsmSeqTerm17_BITS   0:0
#define csr_AcsmSeqTerm17_MSB  14
#define csr_AcsmSeqTerm17_LSB  14
#define csr_AcsmSeqTerm17_MASK 0x4000
#define csr_AcsmLp3Ca317_RANGE  15:15
#define csr_AcsmLp3Ca317_BITS   0:0
#define csr_AcsmLp3Ca317_MSB  15
#define csr_AcsmLp3Ca317_LSB  15
#define csr_AcsmLp3Ca317_MASK 0x8000
#define csr_PPGCCtrl1_RANGE  4:1
#define csr_PPGCCtrl1_BITS   3:0
#define csr_PPGCCtrl1_MSB  4
#define csr_PPGCCtrl1_LSB  1
#define csr_PPGCCtrl1_MASK 0x1e
#define csr_HwtTxDbiEn_RANGE  1:1
#define csr_HwtTxDbiEn_BITS   0:0
#define csr_HwtTxDbiEn_MSB  1
#define csr_HwtTxDbiEn_LSB  1
#define csr_HwtTxDbiEn_MASK 0x2
#define csr_HwtRxDbiEn_RANGE  2:2
#define csr_HwtRxDbiEn_BITS   0:0
#define csr_HwtRxDbiEn_MSB  2
#define csr_HwtRxDbiEn_LSB  2
#define csr_HwtRxDbiEn_MASK 0x4
#define csr_HwtTxDmDbiVal_RANGE  3:3
#define csr_HwtTxDmDbiVal_BITS   0:0
#define csr_HwtTxDmDbiVal_MSB  3
#define csr_HwtTxDmDbiVal_LSB  3
#define csr_HwtTxDmDbiVal_MASK 0x8
#define csr_HwtTxDmDbiSel_RANGE  4:4
#define csr_HwtTxDmDbiSel_BITS   0:0
#define csr_HwtTxDmDbiSel_MSB  4
#define csr_HwtTxDmDbiSel_LSB  4
#define csr_HwtTxDmDbiSel_MASK 0x10
#define csr_PPTTrainSetup2_RANGE  2:0
#define csr_PPTTrainSetup2_BITS   2:0
#define csr_PPTTrainSetup2_MSB  2
#define csr_PPTTrainSetup2_LSB  0
#define csr_PPTTrainSetup2_MASK 0x7
#define csr_PhyMstrFreqOverride_RANGE  2:0
#define csr_PhyMstrFreqOverride_BITS   2:0
#define csr_PhyMstrFreqOverride_MSB  2
#define csr_PhyMstrFreqOverride_LSB  0
#define csr_PhyMstrFreqOverride_MASK 0x7
#define csr_MapCAB1toDfi_RANGE  3:0
#define csr_MapCAB1toDfi_BITS   3:0
#define csr_MapCAB1toDfi_MSB  3
#define csr_MapCAB1toDfi_LSB  0
#define csr_MapCAB1toDfi_MASK 0xf
#define csr_TsmByte2_RANGE  15:0
#define csr_TsmByte2_BITS   15:0
#define csr_TsmByte2_MSB  15
#define csr_TsmByte2_LSB  0
#define csr_TsmByte2_MASK 0xffff
#define csr_DtsmGdBar_RANGE  15:0
#define csr_DtsmGdBar_BITS   15:0
#define csr_DtsmGdBar_MSB  15
#define csr_DtsmGdBar_LSB  0
#define csr_DtsmGdBar_MASK 0xffff
#define csr_Seq0BDisableFlag6_RANGE  15:0
#define csr_Seq0BDisableFlag6_BITS   15:0
#define csr_Seq0BDisableFlag6_MSB  15
#define csr_Seq0BDisableFlag6_LSB  0
#define csr_Seq0BDisableFlag6_MASK 0xffff
#define csr_SequenceReg0b77s2_RANGE  8:0
#define csr_SequenceReg0b77s2_BITS   8:0
#define csr_SequenceReg0b77s2_MSB  8
#define csr_SequenceReg0b77s2_LSB  0
#define csr_SequenceReg0b77s2_MASK 0x1ff
#define csr_AcsmSeq0x18_RANGE  15:0
#define csr_AcsmSeq0x18_BITS   15:0
#define csr_AcsmSeq0x18_MSB  15
#define csr_AcsmSeq0x18_LSB  0
#define csr_AcsmSeq0x18_MASK 0xffff
#define csr_AcsmMclkDly18_RANGE  7:0
#define csr_AcsmMclkDly18_BITS   7:0
#define csr_AcsmMclkDly18_MSB  7
#define csr_AcsmMclkDly18_LSB  0
#define csr_AcsmMclkDly18_MASK 0xff
#define csr_AcsmDdrWe18_RANGE  8:8
#define csr_AcsmDdrWe18_BITS   0:0
#define csr_AcsmDdrWe18_MSB  8
#define csr_AcsmDdrWe18_LSB  8
#define csr_AcsmDdrWe18_MASK 0x100
#define csr_AcsmDdrCas18_RANGE  9:9
#define csr_AcsmDdrCas18_BITS   0:0
#define csr_AcsmDdrCas18_MSB  9
#define csr_AcsmDdrCas18_LSB  9
#define csr_AcsmDdrCas18_MASK 0x200
#define csr_AcsmDdrRas18_RANGE  10:10
#define csr_AcsmDdrRas18_BITS   0:0
#define csr_AcsmDdrRas18_MSB  10
#define csr_AcsmDdrRas18_LSB  10
#define csr_AcsmDdrRas18_MASK 0x400
#define csr_AcsmDdrCkeSet18_RANGE  11:11
#define csr_AcsmDdrCkeSet18_BITS   0:0
#define csr_AcsmDdrCkeSet18_MSB  11
#define csr_AcsmDdrCkeSet18_LSB  11
#define csr_AcsmDdrCkeSet18_MASK 0x800
#define csr_AcsmDdrCkeClr18_RANGE  12:12
#define csr_AcsmDdrCkeClr18_BITS   0:0
#define csr_AcsmDdrCkeClr18_MSB  12
#define csr_AcsmDdrCkeClr18_LSB  12
#define csr_AcsmDdrCkeClr18_MASK 0x1000
#define csr_AcsmSeqGateCmd18_RANGE  13:13
#define csr_AcsmSeqGateCmd18_BITS   0:0
#define csr_AcsmSeqGateCmd18_MSB  13
#define csr_AcsmSeqGateCmd18_LSB  13
#define csr_AcsmSeqGateCmd18_MASK 0x2000
#define csr_AcsmSeqTerm18_RANGE  14:14
#define csr_AcsmSeqTerm18_BITS   0:0
#define csr_AcsmSeqTerm18_MSB  14
#define csr_AcsmSeqTerm18_LSB  14
#define csr_AcsmSeqTerm18_MASK 0x4000
#define csr_AcsmLp3Ca318_RANGE  15:15
#define csr_AcsmLp3Ca318_BITS   0:0
#define csr_AcsmLp3Ca318_MSB  15
#define csr_AcsmLp3Ca318_LSB  15
#define csr_AcsmLp3Ca318_MASK 0x8000
#define csr_ATestMode_RANGE  4:0
#define csr_ATestMode_BITS   4:0
#define csr_ATestMode_MSB  4
#define csr_ATestMode_LSB  0
#define csr_ATestMode_MASK 0x1f
#define csr_ATestPrbsEn_RANGE  0:0
#define csr_ATestPrbsEn_BITS   0:0
#define csr_ATestPrbsEn_MSB  0
#define csr_ATestPrbsEn_LSB  0
#define csr_ATestPrbsEn_MASK 0x1
#define csr_ATestClkEn_RANGE  1:1
#define csr_ATestClkEn_BITS   0:0
#define csr_ATestClkEn_MSB  1
#define csr_ATestClkEn_LSB  1
#define csr_ATestClkEn_MASK 0x2
#define csr_ATestModeSel_RANGE  4:2
#define csr_ATestModeSel_BITS   2:0
#define csr_ATestModeSel_MSB  4
#define csr_ATestModeSel_LSB  2
#define csr_ATestModeSel_MASK 0x1c
#define csr_MapCAB2toDfi_RANGE  3:0
#define csr_MapCAB2toDfi_BITS   3:0
#define csr_MapCAB2toDfi_MSB  3
#define csr_MapCAB2toDfi_LSB  0
#define csr_MapCAB2toDfi_MASK 0xf
#define csr_TsmByte3_RANGE  8:0
#define csr_TsmByte3_BITS   8:0
#define csr_TsmByte3_MSB  8
#define csr_TsmByte3_LSB  0
#define csr_TsmByte3_MASK 0x1ff
#define csr_DtsmIncDecMode_RANGE  0:0
#define csr_DtsmIncDecMode_BITS   0:0
#define csr_DtsmIncDecMode_MSB  0
#define csr_DtsmIncDecMode_LSB  0
#define csr_DtsmIncDecMode_MASK 0x1
#define csr_DtsmIncDecCtrl_RANGE  1:1
#define csr_DtsmIncDecCtrl_BITS   0:0
#define csr_DtsmIncDecCtrl_MSB  1
#define csr_DtsmIncDecCtrl_LSB  1
#define csr_DtsmIncDecCtrl_MASK 0x2
#define csr_EnblRxSampFlops_RANGE  2:2
#define csr_EnblRxSampFlops_BITS   0:0
#define csr_EnblRxSampFlops_MSB  2
#define csr_EnblRxSampFlops_LSB  2
#define csr_EnblRxSampFlops_MASK 0x4
#define csr_SelRxSampFlops_RANGE  3:3
#define csr_SelRxSampFlops_BITS   0:0
#define csr_SelRxSampFlops_MSB  3
#define csr_SelRxSampFlops_LSB  3
#define csr_SelRxSampFlops_MASK 0x8
#define csr_SelRxBybass_RANGE  4:4
#define csr_SelRxBybass_BITS   0:0
#define csr_SelRxBybass_MSB  4
#define csr_SelRxBybass_LSB  4
#define csr_SelRxBybass_MASK 0x10
#define csr_DtsmIgnUpdateAck_RANGE  5:5
#define csr_DtsmIgnUpdateAck_BITS   0:0
#define csr_DtsmIgnUpdateAck_MSB  5
#define csr_DtsmIgnUpdateAck_LSB  5
#define csr_DtsmIgnUpdateAck_MASK 0x20
#define csr_EnableRxDqAsync_RANGE  6:6
#define csr_EnableRxDqAsync_BITS   0:0
#define csr_EnableRxDqAsync_MSB  6
#define csr_EnableRxDqAsync_LSB  6
#define csr_EnableRxDqAsync_MASK 0x40
#define csr_DtsmStaticCmpr_RANGE  7:7
#define csr_DtsmStaticCmpr_BITS   0:0
#define csr_DtsmStaticCmpr_MSB  7
#define csr_DtsmStaticCmpr_LSB  7
#define csr_DtsmStaticCmpr_MASK 0x80
#define csr_DtsmStaticCmprVal_RANGE  8:8
#define csr_DtsmStaticCmprVal_BITS   0:0
#define csr_DtsmStaticCmprVal_MSB  8
#define csr_DtsmStaticCmprVal_LSB  8
#define csr_DtsmStaticCmprVal_MASK 0x100
#define csr_Seq0BDisableFlag7_RANGE  15:0
#define csr_Seq0BDisableFlag7_BITS   15:0
#define csr_Seq0BDisableFlag7_MSB  15
#define csr_Seq0BDisableFlag7_LSB  0
#define csr_Seq0BDisableFlag7_MASK 0xffff
#define csr_SequenceReg0b78s0_RANGE  15:0
#define csr_SequenceReg0b78s0_BITS   15:0
#define csr_SequenceReg0b78s0_MSB  15
#define csr_SequenceReg0b78s0_LSB  0
#define csr_SequenceReg0b78s0_MASK 0xffff
#define csr_AcsmSeq0x19_RANGE  15:0
#define csr_AcsmSeq0x19_BITS   15:0
#define csr_AcsmSeq0x19_MSB  15
#define csr_AcsmSeq0x19_LSB  0
#define csr_AcsmSeq0x19_MASK 0xffff
#define csr_AcsmMclkDly19_RANGE  7:0
#define csr_AcsmMclkDly19_BITS   7:0
#define csr_AcsmMclkDly19_MSB  7
#define csr_AcsmMclkDly19_LSB  0
#define csr_AcsmMclkDly19_MASK 0xff
#define csr_AcsmDdrWe19_RANGE  8:8
#define csr_AcsmDdrWe19_BITS   0:0
#define csr_AcsmDdrWe19_MSB  8
#define csr_AcsmDdrWe19_LSB  8
#define csr_AcsmDdrWe19_MASK 0x100
#define csr_AcsmDdrCas19_RANGE  9:9
#define csr_AcsmDdrCas19_BITS   0:0
#define csr_AcsmDdrCas19_MSB  9
#define csr_AcsmDdrCas19_LSB  9
#define csr_AcsmDdrCas19_MASK 0x200
#define csr_AcsmDdrRas19_RANGE  10:10
#define csr_AcsmDdrRas19_BITS   0:0
#define csr_AcsmDdrRas19_MSB  10
#define csr_AcsmDdrRas19_LSB  10
#define csr_AcsmDdrRas19_MASK 0x400
#define csr_AcsmDdrCkeSet19_RANGE  11:11
#define csr_AcsmDdrCkeSet19_BITS   0:0
#define csr_AcsmDdrCkeSet19_MSB  11
#define csr_AcsmDdrCkeSet19_LSB  11
#define csr_AcsmDdrCkeSet19_MASK 0x800
#define csr_AcsmDdrCkeClr19_RANGE  12:12
#define csr_AcsmDdrCkeClr19_BITS   0:0
#define csr_AcsmDdrCkeClr19_MSB  12
#define csr_AcsmDdrCkeClr19_LSB  12
#define csr_AcsmDdrCkeClr19_MASK 0x1000
#define csr_AcsmSeqGateCmd19_RANGE  13:13
#define csr_AcsmSeqGateCmd19_BITS   0:0
#define csr_AcsmSeqGateCmd19_MSB  13
#define csr_AcsmSeqGateCmd19_LSB  13
#define csr_AcsmSeqGateCmd19_MASK 0x2000
#define csr_AcsmSeqTerm19_RANGE  14:14
#define csr_AcsmSeqTerm19_BITS   0:0
#define csr_AcsmSeqTerm19_MSB  14
#define csr_AcsmSeqTerm19_LSB  14
#define csr_AcsmSeqTerm19_MASK 0x4000
#define csr_AcsmLp3Ca319_RANGE  15:15
#define csr_AcsmLp3Ca319_BITS   0:0
#define csr_AcsmLp3Ca319_MSB  15
#define csr_AcsmLp3Ca319_LSB  15
#define csr_AcsmLp3Ca319_MASK 0x8000
#define csr_MapCAB3toDfi_RANGE  3:0
#define csr_MapCAB3toDfi_BITS   3:0
#define csr_MapCAB3toDfi_MSB  3
#define csr_MapCAB3toDfi_LSB  0
#define csr_MapCAB3toDfi_MASK 0xf
#define csr_TsmByte4_RANGE  3:0
#define csr_TsmByte4_BITS   3:0
#define csr_TsmByte4_MSB  3
#define csr_TsmByte4_LSB  0
#define csr_TsmByte4_MASK 0xf
#define csr_DtsmIncDecPw_RANGE  3:0
#define csr_DtsmIncDecPw_BITS   3:0
#define csr_DtsmIncDecPw_MSB  3
#define csr_DtsmIncDecPw_LSB  0
#define csr_DtsmIncDecPw_MASK 0xf
#define csr_SequenceReg0b78s1_RANGE  15:0
#define csr_SequenceReg0b78s1_BITS   15:0
#define csr_SequenceReg0b78s1_MSB  15
#define csr_SequenceReg0b78s1_LSB  0
#define csr_SequenceReg0b78s1_MASK 0xffff
#define csr_AcsmSeq0x20_RANGE  15:0
#define csr_AcsmSeq0x20_BITS   15:0
#define csr_AcsmSeq0x20_MSB  15
#define csr_AcsmSeq0x20_LSB  0
#define csr_AcsmSeq0x20_MASK 0xffff
#define csr_AcsmMclkDly20_RANGE  7:0
#define csr_AcsmMclkDly20_BITS   7:0
#define csr_AcsmMclkDly20_MSB  7
#define csr_AcsmMclkDly20_LSB  0
#define csr_AcsmMclkDly20_MASK 0xff
#define csr_AcsmDdrWe20_RANGE  8:8
#define csr_AcsmDdrWe20_BITS   0:0
#define csr_AcsmDdrWe20_MSB  8
#define csr_AcsmDdrWe20_LSB  8
#define csr_AcsmDdrWe20_MASK 0x100
#define csr_AcsmDdrCas20_RANGE  9:9
#define csr_AcsmDdrCas20_BITS   0:0
#define csr_AcsmDdrCas20_MSB  9
#define csr_AcsmDdrCas20_LSB  9
#define csr_AcsmDdrCas20_MASK 0x200
#define csr_AcsmDdrRas20_RANGE  10:10
#define csr_AcsmDdrRas20_BITS   0:0
#define csr_AcsmDdrRas20_MSB  10
#define csr_AcsmDdrRas20_LSB  10
#define csr_AcsmDdrRas20_MASK 0x400
#define csr_AcsmDdrCkeSet20_RANGE  11:11
#define csr_AcsmDdrCkeSet20_BITS   0:0
#define csr_AcsmDdrCkeSet20_MSB  11
#define csr_AcsmDdrCkeSet20_LSB  11
#define csr_AcsmDdrCkeSet20_MASK 0x800
#define csr_AcsmDdrCkeClr20_RANGE  12:12
#define csr_AcsmDdrCkeClr20_BITS   0:0
#define csr_AcsmDdrCkeClr20_MSB  12
#define csr_AcsmDdrCkeClr20_LSB  12
#define csr_AcsmDdrCkeClr20_MASK 0x1000
#define csr_AcsmSeqGateCmd20_RANGE  13:13
#define csr_AcsmSeqGateCmd20_BITS   0:0
#define csr_AcsmSeqGateCmd20_MSB  13
#define csr_AcsmSeqGateCmd20_LSB  13
#define csr_AcsmSeqGateCmd20_MASK 0x2000
#define csr_AcsmSeqTerm20_RANGE  14:14
#define csr_AcsmSeqTerm20_BITS   0:0
#define csr_AcsmSeqTerm20_MSB  14
#define csr_AcsmSeqTerm20_LSB  14
#define csr_AcsmSeqTerm20_MASK 0x4000
#define csr_AcsmLp3Ca320_RANGE  15:15
#define csr_AcsmLp3Ca320_BITS   0:0
#define csr_AcsmLp3Ca320_MSB  15
#define csr_AcsmLp3Ca320_LSB  15
#define csr_AcsmLp3Ca320_MASK 0x8000
#define csr_TxCalBinP_RANGE  4:0
#define csr_TxCalBinP_BITS   4:0
#define csr_TxCalBinP_MSB  4
#define csr_TxCalBinP_LSB  0
#define csr_TxCalBinP_MASK 0x1f
#define csr_MapCAB4toDfi_RANGE  3:0
#define csr_MapCAB4toDfi_BITS   3:0
#define csr_MapCAB4toDfi_MSB  3
#define csr_MapCAB4toDfi_LSB  0
#define csr_MapCAB4toDfi_MASK 0xf
#define csr_PpgcLane2CrcInMap0_RANGE  11:0
#define csr_PpgcLane2CrcInMap0_BITS   11:0
#define csr_PpgcLane2CrcInMap0_MSB  11
#define csr_PpgcLane2CrcInMap0_LSB  0
#define csr_PpgcLane2CrcInMap0_MASK 0xfff
#define csr_PpgcCrcLaneMap0_RANGE  2:0
#define csr_PpgcCrcLaneMap0_BITS   2:0
#define csr_PpgcCrcLaneMap0_MSB  2
#define csr_PpgcCrcLaneMap0_LSB  0
#define csr_PpgcCrcLaneMap0_MASK 0x7
#define csr_PpgcCrcLaneMap1_RANGE  5:3
#define csr_PpgcCrcLaneMap1_BITS   2:0
#define csr_PpgcCrcLaneMap1_MSB  5
#define csr_PpgcCrcLaneMap1_LSB  3
#define csr_PpgcCrcLaneMap1_MASK 0x38
#define csr_PpgcCrcLaneMap2_RANGE  8:6
#define csr_PpgcCrcLaneMap2_BITS   2:0
#define csr_PpgcCrcLaneMap2_MSB  8
#define csr_PpgcCrcLaneMap2_LSB  6
#define csr_PpgcCrcLaneMap2_MASK 0x1c0
#define csr_PpgcCrcLaneMap3_RANGE  11:9
#define csr_PpgcCrcLaneMap3_BITS   2:0
#define csr_PpgcCrcLaneMap3_MSB  11
#define csr_PpgcCrcLaneMap3_LSB  9
#define csr_PpgcCrcLaneMap3_MASK 0xe00
#define csr_SequenceReg0b78s2_RANGE  8:0
#define csr_SequenceReg0b78s2_BITS   8:0
#define csr_SequenceReg0b78s2_MSB  8
#define csr_SequenceReg0b78s2_LSB  0
#define csr_SequenceReg0b78s2_MASK 0x1ff
#define csr_AcsmSeq0x21_RANGE  15:0
#define csr_AcsmSeq0x21_BITS   15:0
#define csr_AcsmSeq0x21_MSB  15
#define csr_AcsmSeq0x21_LSB  0
#define csr_AcsmSeq0x21_MASK 0xffff
#define csr_AcsmMclkDly21_RANGE  7:0
#define csr_AcsmMclkDly21_BITS   7:0
#define csr_AcsmMclkDly21_MSB  7
#define csr_AcsmMclkDly21_LSB  0
#define csr_AcsmMclkDly21_MASK 0xff
#define csr_AcsmDdrWe21_RANGE  8:8
#define csr_AcsmDdrWe21_BITS   0:0
#define csr_AcsmDdrWe21_MSB  8
#define csr_AcsmDdrWe21_LSB  8
#define csr_AcsmDdrWe21_MASK 0x100
#define csr_AcsmDdrCas21_RANGE  9:9
#define csr_AcsmDdrCas21_BITS   0:0
#define csr_AcsmDdrCas21_MSB  9
#define csr_AcsmDdrCas21_LSB  9
#define csr_AcsmDdrCas21_MASK 0x200
#define csr_AcsmDdrRas21_RANGE  10:10
#define csr_AcsmDdrRas21_BITS   0:0
#define csr_AcsmDdrRas21_MSB  10
#define csr_AcsmDdrRas21_LSB  10
#define csr_AcsmDdrRas21_MASK 0x400
#define csr_AcsmDdrCkeSet21_RANGE  11:11
#define csr_AcsmDdrCkeSet21_BITS   0:0
#define csr_AcsmDdrCkeSet21_MSB  11
#define csr_AcsmDdrCkeSet21_LSB  11
#define csr_AcsmDdrCkeSet21_MASK 0x800
#define csr_AcsmDdrCkeClr21_RANGE  12:12
#define csr_AcsmDdrCkeClr21_BITS   0:0
#define csr_AcsmDdrCkeClr21_MSB  12
#define csr_AcsmDdrCkeClr21_LSB  12
#define csr_AcsmDdrCkeClr21_MASK 0x1000
#define csr_AcsmSeqGateCmd21_RANGE  13:13
#define csr_AcsmSeqGateCmd21_BITS   0:0
#define csr_AcsmSeqGateCmd21_MSB  13
#define csr_AcsmSeqGateCmd21_LSB  13
#define csr_AcsmSeqGateCmd21_MASK 0x2000
#define csr_AcsmSeqTerm21_RANGE  14:14
#define csr_AcsmSeqTerm21_BITS   0:0
#define csr_AcsmSeqTerm21_MSB  14
#define csr_AcsmSeqTerm21_LSB  14
#define csr_AcsmSeqTerm21_MASK 0x4000
#define csr_AcsmLp3Ca321_RANGE  15:15
#define csr_AcsmLp3Ca321_BITS   0:0
#define csr_AcsmLp3Ca321_MSB  15
#define csr_AcsmLp3Ca321_LSB  15
#define csr_AcsmLp3Ca321_MASK 0x8000
#define csr_TxCalBinN_RANGE  4:0
#define csr_TxCalBinN_BITS   4:0
#define csr_TxCalBinN_MSB  4
#define csr_TxCalBinN_LSB  0
#define csr_TxCalBinN_MASK 0x1f
#define csr_MapCAB5toDfi_RANGE  3:0
#define csr_MapCAB5toDfi_BITS   3:0
#define csr_MapCAB5toDfi_MSB  3
#define csr_MapCAB5toDfi_LSB  0
#define csr_MapCAB5toDfi_MASK 0xf
#define csr_PpgcLane2CrcInMap1_RANGE  11:0
#define csr_PpgcLane2CrcInMap1_BITS   11:0
#define csr_PpgcLane2CrcInMap1_MSB  11
#define csr_PpgcLane2CrcInMap1_LSB  0
#define csr_PpgcLane2CrcInMap1_MASK 0xfff
#define csr_PpgcCrcLaneMap4_RANGE  2:0
#define csr_PpgcCrcLaneMap4_BITS   2:0
#define csr_PpgcCrcLaneMap4_MSB  2
#define csr_PpgcCrcLaneMap4_LSB  0
#define csr_PpgcCrcLaneMap4_MASK 0x7
#define csr_PpgcCrcLaneMap5_RANGE  5:3
#define csr_PpgcCrcLaneMap5_BITS   2:0
#define csr_PpgcCrcLaneMap5_MSB  5
#define csr_PpgcCrcLaneMap5_LSB  3
#define csr_PpgcCrcLaneMap5_MASK 0x38
#define csr_PpgcCrcLaneMap6_RANGE  8:6
#define csr_PpgcCrcLaneMap6_BITS   2:0
#define csr_PpgcCrcLaneMap6_MSB  8
#define csr_PpgcCrcLaneMap6_LSB  6
#define csr_PpgcCrcLaneMap6_MASK 0x1c0
#define csr_PpgcCrcLaneMap7_RANGE  11:9
#define csr_PpgcCrcLaneMap7_BITS   2:0
#define csr_PpgcCrcLaneMap7_MSB  11
#define csr_PpgcCrcLaneMap7_LSB  9
#define csr_PpgcCrcLaneMap7_MASK 0xe00
#define csr_SequenceReg0b79s0_RANGE  15:0
#define csr_SequenceReg0b79s0_BITS   15:0
#define csr_SequenceReg0b79s0_MSB  15
#define csr_SequenceReg0b79s0_LSB  0
#define csr_SequenceReg0b79s0_MASK 0xffff
#define csr_AcsmSeq0x22_RANGE  15:0
#define csr_AcsmSeq0x22_BITS   15:0
#define csr_AcsmSeq0x22_MSB  15
#define csr_AcsmSeq0x22_LSB  0
#define csr_AcsmSeq0x22_MASK 0xffff
#define csr_AcsmMclkDly22_RANGE  7:0
#define csr_AcsmMclkDly22_BITS   7:0
#define csr_AcsmMclkDly22_MSB  7
#define csr_AcsmMclkDly22_LSB  0
#define csr_AcsmMclkDly22_MASK 0xff
#define csr_AcsmDdrWe22_RANGE  8:8
#define csr_AcsmDdrWe22_BITS   0:0
#define csr_AcsmDdrWe22_MSB  8
#define csr_AcsmDdrWe22_LSB  8
#define csr_AcsmDdrWe22_MASK 0x100
#define csr_AcsmDdrCas22_RANGE  9:9
#define csr_AcsmDdrCas22_BITS   0:0
#define csr_AcsmDdrCas22_MSB  9
#define csr_AcsmDdrCas22_LSB  9
#define csr_AcsmDdrCas22_MASK 0x200
#define csr_AcsmDdrRas22_RANGE  10:10
#define csr_AcsmDdrRas22_BITS   0:0
#define csr_AcsmDdrRas22_MSB  10
#define csr_AcsmDdrRas22_LSB  10
#define csr_AcsmDdrRas22_MASK 0x400
#define csr_AcsmDdrCkeSet22_RANGE  11:11
#define csr_AcsmDdrCkeSet22_BITS   0:0
#define csr_AcsmDdrCkeSet22_MSB  11
#define csr_AcsmDdrCkeSet22_LSB  11
#define csr_AcsmDdrCkeSet22_MASK 0x800
#define csr_AcsmDdrCkeClr22_RANGE  12:12
#define csr_AcsmDdrCkeClr22_BITS   0:0
#define csr_AcsmDdrCkeClr22_MSB  12
#define csr_AcsmDdrCkeClr22_LSB  12
#define csr_AcsmDdrCkeClr22_MASK 0x1000
#define csr_AcsmSeqGateCmd22_RANGE  13:13
#define csr_AcsmSeqGateCmd22_BITS   0:0
#define csr_AcsmSeqGateCmd22_MSB  13
#define csr_AcsmSeqGateCmd22_LSB  13
#define csr_AcsmSeqGateCmd22_MASK 0x2000
#define csr_AcsmSeqTerm22_RANGE  14:14
#define csr_AcsmSeqTerm22_BITS   0:0
#define csr_AcsmSeqTerm22_MSB  14
#define csr_AcsmSeqTerm22_LSB  14
#define csr_AcsmSeqTerm22_MASK 0x4000
#define csr_AcsmLp3Ca322_RANGE  15:15
#define csr_AcsmLp3Ca322_BITS   0:0
#define csr_AcsmLp3Ca322_MSB  15
#define csr_AcsmLp3Ca322_LSB  15
#define csr_AcsmLp3Ca322_MASK 0x8000
#define csr_TxCalPOvr_RANGE  5:0
#define csr_TxCalPOvr_BITS   5:0
#define csr_TxCalPOvr_MSB  5
#define csr_TxCalPOvr_LSB  0
#define csr_TxCalPOvr_MASK 0x3f
#define csr_TxCalBinPOvrVal_RANGE  4:0
#define csr_TxCalBinPOvrVal_BITS   4:0
#define csr_TxCalBinPOvrVal_MSB  4
#define csr_TxCalBinPOvrVal_LSB  0
#define csr_TxCalBinPOvrVal_MASK 0x1f
#define csr_TxCalBinPOvrEn_RANGE  5:5
#define csr_TxCalBinPOvrEn_BITS   0:0
#define csr_TxCalBinPOvrEn_MSB  5
#define csr_TxCalBinPOvrEn_LSB  5
#define csr_TxCalBinPOvrEn_MASK 0x20
#define csr_MapCAB6toDfi_RANGE  3:0
#define csr_MapCAB6toDfi_BITS   3:0
#define csr_MapCAB6toDfi_MSB  3
#define csr_MapCAB6toDfi_LSB  0
#define csr_MapCAB6toDfi_MASK 0xf
#define csr_StartVector0b0_RANGE  6:0
#define csr_StartVector0b0_BITS   6:0
#define csr_StartVector0b0_MSB  6
#define csr_StartVector0b0_LSB  0
#define csr_StartVector0b0_MASK 0x7f
#define csr_Seq0BStartVec0_RANGE  6:0
#define csr_Seq0BStartVec0_BITS   6:0
#define csr_Seq0BStartVec0_MSB  6
#define csr_Seq0BStartVec0_LSB  0
#define csr_Seq0BStartVec0_MASK 0x7f
#define csr_SequenceReg0b79s1_RANGE  15:0
#define csr_SequenceReg0b79s1_BITS   15:0
#define csr_SequenceReg0b79s1_MSB  15
#define csr_SequenceReg0b79s1_LSB  0
#define csr_SequenceReg0b79s1_MASK 0xffff
#define csr_AcsmSeq0x23_RANGE  15:0
#define csr_AcsmSeq0x23_BITS   15:0
#define csr_AcsmSeq0x23_MSB  15
#define csr_AcsmSeq0x23_LSB  0
#define csr_AcsmSeq0x23_MASK 0xffff
#define csr_AcsmMclkDly23_RANGE  7:0
#define csr_AcsmMclkDly23_BITS   7:0
#define csr_AcsmMclkDly23_MSB  7
#define csr_AcsmMclkDly23_LSB  0
#define csr_AcsmMclkDly23_MASK 0xff
#define csr_AcsmDdrWe23_RANGE  8:8
#define csr_AcsmDdrWe23_BITS   0:0
#define csr_AcsmDdrWe23_MSB  8
#define csr_AcsmDdrWe23_LSB  8
#define csr_AcsmDdrWe23_MASK 0x100
#define csr_AcsmDdrCas23_RANGE  9:9
#define csr_AcsmDdrCas23_BITS   0:0
#define csr_AcsmDdrCas23_MSB  9
#define csr_AcsmDdrCas23_LSB  9
#define csr_AcsmDdrCas23_MASK 0x200
#define csr_AcsmDdrRas23_RANGE  10:10
#define csr_AcsmDdrRas23_BITS   0:0
#define csr_AcsmDdrRas23_MSB  10
#define csr_AcsmDdrRas23_LSB  10
#define csr_AcsmDdrRas23_MASK 0x400
#define csr_AcsmDdrCkeSet23_RANGE  11:11
#define csr_AcsmDdrCkeSet23_BITS   0:0
#define csr_AcsmDdrCkeSet23_MSB  11
#define csr_AcsmDdrCkeSet23_LSB  11
#define csr_AcsmDdrCkeSet23_MASK 0x800
#define csr_AcsmDdrCkeClr23_RANGE  12:12
#define csr_AcsmDdrCkeClr23_BITS   0:0
#define csr_AcsmDdrCkeClr23_MSB  12
#define csr_AcsmDdrCkeClr23_LSB  12
#define csr_AcsmDdrCkeClr23_MASK 0x1000
#define csr_AcsmSeqGateCmd23_RANGE  13:13
#define csr_AcsmSeqGateCmd23_BITS   0:0
#define csr_AcsmSeqGateCmd23_MSB  13
#define csr_AcsmSeqGateCmd23_LSB  13
#define csr_AcsmSeqGateCmd23_MASK 0x2000
#define csr_AcsmSeqTerm23_RANGE  14:14
#define csr_AcsmSeqTerm23_BITS   0:0
#define csr_AcsmSeqTerm23_MSB  14
#define csr_AcsmSeqTerm23_LSB  14
#define csr_AcsmSeqTerm23_MASK 0x4000
#define csr_AcsmLp3Ca323_RANGE  15:15
#define csr_AcsmLp3Ca323_BITS   0:0
#define csr_AcsmLp3Ca323_MSB  15
#define csr_AcsmLp3Ca323_LSB  15
#define csr_AcsmLp3Ca323_MASK 0x8000
#define csr_TestModeConfig_RANGE  9:0
#define csr_TestModeConfig_BITS   9:0
#define csr_TestModeConfig_MSB  9
#define csr_TestModeConfig_LSB  0
#define csr_TestModeConfig_MASK 0x3ff
#define csr_LoopBackEn_RANGE  0:0
#define csr_LoopBackEn_BITS   0:0
#define csr_LoopBackEn_MSB  0
#define csr_LoopBackEn_LSB  0
#define csr_LoopBackEn_MASK 0x1
#define csr_RSVDTestDllEn_RANGE  1:1
#define csr_RSVDTestDllEn_BITS   0:0
#define csr_RSVDTestDllEn_MSB  1
#define csr_RSVDTestDllEn_LSB  1
#define csr_RSVDTestDllEn_MASK 0x2
#define csr_RSVDTwoTckTxDqsPre_RANGE  2:2
#define csr_RSVDTwoTckTxDqsPre_BITS   0:0
#define csr_RSVDTwoTckTxDqsPre_MSB  2
#define csr_RSVDTwoTckTxDqsPre_LSB  2
#define csr_RSVDTwoTckTxDqsPre_MASK 0x4
#define csr_TestModeRSVD_RANGE  7:3
#define csr_TestModeRSVD_BITS   4:0
#define csr_TestModeRSVD_MSB  7
#define csr_TestModeRSVD_LSB  3
#define csr_TestModeRSVD_MASK 0xf8
#define csr_LoopBackDisDqsTri_RANGE  8:8
#define csr_LoopBackDisDqsTri_BITS   0:0
#define csr_LoopBackDisDqsTri_MSB  8
#define csr_LoopBackDisDqsTri_LSB  8
#define csr_LoopBackDisDqsTri_MASK 0x100
#define csr_RSVDDisTxDqEqPreamble_RANGE  9:9
#define csr_RSVDDisTxDqEqPreamble_BITS   0:0
#define csr_RSVDDisTxDqEqPreamble_MSB  9
#define csr_RSVDDisTxDqEqPreamble_LSB  9
#define csr_RSVDDisTxDqEqPreamble_MASK 0x200
#define csr_TxCalNOvr_RANGE  5:0
#define csr_TxCalNOvr_BITS   5:0
#define csr_TxCalNOvr_MSB  5
#define csr_TxCalNOvr_LSB  0
#define csr_TxCalNOvr_MASK 0x3f
#define csr_TxCalBinNOvrVal_RANGE  4:0
#define csr_TxCalBinNOvrVal_BITS   4:0
#define csr_TxCalBinNOvrVal_MSB  4
#define csr_TxCalBinNOvrVal_LSB  0
#define csr_TxCalBinNOvrVal_MASK 0x1f
#define csr_TxCalBinNOvrEn_RANGE  5:5
#define csr_TxCalBinNOvrEn_BITS   0:0
#define csr_TxCalBinNOvrEn_MSB  5
#define csr_TxCalBinNOvrEn_LSB  5
#define csr_TxCalBinNOvrEn_MASK 0x20
#define csr_MapCAB7toDfi_RANGE  3:0
#define csr_MapCAB7toDfi_BITS   3:0
#define csr_MapCAB7toDfi_MSB  3
#define csr_MapCAB7toDfi_LSB  0
#define csr_MapCAB7toDfi_MASK 0xf
#define csr_TsmByte5_RANGE  15:0
#define csr_TsmByte5_BITS   15:0
#define csr_TsmByte5_MSB  15
#define csr_TsmByte5_LSB  0
#define csr_TsmByte5_MASK 0xffff
#define csr_DtsmBdBar_RANGE  15:0
#define csr_DtsmBdBar_BITS   15:0
#define csr_DtsmBdBar_MSB  15
#define csr_DtsmBdBar_LSB  0
#define csr_DtsmBdBar_MASK 0xffff
#define csr_StartVector0b1_RANGE  6:0
#define csr_StartVector0b1_BITS   6:0
#define csr_StartVector0b1_MSB  6
#define csr_StartVector0b1_LSB  0
#define csr_StartVector0b1_MASK 0x7f
#define csr_Seq0BStartVec1_RANGE  6:0
#define csr_Seq0BStartVec1_BITS   6:0
#define csr_Seq0BStartVec1_MSB  6
#define csr_Seq0BStartVec1_LSB  0
#define csr_Seq0BStartVec1_MASK 0x7f
#define csr_SequenceReg0b79s2_RANGE  8:0
#define csr_SequenceReg0b79s2_BITS   8:0
#define csr_SequenceReg0b79s2_MSB  8
#define csr_SequenceReg0b79s2_LSB  0
#define csr_SequenceReg0b79s2_MASK 0x1ff
#define csr_AcsmSeq0x24_RANGE  15:0
#define csr_AcsmSeq0x24_BITS   15:0
#define csr_AcsmSeq0x24_MSB  15
#define csr_AcsmSeq0x24_LSB  0
#define csr_AcsmSeq0x24_MASK 0xffff
#define csr_AcsmMclkDly24_RANGE  7:0
#define csr_AcsmMclkDly24_BITS   7:0
#define csr_AcsmMclkDly24_MSB  7
#define csr_AcsmMclkDly24_LSB  0
#define csr_AcsmMclkDly24_MASK 0xff
#define csr_AcsmDdrWe24_RANGE  8:8
#define csr_AcsmDdrWe24_BITS   0:0
#define csr_AcsmDdrWe24_MSB  8
#define csr_AcsmDdrWe24_LSB  8
#define csr_AcsmDdrWe24_MASK 0x100
#define csr_AcsmDdrCas24_RANGE  9:9
#define csr_AcsmDdrCas24_BITS   0:0
#define csr_AcsmDdrCas24_MSB  9
#define csr_AcsmDdrCas24_LSB  9
#define csr_AcsmDdrCas24_MASK 0x200
#define csr_AcsmDdrRas24_RANGE  10:10
#define csr_AcsmDdrRas24_BITS   0:0
#define csr_AcsmDdrRas24_MSB  10
#define csr_AcsmDdrRas24_LSB  10
#define csr_AcsmDdrRas24_MASK 0x400
#define csr_AcsmDdrCkeSet24_RANGE  11:11
#define csr_AcsmDdrCkeSet24_BITS   0:0
#define csr_AcsmDdrCkeSet24_MSB  11
#define csr_AcsmDdrCkeSet24_LSB  11
#define csr_AcsmDdrCkeSet24_MASK 0x800
#define csr_AcsmDdrCkeClr24_RANGE  12:12
#define csr_AcsmDdrCkeClr24_BITS   0:0
#define csr_AcsmDdrCkeClr24_MSB  12
#define csr_AcsmDdrCkeClr24_LSB  12
#define csr_AcsmDdrCkeClr24_MASK 0x1000
#define csr_AcsmSeqGateCmd24_RANGE  13:13
#define csr_AcsmSeqGateCmd24_BITS   0:0
#define csr_AcsmSeqGateCmd24_MSB  13
#define csr_AcsmSeqGateCmd24_LSB  13
#define csr_AcsmSeqGateCmd24_MASK 0x2000
#define csr_AcsmSeqTerm24_RANGE  14:14
#define csr_AcsmSeqTerm24_BITS   0:0
#define csr_AcsmSeqTerm24_MSB  14
#define csr_AcsmSeqTerm24_LSB  14
#define csr_AcsmSeqTerm24_MASK 0x4000
#define csr_AcsmLp3Ca324_RANGE  15:15
#define csr_AcsmLp3Ca324_BITS   0:0
#define csr_AcsmLp3Ca324_MSB  15
#define csr_AcsmLp3Ca324_LSB  15
#define csr_AcsmLp3Ca324_MASK 0x8000
#define csr_DfiMode_RANGE  2:0
#define csr_DfiMode_BITS   2:0
#define csr_DfiMode_MSB  2
#define csr_DfiMode_LSB  0
#define csr_DfiMode_MASK 0x7
#define csr_Dfi0Enable_RANGE  0:0
#define csr_Dfi0Enable_BITS   0:0
#define csr_Dfi0Enable_MSB  0
#define csr_Dfi0Enable_LSB  0
#define csr_Dfi0Enable_MASK 0x1
#define csr_Dfi1Enable_RANGE  1:1
#define csr_Dfi1Enable_BITS   0:0
#define csr_Dfi1Enable_MSB  1
#define csr_Dfi1Enable_LSB  1
#define csr_Dfi1Enable_MASK 0x2
#define csr_Dfi1Override_RANGE  2:2
#define csr_Dfi1Override_BITS   0:0
#define csr_Dfi1Override_MSB  2
#define csr_Dfi1Override_LSB  2
#define csr_Dfi1Override_MASK 0x4
#define csr_MapCAB8toDfi_RANGE  3:0
#define csr_MapCAB8toDfi_BITS   3:0
#define csr_MapCAB8toDfi_MSB  3
#define csr_MapCAB8toDfi_LSB  0
#define csr_MapCAB8toDfi_MASK 0xf
#define csr_TristateModeCA_RANGE  3:0
#define csr_TristateModeCA_BITS   3:0
#define csr_TristateModeCA_MSB  3
#define csr_TristateModeCA_LSB  0
#define csr_TristateModeCA_MASK 0xf
#define csr_DisDynAdrTri_RANGE  0:0
#define csr_DisDynAdrTri_BITS   0:0
#define csr_DisDynAdrTri_MSB  0
#define csr_DisDynAdrTri_LSB  0
#define csr_DisDynAdrTri_MASK 0x1
#define csr_DDR2TMode_RANGE  1:1
#define csr_DDR2TMode_BITS   0:0
#define csr_DDR2TMode_MSB  1
#define csr_DDR2TMode_LSB  1
#define csr_DDR2TMode_MASK 0x2
#define csr_CkDisVal_RANGE  3:2
#define csr_CkDisVal_BITS   1:0
#define csr_CkDisVal_MSB  3
#define csr_CkDisVal_LSB  2
#define csr_CkDisVal_MASK 0xc
#define csr_StartVector0b2_RANGE  6:0
#define csr_StartVector0b2_BITS   6:0
#define csr_StartVector0b2_MSB  6
#define csr_StartVector0b2_LSB  0
#define csr_StartVector0b2_MASK 0x7f
#define csr_Seq0BStartVec2_RANGE  6:0
#define csr_Seq0BStartVec2_BITS   6:0
#define csr_Seq0BStartVec2_MSB  6
#define csr_Seq0BStartVec2_LSB  0
#define csr_Seq0BStartVec2_MASK 0x7f
#define csr_SequenceReg0b80s0_RANGE  15:0
#define csr_SequenceReg0b80s0_BITS   15:0
#define csr_SequenceReg0b80s0_MSB  15
#define csr_SequenceReg0b80s0_LSB  0
#define csr_SequenceReg0b80s0_MASK 0xffff
#define csr_AcsmSeq0x25_RANGE  15:0
#define csr_AcsmSeq0x25_BITS   15:0
#define csr_AcsmSeq0x25_MSB  15
#define csr_AcsmSeq0x25_LSB  0
#define csr_AcsmSeq0x25_MASK 0xffff
#define csr_AcsmMclkDly25_RANGE  7:0
#define csr_AcsmMclkDly25_BITS   7:0
#define csr_AcsmMclkDly25_MSB  7
#define csr_AcsmMclkDly25_LSB  0
#define csr_AcsmMclkDly25_MASK 0xff
#define csr_AcsmDdrWe25_RANGE  8:8
#define csr_AcsmDdrWe25_BITS   0:0
#define csr_AcsmDdrWe25_MSB  8
#define csr_AcsmDdrWe25_LSB  8
#define csr_AcsmDdrWe25_MASK 0x100
#define csr_AcsmDdrCas25_RANGE  9:9
#define csr_AcsmDdrCas25_BITS   0:0
#define csr_AcsmDdrCas25_MSB  9
#define csr_AcsmDdrCas25_LSB  9
#define csr_AcsmDdrCas25_MASK 0x200
#define csr_AcsmDdrRas25_RANGE  10:10
#define csr_AcsmDdrRas25_BITS   0:0
#define csr_AcsmDdrRas25_MSB  10
#define csr_AcsmDdrRas25_LSB  10
#define csr_AcsmDdrRas25_MASK 0x400
#define csr_AcsmDdrCkeSet25_RANGE  11:11
#define csr_AcsmDdrCkeSet25_BITS   0:0
#define csr_AcsmDdrCkeSet25_MSB  11
#define csr_AcsmDdrCkeSet25_LSB  11
#define csr_AcsmDdrCkeSet25_MASK 0x800
#define csr_AcsmDdrCkeClr25_RANGE  12:12
#define csr_AcsmDdrCkeClr25_BITS   0:0
#define csr_AcsmDdrCkeClr25_MSB  12
#define csr_AcsmDdrCkeClr25_LSB  12
#define csr_AcsmDdrCkeClr25_MASK 0x1000
#define csr_AcsmSeqGateCmd25_RANGE  13:13
#define csr_AcsmSeqGateCmd25_BITS   0:0
#define csr_AcsmSeqGateCmd25_MSB  13
#define csr_AcsmSeqGateCmd25_LSB  13
#define csr_AcsmSeqGateCmd25_MASK 0x2000
#define csr_AcsmSeqTerm25_RANGE  14:14
#define csr_AcsmSeqTerm25_BITS   0:0
#define csr_AcsmSeqTerm25_MSB  14
#define csr_AcsmSeqTerm25_LSB  14
#define csr_AcsmSeqTerm25_MASK 0x4000
#define csr_AcsmLp3Ca325_RANGE  15:15
#define csr_AcsmLp3Ca325_BITS   0:0
#define csr_AcsmLp3Ca325_MSB  15
#define csr_AcsmLp3Ca325_LSB  15
#define csr_AcsmLp3Ca325_MASK 0x8000
#define csr_MapCAB9toDfi_RANGE  3:0
#define csr_MapCAB9toDfi_BITS   3:0
#define csr_MapCAB9toDfi_MSB  3
#define csr_MapCAB9toDfi_LSB  0
#define csr_MapCAB9toDfi_MASK 0xf
#define csr_MtestMuxSel_RANGE  5:0
#define csr_MtestMuxSel_BITS   5:0
#define csr_MtestMuxSel_MSB  5
#define csr_MtestMuxSel_LSB  0
#define csr_MtestMuxSel_MASK 0x3f
#define csr_StartVector0b3_RANGE  6:0
#define csr_StartVector0b3_BITS   6:0
#define csr_StartVector0b3_MSB  6
#define csr_StartVector0b3_LSB  0
#define csr_StartVector0b3_MASK 0x7f
#define csr_Seq0BStartVec3_RANGE  6:0
#define csr_Seq0BStartVec3_BITS   6:0
#define csr_Seq0BStartVec3_MSB  6
#define csr_Seq0BStartVec3_LSB  0
#define csr_Seq0BStartVec3_MASK 0x7f
#define csr_SequenceReg0b80s1_RANGE  15:0
#define csr_SequenceReg0b80s1_BITS   15:0
#define csr_SequenceReg0b80s1_MSB  15
#define csr_SequenceReg0b80s1_LSB  0
#define csr_SequenceReg0b80s1_MASK 0xffff
#define csr_AcsmSeq0x26_RANGE  15:0
#define csr_AcsmSeq0x26_BITS   15:0
#define csr_AcsmSeq0x26_MSB  15
#define csr_AcsmSeq0x26_LSB  0
#define csr_AcsmSeq0x26_MASK 0xffff
#define csr_AcsmMclkDly26_RANGE  7:0
#define csr_AcsmMclkDly26_BITS   7:0
#define csr_AcsmMclkDly26_MSB  7
#define csr_AcsmMclkDly26_LSB  0
#define csr_AcsmMclkDly26_MASK 0xff
#define csr_AcsmDdrWe26_RANGE  8:8
#define csr_AcsmDdrWe26_BITS   0:0
#define csr_AcsmDdrWe26_MSB  8
#define csr_AcsmDdrWe26_LSB  8
#define csr_AcsmDdrWe26_MASK 0x100
#define csr_AcsmDdrCas26_RANGE  9:9
#define csr_AcsmDdrCas26_BITS   0:0
#define csr_AcsmDdrCas26_MSB  9
#define csr_AcsmDdrCas26_LSB  9
#define csr_AcsmDdrCas26_MASK 0x200
#define csr_AcsmDdrRas26_RANGE  10:10
#define csr_AcsmDdrRas26_BITS   0:0
#define csr_AcsmDdrRas26_MSB  10
#define csr_AcsmDdrRas26_LSB  10
#define csr_AcsmDdrRas26_MASK 0x400
#define csr_AcsmDdrCkeSet26_RANGE  11:11
#define csr_AcsmDdrCkeSet26_BITS   0:0
#define csr_AcsmDdrCkeSet26_MSB  11
#define csr_AcsmDdrCkeSet26_LSB  11
#define csr_AcsmDdrCkeSet26_MASK 0x800
#define csr_AcsmDdrCkeClr26_RANGE  12:12
#define csr_AcsmDdrCkeClr26_BITS   0:0
#define csr_AcsmDdrCkeClr26_MSB  12
#define csr_AcsmDdrCkeClr26_LSB  12
#define csr_AcsmDdrCkeClr26_MASK 0x1000
#define csr_AcsmSeqGateCmd26_RANGE  13:13
#define csr_AcsmSeqGateCmd26_BITS   0:0
#define csr_AcsmSeqGateCmd26_MSB  13
#define csr_AcsmSeqGateCmd26_LSB  13
#define csr_AcsmSeqGateCmd26_MASK 0x2000
#define csr_AcsmSeqTerm26_RANGE  14:14
#define csr_AcsmSeqTerm26_BITS   0:0
#define csr_AcsmSeqTerm26_MSB  14
#define csr_AcsmSeqTerm26_LSB  14
#define csr_AcsmSeqTerm26_MASK 0x4000
#define csr_AcsmLp3Ca326_RANGE  15:15
#define csr_AcsmLp3Ca326_BITS   0:0
#define csr_AcsmLp3Ca326_MSB  15
#define csr_AcsmLp3Ca326_LSB  15
#define csr_AcsmLp3Ca326_MASK 0x8000
#define csr_MtestPgmInfo_RANGE  0:0
#define csr_MtestPgmInfo_BITS   0:0
#define csr_MtestPgmInfo_MSB  0
#define csr_MtestPgmInfo_LSB  0
#define csr_MtestPgmInfo_MASK 0x1
#define csr_StartVector0b4_RANGE  6:0
#define csr_StartVector0b4_BITS   6:0
#define csr_StartVector0b4_MSB  6
#define csr_StartVector0b4_LSB  0
#define csr_StartVector0b4_MASK 0x7f
#define csr_Seq0BStartVec4_RANGE  6:0
#define csr_Seq0BStartVec4_BITS   6:0
#define csr_Seq0BStartVec4_MSB  6
#define csr_Seq0BStartVec4_LSB  0
#define csr_Seq0BStartVec4_MASK 0x7f
#define csr_SequenceReg0b80s2_RANGE  8:0
#define csr_SequenceReg0b80s2_BITS   8:0
#define csr_SequenceReg0b80s2_MSB  8
#define csr_SequenceReg0b80s2_LSB  0
#define csr_SequenceReg0b80s2_MASK 0x1ff
#define csr_AcsmSeq0x27_RANGE  15:0
#define csr_AcsmSeq0x27_BITS   15:0
#define csr_AcsmSeq0x27_MSB  15
#define csr_AcsmSeq0x27_LSB  0
#define csr_AcsmSeq0x27_MASK 0xffff
#define csr_AcsmMclkDly27_RANGE  7:0
#define csr_AcsmMclkDly27_BITS   7:0
#define csr_AcsmMclkDly27_MSB  7
#define csr_AcsmMclkDly27_LSB  0
#define csr_AcsmMclkDly27_MASK 0xff
#define csr_AcsmDdrWe27_RANGE  8:8
#define csr_AcsmDdrWe27_BITS   0:0
#define csr_AcsmDdrWe27_MSB  8
#define csr_AcsmDdrWe27_LSB  8
#define csr_AcsmDdrWe27_MASK 0x100
#define csr_AcsmDdrCas27_RANGE  9:9
#define csr_AcsmDdrCas27_BITS   0:0
#define csr_AcsmDdrCas27_MSB  9
#define csr_AcsmDdrCas27_LSB  9
#define csr_AcsmDdrCas27_MASK 0x200
#define csr_AcsmDdrRas27_RANGE  10:10
#define csr_AcsmDdrRas27_BITS   0:0
#define csr_AcsmDdrRas27_MSB  10
#define csr_AcsmDdrRas27_LSB  10
#define csr_AcsmDdrRas27_MASK 0x400
#define csr_AcsmDdrCkeSet27_RANGE  11:11
#define csr_AcsmDdrCkeSet27_BITS   0:0
#define csr_AcsmDdrCkeSet27_MSB  11
#define csr_AcsmDdrCkeSet27_LSB  11
#define csr_AcsmDdrCkeSet27_MASK 0x800
#define csr_AcsmDdrCkeClr27_RANGE  12:12
#define csr_AcsmDdrCkeClr27_BITS   0:0
#define csr_AcsmDdrCkeClr27_MSB  12
#define csr_AcsmDdrCkeClr27_LSB  12
#define csr_AcsmDdrCkeClr27_MASK 0x1000
#define csr_AcsmSeqGateCmd27_RANGE  13:13
#define csr_AcsmSeqGateCmd27_BITS   0:0
#define csr_AcsmSeqGateCmd27_MSB  13
#define csr_AcsmSeqGateCmd27_LSB  13
#define csr_AcsmSeqGateCmd27_MASK 0x2000
#define csr_AcsmSeqTerm27_RANGE  14:14
#define csr_AcsmSeqTerm27_BITS   0:0
#define csr_AcsmSeqTerm27_MSB  14
#define csr_AcsmSeqTerm27_LSB  14
#define csr_AcsmSeqTerm27_MASK 0x4000
#define csr_AcsmLp3Ca327_RANGE  15:15
#define csr_AcsmLp3Ca327_BITS   0:0
#define csr_AcsmLp3Ca327_MSB  15
#define csr_AcsmLp3Ca327_LSB  15
#define csr_AcsmLp3Ca327_MASK 0x8000
#define csr_PhyInterruptEnable_RANGE  15:0
#define csr_PhyInterruptEnable_BITS   15:0
#define csr_PhyInterruptEnable_MSB  15
#define csr_PhyInterruptEnable_LSB  0
#define csr_PhyInterruptEnable_MASK 0xffff
#define csr_PhyTrngCmpltEn_RANGE  0:0
#define csr_PhyTrngCmpltEn_BITS   0:0
#define csr_PhyTrngCmpltEn_MSB  0
#define csr_PhyTrngCmpltEn_LSB  0
#define csr_PhyTrngCmpltEn_MASK 0x1
#define csr_PhyInitCmpltEn_RANGE  1:1
#define csr_PhyInitCmpltEn_BITS   0:0
#define csr_PhyInitCmpltEn_MSB  1
#define csr_PhyInitCmpltEn_LSB  1
#define csr_PhyInitCmpltEn_MASK 0x2
#define csr_PhyTrngFailEn_RANGE  2:2
#define csr_PhyTrngFailEn_BITS   0:0
#define csr_PhyTrngFailEn_MSB  2
#define csr_PhyTrngFailEn_LSB  2
#define csr_PhyTrngFailEn_MASK 0x4
#define csr_PhyFWReservedEn_RANGE  7:3
#define csr_PhyFWReservedEn_BITS   4:0
#define csr_PhyFWReservedEn_MSB  7
#define csr_PhyFWReservedEn_LSB  3
#define csr_PhyFWReservedEn_MASK 0xf8
#define csr_PhyVTDriftAlarmEn_RANGE  9:8
#define csr_PhyVTDriftAlarmEn_BITS   1:0
#define csr_PhyVTDriftAlarmEn_MSB  9
#define csr_PhyVTDriftAlarmEn_LSB  8
#define csr_PhyVTDriftAlarmEn_MASK 0x300
#define csr_PhyRxFifoCheckEn_RANGE  10:10
#define csr_PhyRxFifoCheckEn_BITS   0:0
#define csr_PhyRxFifoCheckEn_MSB  10
#define csr_PhyRxFifoCheckEn_LSB  10
#define csr_PhyRxFifoCheckEn_MASK 0x400
#define csr_PhyHWReservedEn_RANGE  15:11
#define csr_PhyHWReservedEn_BITS   4:0
#define csr_PhyHWReservedEn_MSB  15
#define csr_PhyHWReservedEn_LSB  11
#define csr_PhyHWReservedEn_MASK 0xf800
#define csr_StartVector0b5_RANGE  6:0
#define csr_StartVector0b5_BITS   6:0
#define csr_StartVector0b5_MSB  6
#define csr_StartVector0b5_LSB  0
#define csr_StartVector0b5_MASK 0x7f
#define csr_Seq0BStartVec5_RANGE  6:0
#define csr_Seq0BStartVec5_BITS   6:0
#define csr_Seq0BStartVec5_MSB  6
#define csr_Seq0BStartVec5_LSB  0
#define csr_Seq0BStartVec5_MASK 0x7f
#define csr_SequenceReg0b81s0_RANGE  15:0
#define csr_SequenceReg0b81s0_BITS   15:0
#define csr_SequenceReg0b81s0_MSB  15
#define csr_SequenceReg0b81s0_LSB  0
#define csr_SequenceReg0b81s0_MASK 0xffff
#define csr_AcsmSeq0x28_RANGE  15:0
#define csr_AcsmSeq0x28_BITS   15:0
#define csr_AcsmSeq0x28_MSB  15
#define csr_AcsmSeq0x28_LSB  0
#define csr_AcsmSeq0x28_MASK 0xffff
#define csr_AcsmMclkDly28_RANGE  7:0
#define csr_AcsmMclkDly28_BITS   7:0
#define csr_AcsmMclkDly28_MSB  7
#define csr_AcsmMclkDly28_LSB  0
#define csr_AcsmMclkDly28_MASK 0xff
#define csr_AcsmDdrWe28_RANGE  8:8
#define csr_AcsmDdrWe28_BITS   0:0
#define csr_AcsmDdrWe28_MSB  8
#define csr_AcsmDdrWe28_LSB  8
#define csr_AcsmDdrWe28_MASK 0x100
#define csr_AcsmDdrCas28_RANGE  9:9
#define csr_AcsmDdrCas28_BITS   0:0
#define csr_AcsmDdrCas28_MSB  9
#define csr_AcsmDdrCas28_LSB  9
#define csr_AcsmDdrCas28_MASK 0x200
#define csr_AcsmDdrRas28_RANGE  10:10
#define csr_AcsmDdrRas28_BITS   0:0
#define csr_AcsmDdrRas28_MSB  10
#define csr_AcsmDdrRas28_LSB  10
#define csr_AcsmDdrRas28_MASK 0x400
#define csr_AcsmDdrCkeSet28_RANGE  11:11
#define csr_AcsmDdrCkeSet28_BITS   0:0
#define csr_AcsmDdrCkeSet28_MSB  11
#define csr_AcsmDdrCkeSet28_LSB  11
#define csr_AcsmDdrCkeSet28_MASK 0x800
#define csr_AcsmDdrCkeClr28_RANGE  12:12
#define csr_AcsmDdrCkeClr28_BITS   0:0
#define csr_AcsmDdrCkeClr28_MSB  12
#define csr_AcsmDdrCkeClr28_LSB  12
#define csr_AcsmDdrCkeClr28_MASK 0x1000
#define csr_AcsmSeqGateCmd28_RANGE  13:13
#define csr_AcsmSeqGateCmd28_BITS   0:0
#define csr_AcsmSeqGateCmd28_MSB  13
#define csr_AcsmSeqGateCmd28_LSB  13
#define csr_AcsmSeqGateCmd28_MASK 0x2000
#define csr_AcsmSeqTerm28_RANGE  14:14
#define csr_AcsmSeqTerm28_BITS   0:0
#define csr_AcsmSeqTerm28_MSB  14
#define csr_AcsmSeqTerm28_LSB  14
#define csr_AcsmSeqTerm28_MASK 0x4000
#define csr_AcsmLp3Ca328_RANGE  15:15
#define csr_AcsmLp3Ca328_BITS   0:0
#define csr_AcsmLp3Ca328_MSB  15
#define csr_AcsmLp3Ca328_LSB  15
#define csr_AcsmLp3Ca328_MASK 0x8000
#define csr_DynPwrDnUp_RANGE  0:0
#define csr_DynPwrDnUp_BITS   0:0
#define csr_DynPwrDnUp_MSB  0
#define csr_DynPwrDnUp_LSB  0
#define csr_DynPwrDnUp_MASK 0x1
#define csr_DynPowerDown_RANGE  0:0
#define csr_DynPowerDown_BITS   0:0
#define csr_DynPowerDown_MSB  0
#define csr_DynPowerDown_LSB  0
#define csr_DynPowerDown_MASK 0x1
#define csr_PhyInterruptFWControl_RANGE  7:0
#define csr_PhyInterruptFWControl_BITS   7:0
#define csr_PhyInterruptFWControl_MSB  7
#define csr_PhyInterruptFWControl_LSB  0
#define csr_PhyInterruptFWControl_MASK 0xff
#define csr_PhyTrngCmpltFW_RANGE  0:0
#define csr_PhyTrngCmpltFW_BITS   0:0
#define csr_PhyTrngCmpltFW_MSB  0
#define csr_PhyTrngCmpltFW_LSB  0
#define csr_PhyTrngCmpltFW_MASK 0x1
#define csr_PhyInitCmpltFW_RANGE  1:1
#define csr_PhyInitCmpltFW_BITS   0:0
#define csr_PhyInitCmpltFW_MSB  1
#define csr_PhyInitCmpltFW_LSB  1
#define csr_PhyInitCmpltFW_MASK 0x2
#define csr_PhyTrngFailFW_RANGE  2:2
#define csr_PhyTrngFailFW_BITS   0:0
#define csr_PhyTrngFailFW_MSB  2
#define csr_PhyTrngFailFW_LSB  2
#define csr_PhyTrngFailFW_MASK 0x4
#define csr_PhyFWReservedFW_RANGE  7:3
#define csr_PhyFWReservedFW_BITS   4:0
#define csr_PhyFWReservedFW_MSB  7
#define csr_PhyFWReservedFW_LSB  3
#define csr_PhyFWReservedFW_MASK 0xf8
#define csr_StartVector0b6_RANGE  6:0
#define csr_StartVector0b6_BITS   6:0
#define csr_StartVector0b6_MSB  6
#define csr_StartVector0b6_LSB  0
#define csr_StartVector0b6_MASK 0x7f
#define csr_Seq0BStartVec6_RANGE  6:0
#define csr_Seq0BStartVec6_BITS   6:0
#define csr_Seq0BStartVec6_MSB  6
#define csr_Seq0BStartVec6_LSB  0
#define csr_Seq0BStartVec6_MASK 0x7f
#define csr_SequenceReg0b81s1_RANGE  15:0
#define csr_SequenceReg0b81s1_BITS   15:0
#define csr_SequenceReg0b81s1_MSB  15
#define csr_SequenceReg0b81s1_LSB  0
#define csr_SequenceReg0b81s1_MASK 0xffff
#define csr_AcsmSeq0x29_RANGE  15:0
#define csr_AcsmSeq0x29_BITS   15:0
#define csr_AcsmSeq0x29_MSB  15
#define csr_AcsmSeq0x29_LSB  0
#define csr_AcsmSeq0x29_MASK 0xffff
#define csr_AcsmMclkDly29_RANGE  7:0
#define csr_AcsmMclkDly29_BITS   7:0
#define csr_AcsmMclkDly29_MSB  7
#define csr_AcsmMclkDly29_LSB  0
#define csr_AcsmMclkDly29_MASK 0xff
#define csr_AcsmDdrWe29_RANGE  8:8
#define csr_AcsmDdrWe29_BITS   0:0
#define csr_AcsmDdrWe29_MSB  8
#define csr_AcsmDdrWe29_LSB  8
#define csr_AcsmDdrWe29_MASK 0x100
#define csr_AcsmDdrCas29_RANGE  9:9
#define csr_AcsmDdrCas29_BITS   0:0
#define csr_AcsmDdrCas29_MSB  9
#define csr_AcsmDdrCas29_LSB  9
#define csr_AcsmDdrCas29_MASK 0x200
#define csr_AcsmDdrRas29_RANGE  10:10
#define csr_AcsmDdrRas29_BITS   0:0
#define csr_AcsmDdrRas29_MSB  10
#define csr_AcsmDdrRas29_LSB  10
#define csr_AcsmDdrRas29_MASK 0x400
#define csr_AcsmDdrCkeSet29_RANGE  11:11
#define csr_AcsmDdrCkeSet29_BITS   0:0
#define csr_AcsmDdrCkeSet29_MSB  11
#define csr_AcsmDdrCkeSet29_LSB  11
#define csr_AcsmDdrCkeSet29_MASK 0x800
#define csr_AcsmDdrCkeClr29_RANGE  12:12
#define csr_AcsmDdrCkeClr29_BITS   0:0
#define csr_AcsmDdrCkeClr29_MSB  12
#define csr_AcsmDdrCkeClr29_LSB  12
#define csr_AcsmDdrCkeClr29_MASK 0x1000
#define csr_AcsmSeqGateCmd29_RANGE  13:13
#define csr_AcsmSeqGateCmd29_BITS   0:0
#define csr_AcsmSeqGateCmd29_MSB  13
#define csr_AcsmSeqGateCmd29_LSB  13
#define csr_AcsmSeqGateCmd29_MASK 0x2000
#define csr_AcsmSeqTerm29_RANGE  14:14
#define csr_AcsmSeqTerm29_BITS   0:0
#define csr_AcsmSeqTerm29_MSB  14
#define csr_AcsmSeqTerm29_LSB  14
#define csr_AcsmSeqTerm29_MASK 0x4000
#define csr_AcsmLp3Ca329_RANGE  15:15
#define csr_AcsmLp3Ca329_BITS   0:0
#define csr_AcsmLp3Ca329_MSB  15
#define csr_AcsmLp3Ca329_LSB  15
#define csr_AcsmLp3Ca329_MASK 0x8000
#define csr_PMIEnable_RANGE  0:0
#define csr_PMIEnable_BITS   0:0
#define csr_PMIEnable_MSB  0
#define csr_PMIEnable_LSB  0
#define csr_PMIEnable_MASK 0x1
#define csr_PhyInterruptMask_RANGE  15:0
#define csr_PhyInterruptMask_BITS   15:0
#define csr_PhyInterruptMask_MSB  15
#define csr_PhyInterruptMask_LSB  0
#define csr_PhyInterruptMask_MASK 0xffff
#define csr_PhyTrngCmpltMsk_RANGE  0:0
#define csr_PhyTrngCmpltMsk_BITS   0:0
#define csr_PhyTrngCmpltMsk_MSB  0
#define csr_PhyTrngCmpltMsk_LSB  0
#define csr_PhyTrngCmpltMsk_MASK 0x1
#define csr_PhyInitCmpltMsk_RANGE  1:1
#define csr_PhyInitCmpltMsk_BITS   0:0
#define csr_PhyInitCmpltMsk_MSB  1
#define csr_PhyInitCmpltMsk_LSB  1
#define csr_PhyInitCmpltMsk_MASK 0x2
#define csr_PhyTrngFailMsk_RANGE  2:2
#define csr_PhyTrngFailMsk_BITS   0:0
#define csr_PhyTrngFailMsk_MSB  2
#define csr_PhyTrngFailMsk_LSB  2
#define csr_PhyTrngFailMsk_MASK 0x4
#define csr_PhyFWReservedMsk_RANGE  7:3
#define csr_PhyFWReservedMsk_BITS   4:0
#define csr_PhyFWReservedMsk_MSB  7
#define csr_PhyFWReservedMsk_LSB  3
#define csr_PhyFWReservedMsk_MASK 0xf8
#define csr_PhyVTDriftAlarmMsk_RANGE  9:8
#define csr_PhyVTDriftAlarmMsk_BITS   1:0
#define csr_PhyVTDriftAlarmMsk_MSB  9
#define csr_PhyVTDriftAlarmMsk_LSB  8
#define csr_PhyVTDriftAlarmMsk_MASK 0x300
#define csr_PhyRxFifoCheckMsk_RANGE  10:10
#define csr_PhyRxFifoCheckMsk_BITS   0:0
#define csr_PhyRxFifoCheckMsk_MSB  10
#define csr_PhyRxFifoCheckMsk_LSB  10
#define csr_PhyRxFifoCheckMsk_MASK 0x400
#define csr_PhyHWReservedMsk_RANGE  15:11
#define csr_PhyHWReservedMsk_BITS   4:0
#define csr_PhyHWReservedMsk_MSB  15
#define csr_PhyHWReservedMsk_LSB  11
#define csr_PhyHWReservedMsk_MASK 0xf800
#define csr_StartVector0b7_RANGE  6:0
#define csr_StartVector0b7_BITS   6:0
#define csr_StartVector0b7_MSB  6
#define csr_StartVector0b7_LSB  0
#define csr_StartVector0b7_MASK 0x7f
#define csr_Seq0BStartVec7_RANGE  6:0
#define csr_Seq0BStartVec7_BITS   6:0
#define csr_Seq0BStartVec7_MSB  6
#define csr_Seq0BStartVec7_LSB  0
#define csr_Seq0BStartVec7_MASK 0x7f
#define csr_SequenceReg0b81s2_RANGE  8:0
#define csr_SequenceReg0b81s2_BITS   8:0
#define csr_SequenceReg0b81s2_MSB  8
#define csr_SequenceReg0b81s2_LSB  0
#define csr_SequenceReg0b81s2_MASK 0x1ff
#define csr_AcsmSeq0x30_RANGE  15:0
#define csr_AcsmSeq0x30_BITS   15:0
#define csr_AcsmSeq0x30_MSB  15
#define csr_AcsmSeq0x30_LSB  0
#define csr_AcsmSeq0x30_MASK 0xffff
#define csr_AcsmMclkDly30_RANGE  7:0
#define csr_AcsmMclkDly30_BITS   7:0
#define csr_AcsmMclkDly30_MSB  7
#define csr_AcsmMclkDly30_LSB  0
#define csr_AcsmMclkDly30_MASK 0xff
#define csr_AcsmDdrWe30_RANGE  8:8
#define csr_AcsmDdrWe30_BITS   0:0
#define csr_AcsmDdrWe30_MSB  8
#define csr_AcsmDdrWe30_LSB  8
#define csr_AcsmDdrWe30_MASK 0x100
#define csr_AcsmDdrCas30_RANGE  9:9
#define csr_AcsmDdrCas30_BITS   0:0
#define csr_AcsmDdrCas30_MSB  9
#define csr_AcsmDdrCas30_LSB  9
#define csr_AcsmDdrCas30_MASK 0x200
#define csr_AcsmDdrRas30_RANGE  10:10
#define csr_AcsmDdrRas30_BITS   0:0
#define csr_AcsmDdrRas30_MSB  10
#define csr_AcsmDdrRas30_LSB  10
#define csr_AcsmDdrRas30_MASK 0x400
#define csr_AcsmDdrCkeSet30_RANGE  11:11
#define csr_AcsmDdrCkeSet30_BITS   0:0
#define csr_AcsmDdrCkeSet30_MSB  11
#define csr_AcsmDdrCkeSet30_LSB  11
#define csr_AcsmDdrCkeSet30_MASK 0x800
#define csr_AcsmDdrCkeClr30_RANGE  12:12
#define csr_AcsmDdrCkeClr30_BITS   0:0
#define csr_AcsmDdrCkeClr30_MSB  12
#define csr_AcsmDdrCkeClr30_LSB  12
#define csr_AcsmDdrCkeClr30_MASK 0x1000
#define csr_AcsmSeqGateCmd30_RANGE  13:13
#define csr_AcsmSeqGateCmd30_BITS   0:0
#define csr_AcsmSeqGateCmd30_MSB  13
#define csr_AcsmSeqGateCmd30_LSB  13
#define csr_AcsmSeqGateCmd30_MASK 0x2000
#define csr_AcsmSeqTerm30_RANGE  14:14
#define csr_AcsmSeqTerm30_BITS   0:0
#define csr_AcsmSeqTerm30_MSB  14
#define csr_AcsmSeqTerm30_LSB  14
#define csr_AcsmSeqTerm30_MASK 0x4000
#define csr_AcsmLp3Ca330_RANGE  15:15
#define csr_AcsmLp3Ca330_BITS   0:0
#define csr_AcsmLp3Ca330_MSB  15
#define csr_AcsmLp3Ca330_LSB  15
#define csr_AcsmLp3Ca330_MASK 0x8000
#define csr_PhyTID_RANGE  15:0
#define csr_PhyTID_BITS   15:0
#define csr_PhyTID_MSB  15
#define csr_PhyTID_LSB  0
#define csr_PhyTID_MASK 0xffff
#define csr_PhyInterruptClear_RANGE  15:0
#define csr_PhyInterruptClear_BITS   15:0
#define csr_PhyInterruptClear_MSB  15
#define csr_PhyInterruptClear_LSB  0
#define csr_PhyInterruptClear_MASK 0xffff
#define csr_PhyTrngCmpltClr_RANGE  0:0
#define csr_PhyTrngCmpltClr_BITS   0:0
#define csr_PhyTrngCmpltClr_MSB  0
#define csr_PhyTrngCmpltClr_LSB  0
#define csr_PhyTrngCmpltClr_MASK 0x1
#define csr_PhyInitCmpltClr_RANGE  1:1
#define csr_PhyInitCmpltClr_BITS   0:0
#define csr_PhyInitCmpltClr_MSB  1
#define csr_PhyInitCmpltClr_LSB  1
#define csr_PhyInitCmpltClr_MASK 0x2
#define csr_PhyTrngFailClr_RANGE  2:2
#define csr_PhyTrngFailClr_BITS   0:0
#define csr_PhyTrngFailClr_MSB  2
#define csr_PhyTrngFailClr_LSB  2
#define csr_PhyTrngFailClr_MASK 0x4
#define csr_PhyFWReservedClr_RANGE  7:3
#define csr_PhyFWReservedClr_BITS   4:0
#define csr_PhyFWReservedClr_MSB  7
#define csr_PhyFWReservedClr_LSB  3
#define csr_PhyFWReservedClr_MASK 0xf8
#define csr_PhyVTDriftAlarmClr_RANGE  9:8
#define csr_PhyVTDriftAlarmClr_BITS   1:0
#define csr_PhyVTDriftAlarmClr_MSB  9
#define csr_PhyVTDriftAlarmClr_LSB  8
#define csr_PhyVTDriftAlarmClr_MASK 0x300
#define csr_PhyRxFifoCheckClr_RANGE  10:10
#define csr_PhyRxFifoCheckClr_BITS   0:0
#define csr_PhyRxFifoCheckClr_MSB  10
#define csr_PhyRxFifoCheckClr_LSB  10
#define csr_PhyRxFifoCheckClr_MASK 0x400
#define csr_PhyHWReservedClr_RANGE  15:11
#define csr_PhyHWReservedClr_BITS   4:0
#define csr_PhyHWReservedClr_MSB  15
#define csr_PhyHWReservedClr_LSB  11
#define csr_PhyHWReservedClr_MASK 0xf800
#define csr_DtsmTrainModeCtrl_RANGE  3:0
#define csr_DtsmTrainModeCtrl_BITS   3:0
#define csr_DtsmTrainModeCtrl_MSB  3
#define csr_DtsmTrainModeCtrl_LSB  0
#define csr_DtsmTrainModeCtrl_MASK 0xf
#define csr_DtsmSoeLaneMode_RANGE  1:0
#define csr_DtsmSoeLaneMode_BITS   1:0
#define csr_DtsmSoeLaneMode_MSB  1
#define csr_DtsmSoeLaneMode_LSB  0
#define csr_DtsmSoeLaneMode_MASK 0x3
#define csr_DtsmByteErrAndMode_RANGE  2:2
#define csr_DtsmByteErrAndMode_BITS   0:0
#define csr_DtsmByteErrAndMode_MSB  2
#define csr_DtsmByteErrAndMode_LSB  2
#define csr_DtsmByteErrAndMode_MASK 0x4
#define csr_DtsmNibErrMode_RANGE  3:3
#define csr_DtsmNibErrMode_BITS   0:0
#define csr_DtsmNibErrMode_MSB  3
#define csr_DtsmNibErrMode_LSB  3
#define csr_DtsmNibErrMode_MASK 0x8
#define csr_StartVector0b8_RANGE  6:0
#define csr_StartVector0b8_BITS   6:0
#define csr_StartVector0b8_MSB  6
#define csr_StartVector0b8_LSB  0
#define csr_StartVector0b8_MASK 0x7f
#define csr_Seq0BStartVec8_RANGE  6:0
#define csr_Seq0BStartVec8_BITS   6:0
#define csr_Seq0BStartVec8_MSB  6
#define csr_Seq0BStartVec8_LSB  0
#define csr_Seq0BStartVec8_MASK 0x7f
#define csr_SequenceReg0b82s0_RANGE  15:0
#define csr_SequenceReg0b82s0_BITS   15:0
#define csr_SequenceReg0b82s0_MSB  15
#define csr_SequenceReg0b82s0_LSB  0
#define csr_SequenceReg0b82s0_MASK 0xffff
#define csr_AcsmSeq0x31_RANGE  15:0
#define csr_AcsmSeq0x31_BITS   15:0
#define csr_AcsmSeq0x31_MSB  15
#define csr_AcsmSeq0x31_LSB  0
#define csr_AcsmSeq0x31_MASK 0xffff
#define csr_AcsmMclkDly31_RANGE  7:0
#define csr_AcsmMclkDly31_BITS   7:0
#define csr_AcsmMclkDly31_MSB  7
#define csr_AcsmMclkDly31_LSB  0
#define csr_AcsmMclkDly31_MASK 0xff
#define csr_AcsmDdrWe31_RANGE  8:8
#define csr_AcsmDdrWe31_BITS   0:0
#define csr_AcsmDdrWe31_MSB  8
#define csr_AcsmDdrWe31_LSB  8
#define csr_AcsmDdrWe31_MASK 0x100
#define csr_AcsmDdrCas31_RANGE  9:9
#define csr_AcsmDdrCas31_BITS   0:0
#define csr_AcsmDdrCas31_MSB  9
#define csr_AcsmDdrCas31_LSB  9
#define csr_AcsmDdrCas31_MASK 0x200
#define csr_AcsmDdrRas31_RANGE  10:10
#define csr_AcsmDdrRas31_BITS   0:0
#define csr_AcsmDdrRas31_MSB  10
#define csr_AcsmDdrRas31_LSB  10
#define csr_AcsmDdrRas31_MASK 0x400
#define csr_AcsmDdrCkeSet31_RANGE  11:11
#define csr_AcsmDdrCkeSet31_BITS   0:0
#define csr_AcsmDdrCkeSet31_MSB  11
#define csr_AcsmDdrCkeSet31_LSB  11
#define csr_AcsmDdrCkeSet31_MASK 0x800
#define csr_AcsmDdrCkeClr31_RANGE  12:12
#define csr_AcsmDdrCkeClr31_BITS   0:0
#define csr_AcsmDdrCkeClr31_MSB  12
#define csr_AcsmDdrCkeClr31_LSB  12
#define csr_AcsmDdrCkeClr31_MASK 0x1000
#define csr_AcsmSeqGateCmd31_RANGE  13:13
#define csr_AcsmSeqGateCmd31_BITS   0:0
#define csr_AcsmSeqGateCmd31_MSB  13
#define csr_AcsmSeqGateCmd31_LSB  13
#define csr_AcsmSeqGateCmd31_MASK 0x2000
#define csr_AcsmSeqTerm31_RANGE  14:14
#define csr_AcsmSeqTerm31_BITS   0:0
#define csr_AcsmSeqTerm31_MSB  14
#define csr_AcsmSeqTerm31_LSB  14
#define csr_AcsmSeqTerm31_MASK 0x4000
#define csr_AcsmLp3Ca331_RANGE  15:15
#define csr_AcsmLp3Ca331_BITS   0:0
#define csr_AcsmLp3Ca331_MSB  15
#define csr_AcsmLp3Ca331_LSB  15
#define csr_AcsmLp3Ca331_MASK 0x8000
#define csr_PhyInterruptStatus_RANGE  15:0
#define csr_PhyInterruptStatus_BITS   15:0
#define csr_PhyInterruptStatus_MSB  15
#define csr_PhyInterruptStatus_LSB  0
#define csr_PhyInterruptStatus_MASK 0xffff
#define csr_PhyTrngCmplt_RANGE  0:0
#define csr_PhyTrngCmplt_BITS   0:0
#define csr_PhyTrngCmplt_MSB  0
#define csr_PhyTrngCmplt_LSB  0
#define csr_PhyTrngCmplt_MASK 0x1
#define csr_PhyInitCmplt_RANGE  1:1
#define csr_PhyInitCmplt_BITS   0:0
#define csr_PhyInitCmplt_MSB  1
#define csr_PhyInitCmplt_LSB  1
#define csr_PhyInitCmplt_MASK 0x2
#define csr_PhyTrngFail_RANGE  2:2
#define csr_PhyTrngFail_BITS   0:0
#define csr_PhyTrngFail_MSB  2
#define csr_PhyTrngFail_LSB  2
#define csr_PhyTrngFail_MASK 0x4
#define csr_PhyFWReserved_RANGE  7:3
#define csr_PhyFWReserved_BITS   4:0
#define csr_PhyFWReserved_MSB  7
#define csr_PhyFWReserved_LSB  3
#define csr_PhyFWReserved_MASK 0xf8
#define csr_VTDriftAlarm_RANGE  9:8
#define csr_VTDriftAlarm_BITS   1:0
#define csr_VTDriftAlarm_MSB  9
#define csr_VTDriftAlarm_LSB  8
#define csr_VTDriftAlarm_MASK 0x300
#define csr_PhyRxFifoCheck_RANGE  10:10
#define csr_PhyRxFifoCheck_BITS   0:0
#define csr_PhyRxFifoCheck_MSB  10
#define csr_PhyRxFifoCheck_LSB  10
#define csr_PhyRxFifoCheck_MASK 0x400
#define csr_PhyHWReserved_RANGE  15:11
#define csr_PhyHWReserved_BITS   4:0
#define csr_PhyHWReserved_MSB  15
#define csr_PhyHWReserved_LSB  11
#define csr_PhyHWReserved_MASK 0xf800
#define csr_HwtMRL_RANGE  4:0
#define csr_HwtMRL_BITS   4:0
#define csr_HwtMRL_MSB  4
#define csr_HwtMRL_LSB  0
#define csr_HwtMRL_MASK 0x1f
#define csr_DFIMRL_RANGE  4:0
#define csr_DFIMRL_BITS   4:0
#define csr_DFIMRL_MSB  4
#define csr_DFIMRL_LSB  0
#define csr_DFIMRL_MASK 0x1f
#define csr_StartVector0b9_RANGE  6:0
#define csr_StartVector0b9_BITS   6:0
#define csr_StartVector0b9_MSB  6
#define csr_StartVector0b9_LSB  0
#define csr_StartVector0b9_MASK 0x7f
#define csr_Seq0BStartVec9_RANGE  6:0
#define csr_Seq0BStartVec9_BITS   6:0
#define csr_Seq0BStartVec9_MSB  6
#define csr_Seq0BStartVec9_LSB  0
#define csr_Seq0BStartVec9_MASK 0x7f
#define csr_SequenceReg0b82s1_RANGE  15:0
#define csr_SequenceReg0b82s1_BITS   15:0
#define csr_SequenceReg0b82s1_MSB  15
#define csr_SequenceReg0b82s1_LSB  0
#define csr_SequenceReg0b82s1_MASK 0xffff
#define csr_AcsmSeq1x0_RANGE  15:0
#define csr_AcsmSeq1x0_BITS   15:0
#define csr_AcsmSeq1x0_MSB  15
#define csr_AcsmSeq1x0_LSB  0
#define csr_AcsmSeq1x0_MASK 0xffff
#define csr_AcsmDdrCs0_RANGE  7:0
#define csr_AcsmDdrCs0_BITS   7:0
#define csr_AcsmDdrCs0_MSB  7
#define csr_AcsmDdrCs0_LSB  0
#define csr_AcsmDdrCs0_MASK 0xff
#define csr_AcsmSaveGen0_RANGE  8:8
#define csr_AcsmSaveGen0_BITS   0:0
#define csr_AcsmSaveGen0_MSB  8
#define csr_AcsmSaveGen0_LSB  8
#define csr_AcsmSaveGen0_MASK 0x100
#define csr_AcsmLoadChk0_RANGE  9:9
#define csr_AcsmLoadChk0_BITS   0:0
#define csr_AcsmLoadChk0_MSB  9
#define csr_AcsmLoadChk0_LSB  9
#define csr_AcsmLoadChk0_MASK 0x200
#define csr_AcsmNoRxEnb0_RANGE  10:10
#define csr_AcsmNoRxEnb0_BITS   0:0
#define csr_AcsmNoRxEnb0_MSB  10
#define csr_AcsmNoRxEnb0_LSB  10
#define csr_AcsmNoRxEnb0_MASK 0x400
#define csr_AcsmNoRxVal0_RANGE  11:11
#define csr_AcsmNoRxVal0_BITS   0:0
#define csr_AcsmNoRxVal0_MSB  11
#define csr_AcsmNoRxVal0_LSB  11
#define csr_AcsmNoRxVal0_MASK 0x800
#define csr_AcsmDdrBnk0_RANGE  15:12
#define csr_AcsmDdrBnk0_BITS   3:0
#define csr_AcsmDdrBnk0_MSB  15
#define csr_AcsmDdrBnk0_LSB  12
#define csr_AcsmDdrBnk0_MASK 0xf000
#define csr_HwtSwizzleHwtAddress0_RANGE  4:0
#define csr_HwtSwizzleHwtAddress0_BITS   4:0
#define csr_HwtSwizzleHwtAddress0_MSB  4
#define csr_HwtSwizzleHwtAddress0_LSB  0
#define csr_HwtSwizzleHwtAddress0_MASK 0x1f
#define csr_DFIPHYUPD_RANGE  15:0
#define csr_DFIPHYUPD_BITS   15:0
#define csr_DFIPHYUPD_MSB  15
#define csr_DFIPHYUPD_LSB  0
#define csr_DFIPHYUPD_MASK 0xffff
#define csr_DFIPHYUPDCNT_RANGE  3:0
#define csr_DFIPHYUPDCNT_BITS   3:0
#define csr_DFIPHYUPDCNT_MSB  3
#define csr_DFIPHYUPDCNT_LSB  0
#define csr_DFIPHYUPDCNT_MASK 0xf
#define csr_DFIPHYUPDRESP_RANGE  6:4
#define csr_DFIPHYUPDRESP_BITS   2:0
#define csr_DFIPHYUPDRESP_MSB  6
#define csr_DFIPHYUPDRESP_LSB  4
#define csr_DFIPHYUPDRESP_MASK 0x70
#define csr_DFIPHYUPDMODE_RANGE  7:7
#define csr_DFIPHYUPDMODE_BITS   0:0
#define csr_DFIPHYUPDMODE_MSB  7
#define csr_DFIPHYUPDMODE_LSB  7
#define csr_DFIPHYUPDMODE_MASK 0x80
#define csr_DFIPHYUPDTHRESHOLD_RANGE  11:8
#define csr_DFIPHYUPDTHRESHOLD_BITS   3:0
#define csr_DFIPHYUPDTHRESHOLD_MSB  11
#define csr_DFIPHYUPDTHRESHOLD_LSB  8
#define csr_DFIPHYUPDTHRESHOLD_MASK 0xf00
#define csr_DFIPHYUPDINTTHRESHOLD_RANGE  15:12
#define csr_DFIPHYUPDINTTHRESHOLD_BITS   3:0
#define csr_DFIPHYUPDINTTHRESHOLD_MSB  15
#define csr_DFIPHYUPDINTTHRESHOLD_LSB  12
#define csr_DFIPHYUPDINTTHRESHOLD_MASK 0xf000
#define csr_StartVector0b10_RANGE  6:0
#define csr_StartVector0b10_BITS   6:0
#define csr_StartVector0b10_MSB  6
#define csr_StartVector0b10_LSB  0
#define csr_StartVector0b10_MASK 0x7f
#define csr_Seq0BStartVec10_RANGE  6:0
#define csr_Seq0BStartVec10_BITS   6:0
#define csr_Seq0BStartVec10_MSB  6
#define csr_Seq0BStartVec10_LSB  0
#define csr_Seq0BStartVec10_MASK 0x7f
#define csr_SequenceReg0b82s2_RANGE  8:0
#define csr_SequenceReg0b82s2_BITS   8:0
#define csr_SequenceReg0b82s2_MSB  8
#define csr_SequenceReg0b82s2_LSB  0
#define csr_SequenceReg0b82s2_MASK 0x1ff
#define csr_AcsmSeq1x1_RANGE  15:0
#define csr_AcsmSeq1x1_BITS   15:0
#define csr_AcsmSeq1x1_MSB  15
#define csr_AcsmSeq1x1_LSB  0
#define csr_AcsmSeq1x1_MASK 0xffff
#define csr_AcsmDdrCs1_RANGE  7:0
#define csr_AcsmDdrCs1_BITS   7:0
#define csr_AcsmDdrCs1_MSB  7
#define csr_AcsmDdrCs1_LSB  0
#define csr_AcsmDdrCs1_MASK 0xff
#define csr_AcsmSaveGen1_RANGE  8:8
#define csr_AcsmSaveGen1_BITS   0:0
#define csr_AcsmSaveGen1_MSB  8
#define csr_AcsmSaveGen1_LSB  8
#define csr_AcsmSaveGen1_MASK 0x100
#define csr_AcsmLoadChk1_RANGE  9:9
#define csr_AcsmLoadChk1_BITS   0:0
#define csr_AcsmLoadChk1_MSB  9
#define csr_AcsmLoadChk1_LSB  9
#define csr_AcsmLoadChk1_MASK 0x200
#define csr_AcsmNoRxEnb1_RANGE  10:10
#define csr_AcsmNoRxEnb1_BITS   0:0
#define csr_AcsmNoRxEnb1_MSB  10
#define csr_AcsmNoRxEnb1_LSB  10
#define csr_AcsmNoRxEnb1_MASK 0x400
#define csr_AcsmNoRxVal1_RANGE  11:11
#define csr_AcsmNoRxVal1_BITS   0:0
#define csr_AcsmNoRxVal1_MSB  11
#define csr_AcsmNoRxVal1_LSB  11
#define csr_AcsmNoRxVal1_MASK 0x800
#define csr_AcsmDdrBnk1_RANGE  15:12
#define csr_AcsmDdrBnk1_BITS   3:0
#define csr_AcsmDdrBnk1_MSB  15
#define csr_AcsmDdrBnk1_LSB  12
#define csr_AcsmDdrBnk1_MASK 0xf000
#define csr_HwtSwizzleHwtAddress1_RANGE  4:0
#define csr_HwtSwizzleHwtAddress1_BITS   4:0
#define csr_HwtSwizzleHwtAddress1_MSB  4
#define csr_HwtSwizzleHwtAddress1_LSB  0
#define csr_HwtSwizzleHwtAddress1_MASK 0x1f
#define csr_PdaMrsWriteMode_RANGE  0:0
#define csr_PdaMrsWriteMode_BITS   0:0
#define csr_PdaMrsWriteMode_MSB  0
#define csr_PdaMrsWriteMode_LSB  0
#define csr_PdaMrsWriteMode_MASK 0x1
#define csr_StartVector0b11_RANGE  6:0
#define csr_StartVector0b11_BITS   6:0
#define csr_StartVector0b11_MSB  6
#define csr_StartVector0b11_LSB  0
#define csr_StartVector0b11_MASK 0x7f
#define csr_Seq0BStartVec11_RANGE  6:0
#define csr_Seq0BStartVec11_BITS   6:0
#define csr_Seq0BStartVec11_MSB  6
#define csr_Seq0BStartVec11_LSB  0
#define csr_Seq0BStartVec11_MASK 0x7f
#define csr_SequenceReg0b83s0_RANGE  15:0
#define csr_SequenceReg0b83s0_BITS   15:0
#define csr_SequenceReg0b83s0_MSB  15
#define csr_SequenceReg0b83s0_LSB  0
#define csr_SequenceReg0b83s0_MASK 0xffff
#define csr_AcsmSeq1x2_RANGE  15:0
#define csr_AcsmSeq1x2_BITS   15:0
#define csr_AcsmSeq1x2_MSB  15
#define csr_AcsmSeq1x2_LSB  0
#define csr_AcsmSeq1x2_MASK 0xffff
#define csr_AcsmDdrCs2_RANGE  7:0
#define csr_AcsmDdrCs2_BITS   7:0
#define csr_AcsmDdrCs2_MSB  7
#define csr_AcsmDdrCs2_LSB  0
#define csr_AcsmDdrCs2_MASK 0xff
#define csr_AcsmSaveGen2_RANGE  8:8
#define csr_AcsmSaveGen2_BITS   0:0
#define csr_AcsmSaveGen2_MSB  8
#define csr_AcsmSaveGen2_LSB  8
#define csr_AcsmSaveGen2_MASK 0x100
#define csr_AcsmLoadChk2_RANGE  9:9
#define csr_AcsmLoadChk2_BITS   0:0
#define csr_AcsmLoadChk2_MSB  9
#define csr_AcsmLoadChk2_LSB  9
#define csr_AcsmLoadChk2_MASK 0x200
#define csr_AcsmNoRxEnb2_RANGE  10:10
#define csr_AcsmNoRxEnb2_BITS   0:0
#define csr_AcsmNoRxEnb2_MSB  10
#define csr_AcsmNoRxEnb2_LSB  10
#define csr_AcsmNoRxEnb2_MASK 0x400
#define csr_AcsmNoRxVal2_RANGE  11:11
#define csr_AcsmNoRxVal2_BITS   0:0
#define csr_AcsmNoRxVal2_MSB  11
#define csr_AcsmNoRxVal2_LSB  11
#define csr_AcsmNoRxVal2_MASK 0x800
#define csr_AcsmDdrBnk2_RANGE  15:12
#define csr_AcsmDdrBnk2_BITS   3:0
#define csr_AcsmDdrBnk2_MSB  15
#define csr_AcsmDdrBnk2_LSB  12
#define csr_AcsmDdrBnk2_MASK 0xf000
#define csr_HwtSwizzleHwtAddress2_RANGE  4:0
#define csr_HwtSwizzleHwtAddress2_BITS   4:0
#define csr_HwtSwizzleHwtAddress2_MSB  4
#define csr_HwtSwizzleHwtAddress2_LSB  0
#define csr_HwtSwizzleHwtAddress2_MASK 0x1f
#define csr_DFIGEARDOWNCTL_RANGE  1:0
#define csr_DFIGEARDOWNCTL_BITS   1:0
#define csr_DFIGEARDOWNCTL_MSB  1
#define csr_DFIGEARDOWNCTL_LSB  0
#define csr_DFIGEARDOWNCTL_MASK 0x3
#define csr_StartVector0b12_RANGE  6:0
#define csr_StartVector0b12_BITS   6:0
#define csr_StartVector0b12_MSB  6
#define csr_StartVector0b12_LSB  0
#define csr_StartVector0b12_MASK 0x7f
#define csr_Seq0BStartVec12_RANGE  6:0
#define csr_Seq0BStartVec12_BITS   6:0
#define csr_Seq0BStartVec12_MSB  6
#define csr_Seq0BStartVec12_LSB  0
#define csr_Seq0BStartVec12_MASK 0x7f
#define csr_SequenceReg0b83s1_RANGE  15:0
#define csr_SequenceReg0b83s1_BITS   15:0
#define csr_SequenceReg0b83s1_MSB  15
#define csr_SequenceReg0b83s1_LSB  0
#define csr_SequenceReg0b83s1_MASK 0xffff
#define csr_AcsmSeq1x3_RANGE  15:0
#define csr_AcsmSeq1x3_BITS   15:0
#define csr_AcsmSeq1x3_MSB  15
#define csr_AcsmSeq1x3_LSB  0
#define csr_AcsmSeq1x3_MASK 0xffff
#define csr_AcsmDdrCs3_RANGE  7:0
#define csr_AcsmDdrCs3_BITS   7:0
#define csr_AcsmDdrCs3_MSB  7
#define csr_AcsmDdrCs3_LSB  0
#define csr_AcsmDdrCs3_MASK 0xff
#define csr_AcsmSaveGen3_RANGE  8:8
#define csr_AcsmSaveGen3_BITS   0:0
#define csr_AcsmSaveGen3_MSB  8
#define csr_AcsmSaveGen3_LSB  8
#define csr_AcsmSaveGen3_MASK 0x100
#define csr_AcsmLoadChk3_RANGE  9:9
#define csr_AcsmLoadChk3_BITS   0:0
#define csr_AcsmLoadChk3_MSB  9
#define csr_AcsmLoadChk3_LSB  9
#define csr_AcsmLoadChk3_MASK 0x200
#define csr_AcsmNoRxEnb3_RANGE  10:10
#define csr_AcsmNoRxEnb3_BITS   0:0
#define csr_AcsmNoRxEnb3_MSB  10
#define csr_AcsmNoRxEnb3_LSB  10
#define csr_AcsmNoRxEnb3_MASK 0x400
#define csr_AcsmNoRxVal3_RANGE  11:11
#define csr_AcsmNoRxVal3_BITS   0:0
#define csr_AcsmNoRxVal3_MSB  11
#define csr_AcsmNoRxVal3_LSB  11
#define csr_AcsmNoRxVal3_MASK 0x800
#define csr_AcsmDdrBnk3_RANGE  15:12
#define csr_AcsmDdrBnk3_BITS   3:0
#define csr_AcsmDdrBnk3_MSB  15
#define csr_AcsmDdrBnk3_LSB  12
#define csr_AcsmDdrBnk3_MASK 0xf000
#define csr_HwtSwizzleHwtAddress3_RANGE  4:0
#define csr_HwtSwizzleHwtAddress3_BITS   4:0
#define csr_HwtSwizzleHwtAddress3_MSB  4
#define csr_HwtSwizzleHwtAddress3_LSB  0
#define csr_HwtSwizzleHwtAddress3_MASK 0x1f
#define csr_PrbsTapDly0_RANGE  15:0
#define csr_PrbsTapDly0_BITS   15:0
#define csr_PrbsTapDly0_MSB  15
#define csr_PrbsTapDly0_LSB  0
#define csr_PrbsTapDly0_MASK 0xffff
#define csr_DqsPreambleControl_RANGE  8:0
#define csr_DqsPreambleControl_BITS   8:0
#define csr_DqsPreambleControl_MSB  8
#define csr_DqsPreambleControl_LSB  0
#define csr_DqsPreambleControl_MASK 0x1ff
#define csr_TwoTckRxDqsPre_RANGE  0:0
#define csr_TwoTckRxDqsPre_BITS   0:0
#define csr_TwoTckRxDqsPre_MSB  0
#define csr_TwoTckRxDqsPre_LSB  0
#define csr_TwoTckRxDqsPre_MASK 0x1
#define csr_TwoTckTxDqsPre_RANGE  1:1
#define csr_TwoTckTxDqsPre_BITS   0:0
#define csr_TwoTckTxDqsPre_MSB  1
#define csr_TwoTckTxDqsPre_LSB  1
#define csr_TwoTckTxDqsPre_MASK 0x2
#define csr_PositionDfeInit_RANGE  4:2
#define csr_PositionDfeInit_BITS   2:0
#define csr_PositionDfeInit_MSB  4
#define csr_PositionDfeInit_LSB  2
#define csr_PositionDfeInit_MASK 0x1c
#define csr_LP4TglTwoTckTxDqsPre_RANGE  5:5
#define csr_LP4TglTwoTckTxDqsPre_BITS   0:0
#define csr_LP4TglTwoTckTxDqsPre_MSB  5
#define csr_LP4TglTwoTckTxDqsPre_LSB  5
#define csr_LP4TglTwoTckTxDqsPre_MASK 0x20
#define csr_LP4PostambleExt_RANGE  6:6
#define csr_LP4PostambleExt_BITS   0:0
#define csr_LP4PostambleExt_MSB  6
#define csr_LP4PostambleExt_LSB  6
#define csr_LP4PostambleExt_MASK 0x40
#define csr_LP4SttcPreBridgeRxEn_RANGE  7:7
#define csr_LP4SttcPreBridgeRxEn_BITS   0:0
#define csr_LP4SttcPreBridgeRxEn_MSB  7
#define csr_LP4SttcPreBridgeRxEn_LSB  7
#define csr_LP4SttcPreBridgeRxEn_MASK 0x80
#define csr_WDQSEXTENSION_RANGE  8:8
#define csr_WDQSEXTENSION_BITS   0:0
#define csr_WDQSEXTENSION_MSB  8
#define csr_WDQSEXTENSION_LSB  8
#define csr_WDQSEXTENSION_MASK 0x100
#define csr_StartVector0b13_RANGE  6:0
#define csr_StartVector0b13_BITS   6:0
#define csr_StartVector0b13_MSB  6
#define csr_StartVector0b13_LSB  0
#define csr_StartVector0b13_MASK 0x7f
#define csr_Seq0BStartVec13_RANGE  6:0
#define csr_Seq0BStartVec13_BITS   6:0
#define csr_Seq0BStartVec13_MSB  6
#define csr_Seq0BStartVec13_LSB  0
#define csr_Seq0BStartVec13_MASK 0x7f
#define csr_SequenceReg0b83s2_RANGE  8:0
#define csr_SequenceReg0b83s2_BITS   8:0
#define csr_SequenceReg0b83s2_MSB  8
#define csr_SequenceReg0b83s2_LSB  0
#define csr_SequenceReg0b83s2_MASK 0x1ff
#define csr_AcsmSeq1x4_RANGE  15:0
#define csr_AcsmSeq1x4_BITS   15:0
#define csr_AcsmSeq1x4_MSB  15
#define csr_AcsmSeq1x4_LSB  0
#define csr_AcsmSeq1x4_MASK 0xffff
#define csr_AcsmDdrCs4_RANGE  7:0
#define csr_AcsmDdrCs4_BITS   7:0
#define csr_AcsmDdrCs4_MSB  7
#define csr_AcsmDdrCs4_LSB  0
#define csr_AcsmDdrCs4_MASK 0xff
#define csr_AcsmSaveGen4_RANGE  8:8
#define csr_AcsmSaveGen4_BITS   0:0
#define csr_AcsmSaveGen4_MSB  8
#define csr_AcsmSaveGen4_LSB  8
#define csr_AcsmSaveGen4_MASK 0x100
#define csr_AcsmLoadChk4_RANGE  9:9
#define csr_AcsmLoadChk4_BITS   0:0
#define csr_AcsmLoadChk4_MSB  9
#define csr_AcsmLoadChk4_LSB  9
#define csr_AcsmLoadChk4_MASK 0x200
#define csr_AcsmNoRxEnb4_RANGE  10:10
#define csr_AcsmNoRxEnb4_BITS   0:0
#define csr_AcsmNoRxEnb4_MSB  10
#define csr_AcsmNoRxEnb4_LSB  10
#define csr_AcsmNoRxEnb4_MASK 0x400
#define csr_AcsmNoRxVal4_RANGE  11:11
#define csr_AcsmNoRxVal4_BITS   0:0
#define csr_AcsmNoRxVal4_MSB  11
#define csr_AcsmNoRxVal4_LSB  11
#define csr_AcsmNoRxVal4_MASK 0x800
#define csr_AcsmDdrBnk4_RANGE  15:12
#define csr_AcsmDdrBnk4_BITS   3:0
#define csr_AcsmDdrBnk4_MSB  15
#define csr_AcsmDdrBnk4_LSB  12
#define csr_AcsmDdrBnk4_MASK 0xf000
#define csr_AsyncDbyteMode_RANGE  8:0
#define csr_AsyncDbyteMode_BITS   8:0
#define csr_AsyncDbyteMode_MSB  8
#define csr_AsyncDbyteMode_LSB  0
#define csr_AsyncDbyteMode_MASK 0x1ff
#define csr_HwtSwizzleHwtAddress4_RANGE  4:0
#define csr_HwtSwizzleHwtAddress4_BITS   4:0
#define csr_HwtSwizzleHwtAddress4_MSB  4
#define csr_HwtSwizzleHwtAddress4_LSB  0
#define csr_HwtSwizzleHwtAddress4_MASK 0x1f
#define csr_PrbsTapDly1_RANGE  15:0
#define csr_PrbsTapDly1_BITS   15:0
#define csr_PrbsTapDly1_MSB  15
#define csr_PrbsTapDly1_LSB  0
#define csr_PrbsTapDly1_MASK 0xffff
#define csr_MasterX4Config_RANGE  3:0
#define csr_MasterX4Config_BITS   3:0
#define csr_MasterX4Config_MSB  3
#define csr_MasterX4Config_LSB  0
#define csr_MasterX4Config_MASK 0xf
#define csr_X4TG_RANGE  3:0
#define csr_X4TG_BITS   3:0
#define csr_X4TG_MSB  3
#define csr_X4TG_LSB  0
#define csr_X4TG_MASK 0xf
#define csr_StartVector0b14_RANGE  6:0
#define csr_StartVector0b14_BITS   6:0
#define csr_StartVector0b14_MSB  6
#define csr_StartVector0b14_LSB  0
#define csr_StartVector0b14_MASK 0x7f
#define csr_Seq0BStartVec14_RANGE  6:0
#define csr_Seq0BStartVec14_BITS   6:0
#define csr_Seq0BStartVec14_MSB  6
#define csr_Seq0BStartVec14_LSB  0
#define csr_Seq0BStartVec14_MASK 0x7f
#define csr_SequenceReg0b84s0_RANGE  15:0
#define csr_SequenceReg0b84s0_BITS   15:0
#define csr_SequenceReg0b84s0_MSB  15
#define csr_SequenceReg0b84s0_LSB  0
#define csr_SequenceReg0b84s0_MASK 0xffff
#define csr_AcsmSeq1x5_RANGE  15:0
#define csr_AcsmSeq1x5_BITS   15:0
#define csr_AcsmSeq1x5_MSB  15
#define csr_AcsmSeq1x5_LSB  0
#define csr_AcsmSeq1x5_MASK 0xffff
#define csr_AcsmDdrCs5_RANGE  7:0
#define csr_AcsmDdrCs5_BITS   7:0
#define csr_AcsmDdrCs5_MSB  7
#define csr_AcsmDdrCs5_LSB  0
#define csr_AcsmDdrCs5_MASK 0xff
#define csr_AcsmSaveGen5_RANGE  8:8
#define csr_AcsmSaveGen5_BITS   0:0
#define csr_AcsmSaveGen5_MSB  8
#define csr_AcsmSaveGen5_LSB  8
#define csr_AcsmSaveGen5_MASK 0x100
#define csr_AcsmLoadChk5_RANGE  9:9
#define csr_AcsmLoadChk5_BITS   0:0
#define csr_AcsmLoadChk5_MSB  9
#define csr_AcsmLoadChk5_LSB  9
#define csr_AcsmLoadChk5_MASK 0x200
#define csr_AcsmNoRxEnb5_RANGE  10:10
#define csr_AcsmNoRxEnb5_BITS   0:0
#define csr_AcsmNoRxEnb5_MSB  10
#define csr_AcsmNoRxEnb5_LSB  10
#define csr_AcsmNoRxEnb5_MASK 0x400
#define csr_AcsmNoRxVal5_RANGE  11:11
#define csr_AcsmNoRxVal5_BITS   0:0
#define csr_AcsmNoRxVal5_MSB  11
#define csr_AcsmNoRxVal5_LSB  11
#define csr_AcsmNoRxVal5_MASK 0x800
#define csr_AcsmDdrBnk5_RANGE  15:12
#define csr_AcsmDdrBnk5_BITS   3:0
#define csr_AcsmDdrBnk5_MSB  15
#define csr_AcsmDdrBnk5_LSB  12
#define csr_AcsmDdrBnk5_MASK 0xf000
#define csr_HwtSwizzleHwtAddress5_RANGE  4:0
#define csr_HwtSwizzleHwtAddress5_BITS   4:0
#define csr_HwtSwizzleHwtAddress5_MSB  4
#define csr_HwtSwizzleHwtAddress5_LSB  0
#define csr_HwtSwizzleHwtAddress5_MASK 0x1f
#define csr_PrbsTapDly2_RANGE  15:0
#define csr_PrbsTapDly2_BITS   15:0
#define csr_PrbsTapDly2_MSB  15
#define csr_PrbsTapDly2_LSB  0
#define csr_PrbsTapDly2_MASK 0xffff
#define csr_WrLevBits_RANGE  7:0
#define csr_WrLevBits_BITS   7:0
#define csr_WrLevBits_MSB  7
#define csr_WrLevBits_LSB  0
#define csr_WrLevBits_MASK 0xff
#define csr_WrLevForDQSL_RANGE  3:0
#define csr_WrLevForDQSL_BITS   3:0
#define csr_WrLevForDQSL_MSB  3
#define csr_WrLevForDQSL_LSB  0
#define csr_WrLevForDQSL_MASK 0xf
#define csr_WrLevForDQSU_RANGE  7:4
#define csr_WrLevForDQSU_BITS   3:0
#define csr_WrLevForDQSU_MSB  7
#define csr_WrLevForDQSU_LSB  4
#define csr_WrLevForDQSU_MASK 0xf0
#define csr_StartVector0b15_RANGE  6:0
#define csr_StartVector0b15_BITS   6:0
#define csr_StartVector0b15_MSB  6
#define csr_StartVector0b15_LSB  0
#define csr_StartVector0b15_MASK 0x7f
#define csr_Seq0BStartVec15_RANGE  6:0
#define csr_Seq0BStartVec15_BITS   6:0
#define csr_Seq0BStartVec15_MSB  6
#define csr_Seq0BStartVec15_LSB  0
#define csr_Seq0BStartVec15_MASK 0x7f
#define csr_SequenceReg0b84s1_RANGE  15:0
#define csr_SequenceReg0b84s1_BITS   15:0
#define csr_SequenceReg0b84s1_MSB  15
#define csr_SequenceReg0b84s1_LSB  0
#define csr_SequenceReg0b84s1_MASK 0xffff
#define csr_AcsmSeq1x6_RANGE  15:0
#define csr_AcsmSeq1x6_BITS   15:0
#define csr_AcsmSeq1x6_MSB  15
#define csr_AcsmSeq1x6_LSB  0
#define csr_AcsmSeq1x6_MASK 0xffff
#define csr_AcsmDdrCs6_RANGE  7:0
#define csr_AcsmDdrCs6_BITS   7:0
#define csr_AcsmDdrCs6_MSB  7
#define csr_AcsmDdrCs6_LSB  0
#define csr_AcsmDdrCs6_MASK 0xff
#define csr_AcsmSaveGen6_RANGE  8:8
#define csr_AcsmSaveGen6_BITS   0:0
#define csr_AcsmSaveGen6_MSB  8
#define csr_AcsmSaveGen6_LSB  8
#define csr_AcsmSaveGen6_MASK 0x100
#define csr_AcsmLoadChk6_RANGE  9:9
#define csr_AcsmLoadChk6_BITS   0:0
#define csr_AcsmLoadChk6_MSB  9
#define csr_AcsmLoadChk6_LSB  9
#define csr_AcsmLoadChk6_MASK 0x200
#define csr_AcsmNoRxEnb6_RANGE  10:10
#define csr_AcsmNoRxEnb6_BITS   0:0
#define csr_AcsmNoRxEnb6_MSB  10
#define csr_AcsmNoRxEnb6_LSB  10
#define csr_AcsmNoRxEnb6_MASK 0x400
#define csr_AcsmNoRxVal6_RANGE  11:11
#define csr_AcsmNoRxVal6_BITS   0:0
#define csr_AcsmNoRxVal6_MSB  11
#define csr_AcsmNoRxVal6_LSB  11
#define csr_AcsmNoRxVal6_MASK 0x800
#define csr_AcsmDdrBnk6_RANGE  15:12
#define csr_AcsmDdrBnk6_BITS   3:0
#define csr_AcsmDdrBnk6_MSB  15
#define csr_AcsmDdrBnk6_LSB  12
#define csr_AcsmDdrBnk6_MASK 0xf000
#define csr_AsyncDbyteTxEn_RANGE  11:0
#define csr_AsyncDbyteTxEn_BITS   11:0
#define csr_AsyncDbyteTxEn_MSB  11
#define csr_AsyncDbyteTxEn_LSB  0
#define csr_AsyncDbyteTxEn_MASK 0xfff
#define csr_HwtSwizzleHwtAddress6_RANGE  4:0
#define csr_HwtSwizzleHwtAddress6_BITS   4:0
#define csr_HwtSwizzleHwtAddress6_MSB  4
#define csr_HwtSwizzleHwtAddress6_LSB  0
#define csr_HwtSwizzleHwtAddress6_MASK 0x1f
#define csr_PrbsTapDly3_RANGE  15:0
#define csr_PrbsTapDly3_BITS   15:0
#define csr_PrbsTapDly3_MSB  15
#define csr_PrbsTapDly3_LSB  0
#define csr_PrbsTapDly3_MASK 0xffff
#define csr_EnableCsMulticast_RANGE  0:0
#define csr_EnableCsMulticast_BITS   0:0
#define csr_EnableCsMulticast_MSB  0
#define csr_EnableCsMulticast_LSB  0
#define csr_EnableCsMulticast_MASK 0x1
#define csr_Seq0bWaitCondSel_RANGE  2:0
#define csr_Seq0bWaitCondSel_BITS   2:0
#define csr_Seq0bWaitCondSel_MSB  2
#define csr_Seq0bWaitCondSel_LSB  0
#define csr_Seq0bWaitCondSel_MASK 0x7
#define csr_SequenceReg0b84s2_RANGE  8:0
#define csr_SequenceReg0b84s2_BITS   8:0
#define csr_SequenceReg0b84s2_MSB  8
#define csr_SequenceReg0b84s2_LSB  0
#define csr_SequenceReg0b84s2_MASK 0x1ff
#define csr_AcsmSeq1x7_RANGE  15:0
#define csr_AcsmSeq1x7_BITS   15:0
#define csr_AcsmSeq1x7_MSB  15
#define csr_AcsmSeq1x7_LSB  0
#define csr_AcsmSeq1x7_MASK 0xffff
#define csr_AcsmDdrCs7_RANGE  7:0
#define csr_AcsmDdrCs7_BITS   7:0
#define csr_AcsmDdrCs7_MSB  7
#define csr_AcsmDdrCs7_LSB  0
#define csr_AcsmDdrCs7_MASK 0xff
#define csr_AcsmSaveGen7_RANGE  8:8
#define csr_AcsmSaveGen7_BITS   0:0
#define csr_AcsmSaveGen7_MSB  8
#define csr_AcsmSaveGen7_LSB  8
#define csr_AcsmSaveGen7_MASK 0x100
#define csr_AcsmLoadChk7_RANGE  9:9
#define csr_AcsmLoadChk7_BITS   0:0
#define csr_AcsmLoadChk7_MSB  9
#define csr_AcsmLoadChk7_LSB  9
#define csr_AcsmLoadChk7_MASK 0x200
#define csr_AcsmNoRxEnb7_RANGE  10:10
#define csr_AcsmNoRxEnb7_BITS   0:0
#define csr_AcsmNoRxEnb7_MSB  10
#define csr_AcsmNoRxEnb7_LSB  10
#define csr_AcsmNoRxEnb7_MASK 0x400
#define csr_AcsmNoRxVal7_RANGE  11:11
#define csr_AcsmNoRxVal7_BITS   0:0
#define csr_AcsmNoRxVal7_MSB  11
#define csr_AcsmNoRxVal7_LSB  11
#define csr_AcsmNoRxVal7_MASK 0x800
#define csr_AcsmDdrBnk7_RANGE  15:12
#define csr_AcsmDdrBnk7_BITS   3:0
#define csr_AcsmDdrBnk7_MSB  15
#define csr_AcsmDdrBnk7_LSB  12
#define csr_AcsmDdrBnk7_MASK 0xf000
#define csr_HwtSwizzleHwtAddress7_RANGE  4:0
#define csr_HwtSwizzleHwtAddress7_BITS   4:0
#define csr_HwtSwizzleHwtAddress7_MSB  4
#define csr_HwtSwizzleHwtAddress7_LSB  0
#define csr_HwtSwizzleHwtAddress7_MASK 0x1f
#define csr_AForceDrvCont_RANGE  3:0
#define csr_AForceDrvCont_BITS   3:0
#define csr_AForceDrvCont_MSB  3
#define csr_AForceDrvCont_LSB  0
#define csr_AForceDrvCont_MASK 0xf
#define csr_HwtLpCsMultiCast_RANGE  0:0
#define csr_HwtLpCsMultiCast_BITS   0:0
#define csr_HwtLpCsMultiCast_MSB  0
#define csr_HwtLpCsMultiCast_LSB  0
#define csr_HwtLpCsMultiCast_MASK 0x1
#define csr_AForceTriCont_RANGE  3:0
#define csr_AForceTriCont_BITS   3:0
#define csr_AForceTriCont_MSB  3
#define csr_AForceTriCont_LSB  0
#define csr_AForceTriCont_MASK 0xf
#define csr_PhyInLP3_RANGE  0:0
#define csr_PhyInLP3_BITS   0:0
#define csr_PhyInLP3_MSB  0
#define csr_PhyInLP3_LSB  0
#define csr_PhyInLP3_MASK 0x1
#define csr_SequenceReg0b85s0_RANGE  15:0
#define csr_SequenceReg0b85s0_BITS   15:0
#define csr_SequenceReg0b85s0_MSB  15
#define csr_SequenceReg0b85s0_LSB  0
#define csr_SequenceReg0b85s0_MASK 0xffff
#define csr_AcsmSeq1x8_RANGE  15:0
#define csr_AcsmSeq1x8_BITS   15:0
#define csr_AcsmSeq1x8_MSB  15
#define csr_AcsmSeq1x8_LSB  0
#define csr_AcsmSeq1x8_MASK 0xffff
#define csr_AcsmDdrCs8_RANGE  7:0
#define csr_AcsmDdrCs8_BITS   7:0
#define csr_AcsmDdrCs8_MSB  7
#define csr_AcsmDdrCs8_LSB  0
#define csr_AcsmDdrCs8_MASK 0xff
#define csr_AcsmSaveGen8_RANGE  8:8
#define csr_AcsmSaveGen8_BITS   0:0
#define csr_AcsmSaveGen8_MSB  8
#define csr_AcsmSaveGen8_LSB  8
#define csr_AcsmSaveGen8_MASK 0x100
#define csr_AcsmLoadChk8_RANGE  9:9
#define csr_AcsmLoadChk8_BITS   0:0
#define csr_AcsmLoadChk8_MSB  9
#define csr_AcsmLoadChk8_LSB  9
#define csr_AcsmLoadChk8_MASK 0x200
#define csr_AcsmNoRxEnb8_RANGE  10:10
#define csr_AcsmNoRxEnb8_BITS   0:0
#define csr_AcsmNoRxEnb8_MSB  10
#define csr_AcsmNoRxEnb8_LSB  10
#define csr_AcsmNoRxEnb8_MASK 0x400
#define csr_AcsmNoRxVal8_RANGE  11:11
#define csr_AcsmNoRxVal8_BITS   0:0
#define csr_AcsmNoRxVal8_MSB  11
#define csr_AcsmNoRxVal8_LSB  11
#define csr_AcsmNoRxVal8_MASK 0x800
#define csr_AcsmDdrBnk8_RANGE  15:12
#define csr_AcsmDdrBnk8_BITS   3:0
#define csr_AcsmDdrBnk8_MSB  15
#define csr_AcsmDdrBnk8_LSB  12
#define csr_AcsmDdrBnk8_MASK 0xf000
#define csr_AsyncDbyteTxData_RANGE  11:0
#define csr_AsyncDbyteTxData_BITS   11:0
#define csr_AsyncDbyteTxData_MSB  11
#define csr_AsyncDbyteTxData_LSB  0
#define csr_AsyncDbyteTxData_MASK 0xfff
#define csr_HwtSwizzleHwtAddress8_RANGE  4:0
#define csr_HwtSwizzleHwtAddress8_BITS   4:0
#define csr_HwtSwizzleHwtAddress8_MSB  4
#define csr_HwtSwizzleHwtAddress8_LSB  0
#define csr_HwtSwizzleHwtAddress8_MASK 0x1f
#define csr_SequenceReg0b0s0_RANGE  15:0
#define csr_SequenceReg0b0s0_BITS   15:0
#define csr_SequenceReg0b0s0_MSB  15
#define csr_SequenceReg0b0s0_LSB  0
#define csr_SequenceReg0b0s0_MASK 0xffff
#define csr_SequenceReg0b85s1_RANGE  15:0
#define csr_SequenceReg0b85s1_BITS   15:0
#define csr_SequenceReg0b85s1_MSB  15
#define csr_SequenceReg0b85s1_LSB  0
#define csr_SequenceReg0b85s1_MASK 0xffff
#define csr_AcsmSeq1x9_RANGE  15:0
#define csr_AcsmSeq1x9_BITS   15:0
#define csr_AcsmSeq1x9_MSB  15
#define csr_AcsmSeq1x9_LSB  0
#define csr_AcsmSeq1x9_MASK 0xffff
#define csr_AcsmDdrCs9_RANGE  7:0
#define csr_AcsmDdrCs9_BITS   7:0
#define csr_AcsmDdrCs9_MSB  7
#define csr_AcsmDdrCs9_LSB  0
#define csr_AcsmDdrCs9_MASK 0xff
#define csr_AcsmSaveGen9_RANGE  8:8
#define csr_AcsmSaveGen9_BITS   0:0
#define csr_AcsmSaveGen9_MSB  8
#define csr_AcsmSaveGen9_LSB  8
#define csr_AcsmSaveGen9_MASK 0x100
#define csr_AcsmLoadChk9_RANGE  9:9
#define csr_AcsmLoadChk9_BITS   0:0
#define csr_AcsmLoadChk9_MSB  9
#define csr_AcsmLoadChk9_LSB  9
#define csr_AcsmLoadChk9_MASK 0x200
#define csr_AcsmNoRxEnb9_RANGE  10:10
#define csr_AcsmNoRxEnb9_BITS   0:0
#define csr_AcsmNoRxEnb9_MSB  10
#define csr_AcsmNoRxEnb9_LSB  10
#define csr_AcsmNoRxEnb9_MASK 0x400
#define csr_AcsmNoRxVal9_RANGE  11:11
#define csr_AcsmNoRxVal9_BITS   0:0
#define csr_AcsmNoRxVal9_MSB  11
#define csr_AcsmNoRxVal9_LSB  11
#define csr_AcsmNoRxVal9_MASK 0x800
#define csr_AcsmDdrBnk9_RANGE  15:12
#define csr_AcsmDdrBnk9_BITS   3:0
#define csr_AcsmDdrBnk9_MSB  15
#define csr_AcsmDdrBnk9_LSB  12
#define csr_AcsmDdrBnk9_MASK 0xf000
#define csr_HwtSwizzleHwtAddress9_RANGE  4:0
#define csr_HwtSwizzleHwtAddress9_BITS   4:0
#define csr_HwtSwizzleHwtAddress9_MSB  4
#define csr_HwtSwizzleHwtAddress9_LSB  0
#define csr_HwtSwizzleHwtAddress9_MASK 0x1f
#define csr_SequenceReg0b0s1_RANGE  15:0
#define csr_SequenceReg0b0s1_BITS   15:0
#define csr_SequenceReg0b0s1_MSB  15
#define csr_SequenceReg0b0s1_LSB  0
#define csr_SequenceReg0b0s1_MASK 0xffff
#define csr_SequenceReg0b85s2_RANGE  8:0
#define csr_SequenceReg0b85s2_BITS   8:0
#define csr_SequenceReg0b85s2_MSB  8
#define csr_SequenceReg0b85s2_LSB  0
#define csr_SequenceReg0b85s2_MASK 0x1ff
#define csr_AcsmSeq1x10_RANGE  15:0
#define csr_AcsmSeq1x10_BITS   15:0
#define csr_AcsmSeq1x10_MSB  15
#define csr_AcsmSeq1x10_LSB  0
#define csr_AcsmSeq1x10_MASK 0xffff
#define csr_AcsmDdrCs10_RANGE  7:0
#define csr_AcsmDdrCs10_BITS   7:0
#define csr_AcsmDdrCs10_MSB  7
#define csr_AcsmDdrCs10_LSB  0
#define csr_AcsmDdrCs10_MASK 0xff
#define csr_AcsmSaveGen10_RANGE  8:8
#define csr_AcsmSaveGen10_BITS   0:0
#define csr_AcsmSaveGen10_MSB  8
#define csr_AcsmSaveGen10_LSB  8
#define csr_AcsmSaveGen10_MASK 0x100
#define csr_AcsmLoadChk10_RANGE  9:9
#define csr_AcsmLoadChk10_BITS   0:0
#define csr_AcsmLoadChk10_MSB  9
#define csr_AcsmLoadChk10_LSB  9
#define csr_AcsmLoadChk10_MASK 0x200
#define csr_AcsmNoRxEnb10_RANGE  10:10
#define csr_AcsmNoRxEnb10_BITS   0:0
#define csr_AcsmNoRxEnb10_MSB  10
#define csr_AcsmNoRxEnb10_LSB  10
#define csr_AcsmNoRxEnb10_MASK 0x400
#define csr_AcsmNoRxVal10_RANGE  11:11
#define csr_AcsmNoRxVal10_BITS   0:0
#define csr_AcsmNoRxVal10_MSB  11
#define csr_AcsmNoRxVal10_LSB  11
#define csr_AcsmNoRxVal10_MASK 0x800
#define csr_AcsmDdrBnk10_RANGE  15:12
#define csr_AcsmDdrBnk10_BITS   3:0
#define csr_AcsmDdrBnk10_MSB  15
#define csr_AcsmDdrBnk10_LSB  12
#define csr_AcsmDdrBnk10_MASK 0xf000
#define csr_AsyncDbyteRxData_RANGE  11:0
#define csr_AsyncDbyteRxData_BITS   11:0
#define csr_AsyncDbyteRxData_MSB  11
#define csr_AsyncDbyteRxData_LSB  0
#define csr_AsyncDbyteRxData_MASK 0xfff
#define csr_HwtSwizzleHwtAddress10_RANGE  4:0
#define csr_HwtSwizzleHwtAddress10_BITS   4:0
#define csr_HwtSwizzleHwtAddress10_MSB  4
#define csr_HwtSwizzleHwtAddress10_LSB  0
#define csr_HwtSwizzleHwtAddress10_MASK 0x1f
#define csr_SequenceReg0b0s2_RANGE  8:0
#define csr_SequenceReg0b0s2_BITS   8:0
#define csr_SequenceReg0b0s2_MSB  8
#define csr_SequenceReg0b0s2_LSB  0
#define csr_SequenceReg0b0s2_MASK 0x1ff
#define csr_SequenceReg0b86s0_RANGE  15:0
#define csr_SequenceReg0b86s0_BITS   15:0
#define csr_SequenceReg0b86s0_MSB  15
#define csr_SequenceReg0b86s0_LSB  0
#define csr_SequenceReg0b86s0_MASK 0xffff
#define csr_AcsmSeq1x11_RANGE  15:0
#define csr_AcsmSeq1x11_BITS   15:0
#define csr_AcsmSeq1x11_MSB  15
#define csr_AcsmSeq1x11_LSB  0
#define csr_AcsmSeq1x11_MASK 0xffff
#define csr_AcsmDdrCs11_RANGE  7:0
#define csr_AcsmDdrCs11_BITS   7:0
#define csr_AcsmDdrCs11_MSB  7
#define csr_AcsmDdrCs11_LSB  0
#define csr_AcsmDdrCs11_MASK 0xff
#define csr_AcsmSaveGen11_RANGE  8:8
#define csr_AcsmSaveGen11_BITS   0:0
#define csr_AcsmSaveGen11_MSB  8
#define csr_AcsmSaveGen11_LSB  8
#define csr_AcsmSaveGen11_MASK 0x100
#define csr_AcsmLoadChk11_RANGE  9:9
#define csr_AcsmLoadChk11_BITS   0:0
#define csr_AcsmLoadChk11_MSB  9
#define csr_AcsmLoadChk11_LSB  9
#define csr_AcsmLoadChk11_MASK 0x200
#define csr_AcsmNoRxEnb11_RANGE  10:10
#define csr_AcsmNoRxEnb11_BITS   0:0
#define csr_AcsmNoRxEnb11_MSB  10
#define csr_AcsmNoRxEnb11_LSB  10
#define csr_AcsmNoRxEnb11_MASK 0x400
#define csr_AcsmNoRxVal11_RANGE  11:11
#define csr_AcsmNoRxVal11_BITS   0:0
#define csr_AcsmNoRxVal11_MSB  11
#define csr_AcsmNoRxVal11_LSB  11
#define csr_AcsmNoRxVal11_MASK 0x800
#define csr_AcsmDdrBnk11_RANGE  15:12
#define csr_AcsmDdrBnk11_BITS   3:0
#define csr_AcsmDdrBnk11_MSB  15
#define csr_AcsmDdrBnk11_LSB  12
#define csr_AcsmDdrBnk11_MASK 0xf000
#define csr_HwtSwizzleHwtAddress11_RANGE  4:0
#define csr_HwtSwizzleHwtAddress11_BITS   4:0
#define csr_HwtSwizzleHwtAddress11_MSB  4
#define csr_HwtSwizzleHwtAddress11_LSB  0
#define csr_HwtSwizzleHwtAddress11_MASK 0x1f
#define csr_SequenceReg0b1s0_RANGE  15:0
#define csr_SequenceReg0b1s0_BITS   15:0
#define csr_SequenceReg0b1s0_MSB  15
#define csr_SequenceReg0b1s0_LSB  0
#define csr_SequenceReg0b1s0_MASK 0xffff
#define csr_SequenceReg0b86s1_RANGE  15:0
#define csr_SequenceReg0b86s1_BITS   15:0
#define csr_SequenceReg0b86s1_MSB  15
#define csr_SequenceReg0b86s1_LSB  0
#define csr_SequenceReg0b86s1_MASK 0xffff
#define csr_AcsmSeq1x12_RANGE  15:0
#define csr_AcsmSeq1x12_BITS   15:0
#define csr_AcsmSeq1x12_MSB  15
#define csr_AcsmSeq1x12_LSB  0
#define csr_AcsmSeq1x12_MASK 0xffff
#define csr_AcsmDdrCs12_RANGE  7:0
#define csr_AcsmDdrCs12_BITS   7:0
#define csr_AcsmDdrCs12_MSB  7
#define csr_AcsmDdrCs12_LSB  0
#define csr_AcsmDdrCs12_MASK 0xff
#define csr_AcsmSaveGen12_RANGE  8:8
#define csr_AcsmSaveGen12_BITS   0:0
#define csr_AcsmSaveGen12_MSB  8
#define csr_AcsmSaveGen12_LSB  8
#define csr_AcsmSaveGen12_MASK 0x100
#define csr_AcsmLoadChk12_RANGE  9:9
#define csr_AcsmLoadChk12_BITS   0:0
#define csr_AcsmLoadChk12_MSB  9
#define csr_AcsmLoadChk12_LSB  9
#define csr_AcsmLoadChk12_MASK 0x200
#define csr_AcsmNoRxEnb12_RANGE  10:10
#define csr_AcsmNoRxEnb12_BITS   0:0
#define csr_AcsmNoRxEnb12_MSB  10
#define csr_AcsmNoRxEnb12_LSB  10
#define csr_AcsmNoRxEnb12_MASK 0x400
#define csr_AcsmNoRxVal12_RANGE  11:11
#define csr_AcsmNoRxVal12_BITS   0:0
#define csr_AcsmNoRxVal12_MSB  11
#define csr_AcsmNoRxVal12_LSB  11
#define csr_AcsmNoRxVal12_MASK 0x800
#define csr_AcsmDdrBnk12_RANGE  15:12
#define csr_AcsmDdrBnk12_BITS   3:0
#define csr_AcsmDdrBnk12_MSB  15
#define csr_AcsmDdrBnk12_LSB  12
#define csr_AcsmDdrBnk12_MASK 0xf000
#define csr_Acx4AnibDis_RANGE  11:0
#define csr_Acx4AnibDis_BITS   11:0
#define csr_Acx4AnibDis_MSB  11
#define csr_Acx4AnibDis_LSB  0
#define csr_Acx4AnibDis_MASK 0xfff
#define csr_HwtSwizzleHwtAddress12_RANGE  4:0
#define csr_HwtSwizzleHwtAddress12_BITS   4:0
#define csr_HwtSwizzleHwtAddress12_MSB  4
#define csr_HwtSwizzleHwtAddress12_LSB  0
#define csr_HwtSwizzleHwtAddress12_MASK 0x1f
#define csr_DMIPinPresent_RANGE  0:0
#define csr_DMIPinPresent_BITS   0:0
#define csr_DMIPinPresent_MSB  0
#define csr_DMIPinPresent_LSB  0
#define csr_DMIPinPresent_MASK 0x1
#define csr_RdDbiEnabled_RANGE  0:0
#define csr_RdDbiEnabled_BITS   0:0
#define csr_RdDbiEnabled_MSB  0
#define csr_RdDbiEnabled_LSB  0
#define csr_RdDbiEnabled_MASK 0x1
#define csr_SequenceReg0b1s1_RANGE  15:0
#define csr_SequenceReg0b1s1_BITS   15:0
#define csr_SequenceReg0b1s1_MSB  15
#define csr_SequenceReg0b1s1_LSB  0
#define csr_SequenceReg0b1s1_MASK 0xffff
#define csr_SequenceReg0b86s2_RANGE  8:0
#define csr_SequenceReg0b86s2_BITS   8:0
#define csr_SequenceReg0b86s2_MSB  8
#define csr_SequenceReg0b86s2_LSB  0
#define csr_SequenceReg0b86s2_MASK 0x1ff
#define csr_AcsmSeq1x13_RANGE  15:0
#define csr_AcsmSeq1x13_BITS   15:0
#define csr_AcsmSeq1x13_MSB  15
#define csr_AcsmSeq1x13_LSB  0
#define csr_AcsmSeq1x13_MASK 0xffff
#define csr_AcsmDdrCs13_RANGE  7:0
#define csr_AcsmDdrCs13_BITS   7:0
#define csr_AcsmDdrCs13_MSB  7
#define csr_AcsmDdrCs13_LSB  0
#define csr_AcsmDdrCs13_MASK 0xff
#define csr_AcsmSaveGen13_RANGE  8:8
#define csr_AcsmSaveGen13_BITS   0:0
#define csr_AcsmSaveGen13_MSB  8
#define csr_AcsmSaveGen13_LSB  8
#define csr_AcsmSaveGen13_MASK 0x100
#define csr_AcsmLoadChk13_RANGE  9:9
#define csr_AcsmLoadChk13_BITS   0:0
#define csr_AcsmLoadChk13_MSB  9
#define csr_AcsmLoadChk13_LSB  9
#define csr_AcsmLoadChk13_MASK 0x200
#define csr_AcsmNoRxEnb13_RANGE  10:10
#define csr_AcsmNoRxEnb13_BITS   0:0
#define csr_AcsmNoRxEnb13_MSB  10
#define csr_AcsmNoRxEnb13_LSB  10
#define csr_AcsmNoRxEnb13_MASK 0x400
#define csr_AcsmNoRxVal13_RANGE  11:11
#define csr_AcsmNoRxVal13_BITS   0:0
#define csr_AcsmNoRxVal13_MSB  11
#define csr_AcsmNoRxVal13_LSB  11
#define csr_AcsmNoRxVal13_MASK 0x800
#define csr_AcsmDdrBnk13_RANGE  15:12
#define csr_AcsmDdrBnk13_BITS   3:0
#define csr_AcsmDdrBnk13_MSB  15
#define csr_AcsmDdrBnk13_LSB  12
#define csr_AcsmDdrBnk13_MASK 0xf000
#define csr_HwtSwizzleHwtAddress13_RANGE  4:0
#define csr_HwtSwizzleHwtAddress13_BITS   4:0
#define csr_HwtSwizzleHwtAddress13_MSB  4
#define csr_HwtSwizzleHwtAddress13_LSB  0
#define csr_HwtSwizzleHwtAddress13_MASK 0x1f
#define csr_ARdPtrInitVal_RANGE  3:0
#define csr_ARdPtrInitVal_BITS   3:0
#define csr_ARdPtrInitVal_MSB  3
#define csr_ARdPtrInitVal_LSB  0
#define csr_ARdPtrInitVal_MASK 0xf
#define csr_SequenceReg0b1s2_RANGE  8:0
#define csr_SequenceReg0b1s2_BITS   8:0
#define csr_SequenceReg0b1s2_MSB  8
#define csr_SequenceReg0b1s2_LSB  0
#define csr_SequenceReg0b1s2_MASK 0x1ff
#define csr_SequenceReg0b87s0_RANGE  15:0
#define csr_SequenceReg0b87s0_BITS   15:0
#define csr_SequenceReg0b87s0_MSB  15
#define csr_SequenceReg0b87s0_LSB  0
#define csr_SequenceReg0b87s0_MASK 0xffff
#define csr_AcsmSeq1x14_RANGE  15:0
#define csr_AcsmSeq1x14_BITS   15:0
#define csr_AcsmSeq1x14_MSB  15
#define csr_AcsmSeq1x14_LSB  0
#define csr_AcsmSeq1x14_MASK 0xffff
#define csr_AcsmDdrCs14_RANGE  7:0
#define csr_AcsmDdrCs14_BITS   7:0
#define csr_AcsmDdrCs14_MSB  7
#define csr_AcsmDdrCs14_LSB  0
#define csr_AcsmDdrCs14_MASK 0xff
#define csr_AcsmSaveGen14_RANGE  8:8
#define csr_AcsmSaveGen14_BITS   0:0
#define csr_AcsmSaveGen14_MSB  8
#define csr_AcsmSaveGen14_LSB  8
#define csr_AcsmSaveGen14_MASK 0x100
#define csr_AcsmLoadChk14_RANGE  9:9
#define csr_AcsmLoadChk14_BITS   0:0
#define csr_AcsmLoadChk14_MSB  9
#define csr_AcsmLoadChk14_LSB  9
#define csr_AcsmLoadChk14_MASK 0x200
#define csr_AcsmNoRxEnb14_RANGE  10:10
#define csr_AcsmNoRxEnb14_BITS   0:0
#define csr_AcsmNoRxEnb14_MSB  10
#define csr_AcsmNoRxEnb14_LSB  10
#define csr_AcsmNoRxEnb14_MASK 0x400
#define csr_AcsmNoRxVal14_RANGE  11:11
#define csr_AcsmNoRxVal14_BITS   0:0
#define csr_AcsmNoRxVal14_MSB  11
#define csr_AcsmNoRxVal14_LSB  11
#define csr_AcsmNoRxVal14_MASK 0x800
#define csr_AcsmDdrBnk14_RANGE  15:12
#define csr_AcsmDdrBnk14_BITS   3:0
#define csr_AcsmDdrBnk14_MSB  15
#define csr_AcsmDdrBnk14_LSB  12
#define csr_AcsmDdrBnk14_MASK 0xf000
#define csr_HwtSwizzleHwtAddress14_RANGE  4:0
#define csr_HwtSwizzleHwtAddress14_BITS   4:0
#define csr_HwtSwizzleHwtAddress14_MSB  4
#define csr_HwtSwizzleHwtAddress14_LSB  0
#define csr_HwtSwizzleHwtAddress14_MASK 0x1f
#define csr_SequenceReg0b2s0_RANGE  15:0
#define csr_SequenceReg0b2s0_BITS   15:0
#define csr_SequenceReg0b2s0_MSB  15
#define csr_SequenceReg0b2s0_LSB  0
#define csr_SequenceReg0b2s0_MASK 0xffff
#define csr_SequenceReg0b87s1_RANGE  15:0
#define csr_SequenceReg0b87s1_BITS   15:0
#define csr_SequenceReg0b87s1_MSB  15
#define csr_SequenceReg0b87s1_LSB  0
#define csr_SequenceReg0b87s1_MASK 0xffff
#define csr_AcsmSeq1x15_RANGE  15:0
#define csr_AcsmSeq1x15_BITS   15:0
#define csr_AcsmSeq1x15_MSB  15
#define csr_AcsmSeq1x15_LSB  0
#define csr_AcsmSeq1x15_MASK 0xffff
#define csr_AcsmDdrCs15_RANGE  7:0
#define csr_AcsmDdrCs15_BITS   7:0
#define csr_AcsmDdrCs15_MSB  7
#define csr_AcsmDdrCs15_LSB  0
#define csr_AcsmDdrCs15_MASK 0xff
#define csr_AcsmSaveGen15_RANGE  8:8
#define csr_AcsmSaveGen15_BITS   0:0
#define csr_AcsmSaveGen15_MSB  8
#define csr_AcsmSaveGen15_LSB  8
#define csr_AcsmSaveGen15_MASK 0x100
#define csr_AcsmLoadChk15_RANGE  9:9
#define csr_AcsmLoadChk15_BITS   0:0
#define csr_AcsmLoadChk15_MSB  9
#define csr_AcsmLoadChk15_LSB  9
#define csr_AcsmLoadChk15_MASK 0x200
#define csr_AcsmNoRxEnb15_RANGE  10:10
#define csr_AcsmNoRxEnb15_BITS   0:0
#define csr_AcsmNoRxEnb15_MSB  10
#define csr_AcsmNoRxEnb15_LSB  10
#define csr_AcsmNoRxEnb15_MASK 0x400
#define csr_AcsmNoRxVal15_RANGE  11:11
#define csr_AcsmNoRxVal15_BITS   0:0
#define csr_AcsmNoRxVal15_MSB  11
#define csr_AcsmNoRxVal15_LSB  11
#define csr_AcsmNoRxVal15_MASK 0x800
#define csr_AcsmDdrBnk15_RANGE  15:12
#define csr_AcsmDdrBnk15_BITS   3:0
#define csr_AcsmDdrBnk15_MSB  15
#define csr_AcsmDdrBnk15_LSB  12
#define csr_AcsmDdrBnk15_MASK 0xf000
#define csr_HwtSwizzleHwtAddress15_RANGE  4:0
#define csr_HwtSwizzleHwtAddress15_BITS   4:0
#define csr_HwtSwizzleHwtAddress15_MSB  4
#define csr_HwtSwizzleHwtAddress15_LSB  0
#define csr_HwtSwizzleHwtAddress15_MASK 0x1f
#define csr_Db0LcdlCalPhDetOut_RANGE  15:0
#define csr_Db0LcdlCalPhDetOut_BITS   15:0
#define csr_Db0LcdlCalPhDetOut_MSB  15
#define csr_Db0LcdlCalPhDetOut_LSB  0
#define csr_Db0LcdlCalPhDetOut_MASK 0xffff
#define csr_GenPrbsByte0_RANGE  15:0
#define csr_GenPrbsByte0_BITS   15:0
#define csr_GenPrbsByte0_MSB  15
#define csr_GenPrbsByte0_LSB  0
#define csr_GenPrbsByte0_MASK 0xffff
#define csr_SequenceReg0b2s1_RANGE  15:0
#define csr_SequenceReg0b2s1_BITS   15:0
#define csr_SequenceReg0b2s1_MSB  15
#define csr_SequenceReg0b2s1_LSB  0
#define csr_SequenceReg0b2s1_MASK 0xffff
#define csr_SequenceReg0b87s2_RANGE  8:0
#define csr_SequenceReg0b87s2_BITS   8:0
#define csr_SequenceReg0b87s2_MSB  8
#define csr_SequenceReg0b87s2_LSB  0
#define csr_SequenceReg0b87s2_MASK 0x1ff
#define csr_AcsmSeq1x16_RANGE  15:0
#define csr_AcsmSeq1x16_BITS   15:0
#define csr_AcsmSeq1x16_MSB  15
#define csr_AcsmSeq1x16_LSB  0
#define csr_AcsmSeq1x16_MASK 0xffff
#define csr_AcsmDdrCs16_RANGE  7:0
#define csr_AcsmDdrCs16_BITS   7:0
#define csr_AcsmDdrCs16_MSB  7
#define csr_AcsmDdrCs16_LSB  0
#define csr_AcsmDdrCs16_MASK 0xff
#define csr_AcsmSaveGen16_RANGE  8:8
#define csr_AcsmSaveGen16_BITS   0:0
#define csr_AcsmSaveGen16_MSB  8
#define csr_AcsmSaveGen16_LSB  8
#define csr_AcsmSaveGen16_MASK 0x100
#define csr_AcsmLoadChk16_RANGE  9:9
#define csr_AcsmLoadChk16_BITS   0:0
#define csr_AcsmLoadChk16_MSB  9
#define csr_AcsmLoadChk16_LSB  9
#define csr_AcsmLoadChk16_MASK 0x200
#define csr_AcsmNoRxEnb16_RANGE  10:10
#define csr_AcsmNoRxEnb16_BITS   0:0
#define csr_AcsmNoRxEnb16_MSB  10
#define csr_AcsmNoRxEnb16_LSB  10
#define csr_AcsmNoRxEnb16_MASK 0x400
#define csr_AcsmNoRxVal16_RANGE  11:11
#define csr_AcsmNoRxVal16_BITS   0:0
#define csr_AcsmNoRxVal16_MSB  11
#define csr_AcsmNoRxVal16_LSB  11
#define csr_AcsmNoRxVal16_MASK 0x800
#define csr_AcsmDdrBnk16_RANGE  15:12
#define csr_AcsmDdrBnk16_BITS   3:0
#define csr_AcsmDdrBnk16_MSB  15
#define csr_AcsmDdrBnk16_LSB  12
#define csr_AcsmDdrBnk16_MASK 0xf000
#define csr_VrefDAC1_RANGE  6:0
#define csr_VrefDAC1_BITS   6:0
#define csr_VrefDAC1_MSB  6
#define csr_VrefDAC1_LSB  0
#define csr_VrefDAC1_MASK 0x7f
#define csr_DctWriteOnly_RANGE  15:0
#define csr_DctWriteOnly_BITS   15:0
#define csr_DctWriteOnly_MSB  15
#define csr_DctWriteOnly_LSB  0
#define csr_DctWriteOnly_MASK 0xffff
#define csr_DctWriteOnlyShadow_RANGE  15:0
#define csr_DctWriteOnlyShadow_BITS   15:0
#define csr_DctWriteOnlyShadow_MSB  15
#define csr_DctWriteOnlyShadow_LSB  0
#define csr_DctWriteOnlyShadow_MASK 0xffff
#define csr_HwtSwizzleHwtAddress17_RANGE  4:0
#define csr_HwtSwizzleHwtAddress17_BITS   4:0
#define csr_HwtSwizzleHwtAddress17_MSB  4
#define csr_HwtSwizzleHwtAddress17_LSB  0
#define csr_HwtSwizzleHwtAddress17_MASK 0x1f
#define csr_Db1LcdlCalPhDetOut_RANGE  15:0
#define csr_Db1LcdlCalPhDetOut_BITS   15:0
#define csr_Db1LcdlCalPhDetOut_MSB  15
#define csr_Db1LcdlCalPhDetOut_LSB  0
#define csr_Db1LcdlCalPhDetOut_MASK 0xffff
#define csr_GenPrbsByte1_RANGE  15:0
#define csr_GenPrbsByte1_BITS   15:0
#define csr_GenPrbsByte1_MSB  15
#define csr_GenPrbsByte1_LSB  0
#define csr_GenPrbsByte1_MASK 0xffff
#define csr_SequenceReg0b2s2_RANGE  8:0
#define csr_SequenceReg0b2s2_BITS   8:0
#define csr_SequenceReg0b2s2_MSB  8
#define csr_SequenceReg0b2s2_LSB  0
#define csr_SequenceReg0b2s2_MASK 0x1ff
#define csr_SequenceReg0b88s0_RANGE  15:0
#define csr_SequenceReg0b88s0_BITS   15:0
#define csr_SequenceReg0b88s0_MSB  15
#define csr_SequenceReg0b88s0_LSB  0
#define csr_SequenceReg0b88s0_MASK 0xffff
#define csr_AcsmSeq1x17_RANGE  15:0
#define csr_AcsmSeq1x17_BITS   15:0
#define csr_AcsmSeq1x17_MSB  15
#define csr_AcsmSeq1x17_LSB  0
#define csr_AcsmSeq1x17_MASK 0xffff
#define csr_AcsmDdrCs17_RANGE  7:0
#define csr_AcsmDdrCs17_BITS   7:0
#define csr_AcsmDdrCs17_MSB  7
#define csr_AcsmDdrCs17_LSB  0
#define csr_AcsmDdrCs17_MASK 0xff
#define csr_AcsmSaveGen17_RANGE  8:8
#define csr_AcsmSaveGen17_BITS   0:0
#define csr_AcsmSaveGen17_MSB  8
#define csr_AcsmSaveGen17_LSB  8
#define csr_AcsmSaveGen17_MASK 0x100
#define csr_AcsmLoadChk17_RANGE  9:9
#define csr_AcsmLoadChk17_BITS   0:0
#define csr_AcsmLoadChk17_MSB  9
#define csr_AcsmLoadChk17_LSB  9
#define csr_AcsmLoadChk17_MASK 0x200
#define csr_AcsmNoRxEnb17_RANGE  10:10
#define csr_AcsmNoRxEnb17_BITS   0:0
#define csr_AcsmNoRxEnb17_MSB  10
#define csr_AcsmNoRxEnb17_LSB  10
#define csr_AcsmNoRxEnb17_MASK 0x400
#define csr_AcsmNoRxVal17_RANGE  11:11
#define csr_AcsmNoRxVal17_BITS   0:0
#define csr_AcsmNoRxVal17_MSB  11
#define csr_AcsmNoRxVal17_LSB  11
#define csr_AcsmNoRxVal17_MASK 0x800
#define csr_AcsmDdrBnk17_RANGE  15:12
#define csr_AcsmDdrBnk17_BITS   3:0
#define csr_AcsmDdrBnk17_MSB  15
#define csr_AcsmDdrBnk17_LSB  12
#define csr_AcsmDdrBnk17_MASK 0xf000
#define csr_DctWriteProt_RANGE  0:0
#define csr_DctWriteProt_BITS   0:0
#define csr_DctWriteProt_MSB  0
#define csr_DctWriteProt_LSB  0
#define csr_DctWriteProt_MASK 0x1
#define csr_HwtSwizzleHwtActN_RANGE  4:0
#define csr_HwtSwizzleHwtActN_BITS   4:0
#define csr_HwtSwizzleHwtActN_MSB  4
#define csr_HwtSwizzleHwtActN_LSB  0
#define csr_HwtSwizzleHwtActN_MASK 0x1f
#define csr_Db2LcdlCalPhDetOut_RANGE  15:0
#define csr_Db2LcdlCalPhDetOut_BITS   15:0
#define csr_Db2LcdlCalPhDetOut_MSB  15
#define csr_Db2LcdlCalPhDetOut_LSB  0
#define csr_Db2LcdlCalPhDetOut_MASK 0xffff
#define csr_TrainingCntr_RANGE  15:0
#define csr_TrainingCntr_BITS   15:0
#define csr_TrainingCntr_MSB  15
#define csr_TrainingCntr_LSB  0
#define csr_TrainingCntr_MASK 0xffff
#define csr_TrainingCntrFine_RANGE  9:0
#define csr_TrainingCntrFine_BITS   9:0
#define csr_TrainingCntrFine_MSB  9
#define csr_TrainingCntrFine_LSB  0
#define csr_TrainingCntrFine_MASK 0x3ff
#define csr_TrainingCntrCoarse_RANGE  15:10
#define csr_TrainingCntrCoarse_BITS   5:0
#define csr_TrainingCntrCoarse_MSB  15
#define csr_TrainingCntrCoarse_LSB  10
#define csr_TrainingCntrCoarse_MASK 0xfc00
#define csr_GenPrbsByte2_RANGE  15:0
#define csr_GenPrbsByte2_BITS   15:0
#define csr_GenPrbsByte2_MSB  15
#define csr_GenPrbsByte2_LSB  0
#define csr_GenPrbsByte2_MASK 0xffff
#define csr_SequenceReg0b3s0_RANGE  15:0
#define csr_SequenceReg0b3s0_BITS   15:0
#define csr_SequenceReg0b3s0_MSB  15
#define csr_SequenceReg0b3s0_LSB  0
#define csr_SequenceReg0b3s0_MASK 0xffff
#define csr_SequenceReg0b88s1_RANGE  15:0
#define csr_SequenceReg0b88s1_BITS   15:0
#define csr_SequenceReg0b88s1_MSB  15
#define csr_SequenceReg0b88s1_LSB  0
#define csr_SequenceReg0b88s1_MASK 0xffff
#define csr_AcsmSeq1x18_RANGE  15:0
#define csr_AcsmSeq1x18_BITS   15:0
#define csr_AcsmSeq1x18_MSB  15
#define csr_AcsmSeq1x18_LSB  0
#define csr_AcsmSeq1x18_MASK 0xffff
#define csr_AcsmDdrCs18_RANGE  7:0
#define csr_AcsmDdrCs18_BITS   7:0
#define csr_AcsmDdrCs18_MSB  7
#define csr_AcsmDdrCs18_LSB  0
#define csr_AcsmDdrCs18_MASK 0xff
#define csr_AcsmSaveGen18_RANGE  8:8
#define csr_AcsmSaveGen18_BITS   0:0
#define csr_AcsmSaveGen18_MSB  8
#define csr_AcsmSaveGen18_LSB  8
#define csr_AcsmSaveGen18_MASK 0x100
#define csr_AcsmLoadChk18_RANGE  9:9
#define csr_AcsmLoadChk18_BITS   0:0
#define csr_AcsmLoadChk18_MSB  9
#define csr_AcsmLoadChk18_LSB  9
#define csr_AcsmLoadChk18_MASK 0x200
#define csr_AcsmNoRxEnb18_RANGE  10:10
#define csr_AcsmNoRxEnb18_BITS   0:0
#define csr_AcsmNoRxEnb18_MSB  10
#define csr_AcsmNoRxEnb18_LSB  10
#define csr_AcsmNoRxEnb18_MASK 0x400
#define csr_AcsmNoRxVal18_RANGE  11:11
#define csr_AcsmNoRxVal18_BITS   0:0
#define csr_AcsmNoRxVal18_MSB  11
#define csr_AcsmNoRxVal18_LSB  11
#define csr_AcsmNoRxVal18_MASK 0x800
#define csr_AcsmDdrBnk18_RANGE  15:12
#define csr_AcsmDdrBnk18_BITS   3:0
#define csr_AcsmDdrBnk18_MSB  15
#define csr_AcsmDdrBnk18_LSB  12
#define csr_AcsmDdrBnk18_MASK 0xf000
#define csr_UctWriteOnly_RANGE  15:0
#define csr_UctWriteOnly_BITS   15:0
#define csr_UctWriteOnly_MSB  15
#define csr_UctWriteOnly_LSB  0
#define csr_UctWriteOnly_MASK 0xffff
#define csr_UctWriteOnlyShadow_RANGE  15:0
#define csr_UctWriteOnlyShadow_BITS   15:0
#define csr_UctWriteOnlyShadow_MSB  15
#define csr_UctWriteOnlyShadow_LSB  0
#define csr_UctWriteOnlyShadow_MASK 0xffff
#define csr_HwtSwizzleHwtBank0_RANGE  4:0
#define csr_HwtSwizzleHwtBank0_BITS   4:0
#define csr_HwtSwizzleHwtBank0_MSB  4
#define csr_HwtSwizzleHwtBank0_LSB  0
#define csr_HwtSwizzleHwtBank0_MASK 0x1f
#define csr_Db3LcdlCalPhDetOut_RANGE  15:0
#define csr_Db3LcdlCalPhDetOut_BITS   15:0
#define csr_Db3LcdlCalPhDetOut_MSB  15
#define csr_Db3LcdlCalPhDetOut_LSB  0
#define csr_Db3LcdlCalPhDetOut_MASK 0xffff
#define csr_GenPrbsByte3_RANGE  15:0
#define csr_GenPrbsByte3_BITS   15:0
#define csr_GenPrbsByte3_MSB  15
#define csr_GenPrbsByte3_LSB  0
#define csr_GenPrbsByte3_MASK 0xffff
#define csr_SequenceReg0b3s1_RANGE  15:0
#define csr_SequenceReg0b3s1_BITS   15:0
#define csr_SequenceReg0b3s1_MSB  15
#define csr_SequenceReg0b3s1_LSB  0
#define csr_SequenceReg0b3s1_MASK 0xffff
#define csr_SequenceReg0b88s2_RANGE  8:0
#define csr_SequenceReg0b88s2_BITS   8:0
#define csr_SequenceReg0b88s2_MSB  8
#define csr_SequenceReg0b88s2_LSB  0
#define csr_SequenceReg0b88s2_MASK 0x1ff
#define csr_AcsmSeq1x19_RANGE  15:0
#define csr_AcsmSeq1x19_BITS   15:0
#define csr_AcsmSeq1x19_MSB  15
#define csr_AcsmSeq1x19_LSB  0
#define csr_AcsmSeq1x19_MASK 0xffff
#define csr_AcsmDdrCs19_RANGE  7:0
#define csr_AcsmDdrCs19_BITS   7:0
#define csr_AcsmDdrCs19_MSB  7
#define csr_AcsmDdrCs19_LSB  0
#define csr_AcsmDdrCs19_MASK 0xff
#define csr_AcsmSaveGen19_RANGE  8:8
#define csr_AcsmSaveGen19_BITS   0:0
#define csr_AcsmSaveGen19_MSB  8
#define csr_AcsmSaveGen19_LSB  8
#define csr_AcsmSaveGen19_MASK 0x100
#define csr_AcsmLoadChk19_RANGE  9:9
#define csr_AcsmLoadChk19_BITS   0:0
#define csr_AcsmLoadChk19_MSB  9
#define csr_AcsmLoadChk19_LSB  9
#define csr_AcsmLoadChk19_MASK 0x200
#define csr_AcsmNoRxEnb19_RANGE  10:10
#define csr_AcsmNoRxEnb19_BITS   0:0
#define csr_AcsmNoRxEnb19_MSB  10
#define csr_AcsmNoRxEnb19_LSB  10
#define csr_AcsmNoRxEnb19_MASK 0x400
#define csr_AcsmNoRxVal19_RANGE  11:11
#define csr_AcsmNoRxVal19_BITS   0:0
#define csr_AcsmNoRxVal19_MSB  11
#define csr_AcsmNoRxVal19_LSB  11
#define csr_AcsmNoRxVal19_MASK 0x800
#define csr_AcsmDdrBnk19_RANGE  15:12
#define csr_AcsmDdrBnk19_BITS   3:0
#define csr_AcsmDdrBnk19_MSB  15
#define csr_AcsmDdrBnk19_LSB  12
#define csr_AcsmDdrBnk19_MASK 0xf000
#define csr_UctWriteProt_RANGE  0:0
#define csr_UctWriteProt_BITS   0:0
#define csr_UctWriteProt_MSB  0
#define csr_UctWriteProt_LSB  0
#define csr_UctWriteProt_MASK 0x1
#define csr_HwtSwizzleHwtBank1_RANGE  4:0
#define csr_HwtSwizzleHwtBank1_BITS   4:0
#define csr_HwtSwizzleHwtBank1_MSB  4
#define csr_HwtSwizzleHwtBank1_LSB  0
#define csr_HwtSwizzleHwtBank1_MASK 0x1f
#define csr_Db4LcdlCalPhDetOut_RANGE  15:0
#define csr_Db4LcdlCalPhDetOut_BITS   15:0
#define csr_Db4LcdlCalPhDetOut_MSB  15
#define csr_Db4LcdlCalPhDetOut_LSB  0
#define csr_Db4LcdlCalPhDetOut_MASK 0xffff
#define csr_GenPrbsByte4_RANGE  15:0
#define csr_GenPrbsByte4_BITS   15:0
#define csr_GenPrbsByte4_MSB  15
#define csr_GenPrbsByte4_LSB  0
#define csr_GenPrbsByte4_MASK 0xffff
#define csr_SequenceReg0b3s2_RANGE  8:0
#define csr_SequenceReg0b3s2_BITS   8:0
#define csr_SequenceReg0b3s2_MSB  8
#define csr_SequenceReg0b3s2_LSB  0
#define csr_SequenceReg0b3s2_MASK 0x1ff
#define csr_SequenceReg0b89s0_RANGE  15:0
#define csr_SequenceReg0b89s0_BITS   15:0
#define csr_SequenceReg0b89s0_MSB  15
#define csr_SequenceReg0b89s0_LSB  0
#define csr_SequenceReg0b89s0_MASK 0xffff
#define csr_AcsmSeq1x20_RANGE  15:0
#define csr_AcsmSeq1x20_BITS   15:0
#define csr_AcsmSeq1x20_MSB  15
#define csr_AcsmSeq1x20_LSB  0
#define csr_AcsmSeq1x20_MASK 0xffff
#define csr_AcsmDdrCs20_RANGE  7:0
#define csr_AcsmDdrCs20_BITS   7:0
#define csr_AcsmDdrCs20_MSB  7
#define csr_AcsmDdrCs20_LSB  0
#define csr_AcsmDdrCs20_MASK 0xff
#define csr_AcsmSaveGen20_RANGE  8:8
#define csr_AcsmSaveGen20_BITS   0:0
#define csr_AcsmSaveGen20_MSB  8
#define csr_AcsmSaveGen20_LSB  8
#define csr_AcsmSaveGen20_MASK 0x100
#define csr_AcsmLoadChk20_RANGE  9:9
#define csr_AcsmLoadChk20_BITS   0:0
#define csr_AcsmLoadChk20_MSB  9
#define csr_AcsmLoadChk20_LSB  9
#define csr_AcsmLoadChk20_MASK 0x200
#define csr_AcsmNoRxEnb20_RANGE  10:10
#define csr_AcsmNoRxEnb20_BITS   0:0
#define csr_AcsmNoRxEnb20_MSB  10
#define csr_AcsmNoRxEnb20_LSB  10
#define csr_AcsmNoRxEnb20_MASK 0x400
#define csr_AcsmNoRxVal20_RANGE  11:11
#define csr_AcsmNoRxVal20_BITS   0:0
#define csr_AcsmNoRxVal20_MSB  11
#define csr_AcsmNoRxVal20_LSB  11
#define csr_AcsmNoRxVal20_MASK 0x800
#define csr_AcsmDdrBnk20_RANGE  15:12
#define csr_AcsmDdrBnk20_BITS   3:0
#define csr_AcsmDdrBnk20_MSB  15
#define csr_AcsmDdrBnk20_LSB  12
#define csr_AcsmDdrBnk20_MASK 0xf000
#define csr_UctDatWriteOnly_RANGE  15:0
#define csr_UctDatWriteOnly_BITS   15:0
#define csr_UctDatWriteOnly_MSB  15
#define csr_UctDatWriteOnly_LSB  0
#define csr_UctDatWriteOnly_MASK 0xffff
#define csr_UctDatWriteOnlyShadow_RANGE  15:0
#define csr_UctDatWriteOnlyShadow_BITS   15:0
#define csr_UctDatWriteOnlyShadow_MSB  15
#define csr_UctDatWriteOnlyShadow_LSB  0
#define csr_UctDatWriteOnlyShadow_MASK 0xffff
#define csr_HwtSwizzleHwtBank2_RANGE  4:0
#define csr_HwtSwizzleHwtBank2_BITS   4:0
#define csr_HwtSwizzleHwtBank2_MSB  4
#define csr_HwtSwizzleHwtBank2_LSB  0
#define csr_HwtSwizzleHwtBank2_MASK 0x1f
#define csr_Db5LcdlCalPhDetOut_RANGE  15:0
#define csr_Db5LcdlCalPhDetOut_BITS   15:0
#define csr_Db5LcdlCalPhDetOut_MSB  15
#define csr_Db5LcdlCalPhDetOut_LSB  0
#define csr_Db5LcdlCalPhDetOut_MASK 0xffff
#define csr_GenPrbsByte5_RANGE  15:0
#define csr_GenPrbsByte5_BITS   15:0
#define csr_GenPrbsByte5_MSB  15
#define csr_GenPrbsByte5_LSB  0
#define csr_GenPrbsByte5_MASK 0xffff
#define csr_SequenceReg0b4s0_RANGE  15:0
#define csr_SequenceReg0b4s0_BITS   15:0
#define csr_SequenceReg0b4s0_MSB  15
#define csr_SequenceReg0b4s0_LSB  0
#define csr_SequenceReg0b4s0_MASK 0xffff
#define csr_SequenceReg0b89s1_RANGE  15:0
#define csr_SequenceReg0b89s1_BITS   15:0
#define csr_SequenceReg0b89s1_MSB  15
#define csr_SequenceReg0b89s1_LSB  0
#define csr_SequenceReg0b89s1_MASK 0xffff
#define csr_AcsmSeq1x21_RANGE  15:0
#define csr_AcsmSeq1x21_BITS   15:0
#define csr_AcsmSeq1x21_MSB  15
#define csr_AcsmSeq1x21_LSB  0
#define csr_AcsmSeq1x21_MASK 0xffff
#define csr_AcsmDdrCs21_RANGE  7:0
#define csr_AcsmDdrCs21_BITS   7:0
#define csr_AcsmDdrCs21_MSB  7
#define csr_AcsmDdrCs21_LSB  0
#define csr_AcsmDdrCs21_MASK 0xff
#define csr_AcsmSaveGen21_RANGE  8:8
#define csr_AcsmSaveGen21_BITS   0:0
#define csr_AcsmSaveGen21_MSB  8
#define csr_AcsmSaveGen21_LSB  8
#define csr_AcsmSaveGen21_MASK 0x100
#define csr_AcsmLoadChk21_RANGE  9:9
#define csr_AcsmLoadChk21_BITS   0:0
#define csr_AcsmLoadChk21_MSB  9
#define csr_AcsmLoadChk21_LSB  9
#define csr_AcsmLoadChk21_MASK 0x200
#define csr_AcsmNoRxEnb21_RANGE  10:10
#define csr_AcsmNoRxEnb21_BITS   0:0
#define csr_AcsmNoRxEnb21_MSB  10
#define csr_AcsmNoRxEnb21_LSB  10
#define csr_AcsmNoRxEnb21_MASK 0x400
#define csr_AcsmNoRxVal21_RANGE  11:11
#define csr_AcsmNoRxVal21_BITS   0:0
#define csr_AcsmNoRxVal21_MSB  11
#define csr_AcsmNoRxVal21_LSB  11
#define csr_AcsmNoRxVal21_MASK 0x800
#define csr_AcsmDdrBnk21_RANGE  15:12
#define csr_AcsmDdrBnk21_BITS   3:0
#define csr_AcsmDdrBnk21_MSB  15
#define csr_AcsmDdrBnk21_LSB  12
#define csr_AcsmDdrBnk21_MASK 0xf000
#define csr_NeverGateCsrClock_RANGE  0:0
#define csr_NeverGateCsrClock_BITS   0:0
#define csr_NeverGateCsrClock_MSB  0
#define csr_NeverGateCsrClock_LSB  0
#define csr_NeverGateCsrClock_MASK 0x1
#define csr_UctDatWriteProt_RANGE  0:0
#define csr_UctDatWriteProt_BITS   0:0
#define csr_UctDatWriteProt_MSB  0
#define csr_UctDatWriteProt_LSB  0
#define csr_UctDatWriteProt_MASK 0x1
#define csr_HwtSwizzleHwtBg0_RANGE  4:0
#define csr_HwtSwizzleHwtBg0_BITS   4:0
#define csr_HwtSwizzleHwtBg0_MSB  4
#define csr_HwtSwizzleHwtBg0_LSB  0
#define csr_HwtSwizzleHwtBg0_MASK 0x1f
#define csr_Db6LcdlCalPhDetOut_RANGE  15:0
#define csr_Db6LcdlCalPhDetOut_BITS   15:0
#define csr_Db6LcdlCalPhDetOut_MSB  15
#define csr_Db6LcdlCalPhDetOut_LSB  0
#define csr_Db6LcdlCalPhDetOut_MASK 0xffff
#define csr_GenPrbsByte6_RANGE  15:0
#define csr_GenPrbsByte6_BITS   15:0
#define csr_GenPrbsByte6_MSB  15
#define csr_GenPrbsByte6_LSB  0
#define csr_GenPrbsByte6_MASK 0xffff
#define csr_SequenceReg0b4s1_RANGE  15:0
#define csr_SequenceReg0b4s1_BITS   15:0
#define csr_SequenceReg0b4s1_MSB  15
#define csr_SequenceReg0b4s1_LSB  0
#define csr_SequenceReg0b4s1_MASK 0xffff
#define csr_SequenceReg0b89s2_RANGE  8:0
#define csr_SequenceReg0b89s2_BITS   8:0
#define csr_SequenceReg0b89s2_MSB  8
#define csr_SequenceReg0b89s2_LSB  0
#define csr_SequenceReg0b89s2_MASK 0x1ff
#define csr_AcsmSeq1x22_RANGE  15:0
#define csr_AcsmSeq1x22_BITS   15:0
#define csr_AcsmSeq1x22_MSB  15
#define csr_AcsmSeq1x22_LSB  0
#define csr_AcsmSeq1x22_MASK 0xffff
#define csr_AcsmDdrCs22_RANGE  7:0
#define csr_AcsmDdrCs22_BITS   7:0
#define csr_AcsmDdrCs22_MSB  7
#define csr_AcsmDdrCs22_LSB  0
#define csr_AcsmDdrCs22_MASK 0xff
#define csr_AcsmSaveGen22_RANGE  8:8
#define csr_AcsmSaveGen22_BITS   0:0
#define csr_AcsmSaveGen22_MSB  8
#define csr_AcsmSaveGen22_LSB  8
#define csr_AcsmSaveGen22_MASK 0x100
#define csr_AcsmLoadChk22_RANGE  9:9
#define csr_AcsmLoadChk22_BITS   0:0
#define csr_AcsmLoadChk22_MSB  9
#define csr_AcsmLoadChk22_LSB  9
#define csr_AcsmLoadChk22_MASK 0x200
#define csr_AcsmNoRxEnb22_RANGE  10:10
#define csr_AcsmNoRxEnb22_BITS   0:0
#define csr_AcsmNoRxEnb22_MSB  10
#define csr_AcsmNoRxEnb22_LSB  10
#define csr_AcsmNoRxEnb22_MASK 0x400
#define csr_AcsmNoRxVal22_RANGE  11:11
#define csr_AcsmNoRxVal22_BITS   0:0
#define csr_AcsmNoRxVal22_MSB  11
#define csr_AcsmNoRxVal22_LSB  11
#define csr_AcsmNoRxVal22_MASK 0x800
#define csr_AcsmDdrBnk22_RANGE  15:12
#define csr_AcsmDdrBnk22_BITS   3:0
#define csr_AcsmDdrBnk22_MSB  15
#define csr_AcsmDdrBnk22_LSB  12
#define csr_AcsmDdrBnk22_MASK 0xf000
#define csr_UctlErr_RANGE  0:0
#define csr_UctlErr_BITS   0:0
#define csr_UctlErr_MSB  0
#define csr_UctlErr_LSB  0
#define csr_UctlErr_MASK 0x1
#define csr_HwtSwizzleHwtBg1_RANGE  4:0
#define csr_HwtSwizzleHwtBg1_BITS   4:0
#define csr_HwtSwizzleHwtBg1_MSB  4
#define csr_HwtSwizzleHwtBg1_LSB  0
#define csr_HwtSwizzleHwtBg1_MASK 0x1f
#define csr_Db7LcdlCalPhDetOut_RANGE  15:0
#define csr_Db7LcdlCalPhDetOut_BITS   15:0
#define csr_Db7LcdlCalPhDetOut_MSB  15
#define csr_Db7LcdlCalPhDetOut_LSB  0
#define csr_Db7LcdlCalPhDetOut_MASK 0xffff
#define csr_GenPrbsByte7_RANGE  15:0
#define csr_GenPrbsByte7_BITS   15:0
#define csr_GenPrbsByte7_MSB  15
#define csr_GenPrbsByte7_LSB  0
#define csr_GenPrbsByte7_MASK 0xffff
#define csr_SequenceReg0b4s2_RANGE  8:0
#define csr_SequenceReg0b4s2_BITS   8:0
#define csr_SequenceReg0b4s2_MSB  8
#define csr_SequenceReg0b4s2_LSB  0
#define csr_SequenceReg0b4s2_MASK 0x1ff
#define csr_SequenceReg0b90s0_RANGE  15:0
#define csr_SequenceReg0b90s0_BITS   15:0
#define csr_SequenceReg0b90s0_MSB  15
#define csr_SequenceReg0b90s0_LSB  0
#define csr_SequenceReg0b90s0_MASK 0xffff
#define csr_AcsmSeq1x23_RANGE  15:0
#define csr_AcsmSeq1x23_BITS   15:0
#define csr_AcsmSeq1x23_MSB  15
#define csr_AcsmSeq1x23_LSB  0
#define csr_AcsmSeq1x23_MASK 0xffff
#define csr_AcsmDdrCs23_RANGE  7:0
#define csr_AcsmDdrCs23_BITS   7:0
#define csr_AcsmDdrCs23_MSB  7
#define csr_AcsmDdrCs23_LSB  0
#define csr_AcsmDdrCs23_MASK 0xff
#define csr_AcsmSaveGen23_RANGE  8:8
#define csr_AcsmSaveGen23_BITS   0:0
#define csr_AcsmSaveGen23_MSB  8
#define csr_AcsmSaveGen23_LSB  8
#define csr_AcsmSaveGen23_MASK 0x100
#define csr_AcsmLoadChk23_RANGE  9:9
#define csr_AcsmLoadChk23_BITS   0:0
#define csr_AcsmLoadChk23_MSB  9
#define csr_AcsmLoadChk23_LSB  9
#define csr_AcsmLoadChk23_MASK 0x200
#define csr_AcsmNoRxEnb23_RANGE  10:10
#define csr_AcsmNoRxEnb23_BITS   0:0
#define csr_AcsmNoRxEnb23_MSB  10
#define csr_AcsmNoRxEnb23_LSB  10
#define csr_AcsmNoRxEnb23_MASK 0x400
#define csr_AcsmNoRxVal23_RANGE  11:11
#define csr_AcsmNoRxVal23_BITS   0:0
#define csr_AcsmNoRxVal23_MSB  11
#define csr_AcsmNoRxVal23_LSB  11
#define csr_AcsmNoRxVal23_MASK 0x800
#define csr_AcsmDdrBnk23_RANGE  15:12
#define csr_AcsmDdrBnk23_BITS   3:0
#define csr_AcsmDdrBnk23_MSB  15
#define csr_AcsmDdrBnk23_LSB  12
#define csr_AcsmDdrBnk23_MASK 0xf000
#define csr_DfiCfgRdDataValidTicks_RANGE  5:0
#define csr_DfiCfgRdDataValidTicks_BITS   5:0
#define csr_DfiCfgRdDataValidTicks_MSB  5
#define csr_DfiCfgRdDataValidTicks_LSB  0
#define csr_DfiCfgRdDataValidTicks_MASK 0x3f
#define csr_HwtSwizzleHwtCasN_RANGE  4:0
#define csr_HwtSwizzleHwtCasN_BITS   4:0
#define csr_HwtSwizzleHwtCasN_MSB  4
#define csr_HwtSwizzleHwtCasN_LSB  0
#define csr_HwtSwizzleHwtCasN_MASK 0x1f
#define csr_Db8LcdlCalPhDetOut_RANGE  15:0
#define csr_Db8LcdlCalPhDetOut_BITS   15:0
#define csr_Db8LcdlCalPhDetOut_MSB  15
#define csr_Db8LcdlCalPhDetOut_LSB  0
#define csr_Db8LcdlCalPhDetOut_MASK 0xffff
#define csr_GenPrbsByte8_RANGE  15:0
#define csr_GenPrbsByte8_BITS   15:0
#define csr_GenPrbsByte8_MSB  15
#define csr_GenPrbsByte8_LSB  0
#define csr_GenPrbsByte8_MASK 0xffff
#define csr_SequenceReg0b5s0_RANGE  15:0
#define csr_SequenceReg0b5s0_BITS   15:0
#define csr_SequenceReg0b5s0_MSB  15
#define csr_SequenceReg0b5s0_LSB  0
#define csr_SequenceReg0b5s0_MASK 0xffff
#define csr_SequenceReg0b90s1_RANGE  15:0
#define csr_SequenceReg0b90s1_BITS   15:0
#define csr_SequenceReg0b90s1_MSB  15
#define csr_SequenceReg0b90s1_LSB  0
#define csr_SequenceReg0b90s1_MASK 0xffff
#define csr_AcsmSeq1x24_RANGE  15:0
#define csr_AcsmSeq1x24_BITS   15:0
#define csr_AcsmSeq1x24_MSB  15
#define csr_AcsmSeq1x24_LSB  0
#define csr_AcsmSeq1x24_MASK 0xffff
#define csr_AcsmDdrCs24_RANGE  7:0
#define csr_AcsmDdrCs24_BITS   7:0
#define csr_AcsmDdrCs24_MSB  7
#define csr_AcsmDdrCs24_LSB  0
#define csr_AcsmDdrCs24_MASK 0xff
#define csr_AcsmSaveGen24_RANGE  8:8
#define csr_AcsmSaveGen24_BITS   0:0
#define csr_AcsmSaveGen24_MSB  8
#define csr_AcsmSaveGen24_LSB  8
#define csr_AcsmSaveGen24_MASK 0x100
#define csr_AcsmLoadChk24_RANGE  9:9
#define csr_AcsmLoadChk24_BITS   0:0
#define csr_AcsmLoadChk24_MSB  9
#define csr_AcsmLoadChk24_LSB  9
#define csr_AcsmLoadChk24_MASK 0x200
#define csr_AcsmNoRxEnb24_RANGE  10:10
#define csr_AcsmNoRxEnb24_BITS   0:0
#define csr_AcsmNoRxEnb24_MSB  10
#define csr_AcsmNoRxEnb24_LSB  10
#define csr_AcsmNoRxEnb24_MASK 0x400
#define csr_AcsmNoRxVal24_RANGE  11:11
#define csr_AcsmNoRxVal24_BITS   0:0
#define csr_AcsmNoRxVal24_MSB  11
#define csr_AcsmNoRxVal24_LSB  11
#define csr_AcsmNoRxVal24_MASK 0x800
#define csr_AcsmDdrBnk24_RANGE  15:12
#define csr_AcsmDdrBnk24_BITS   3:0
#define csr_AcsmDdrBnk24_MSB  15
#define csr_AcsmDdrBnk24_LSB  12
#define csr_AcsmDdrBnk24_MASK 0xf000
#define csr_HwtSwizzleHwtRasN_RANGE  4:0
#define csr_HwtSwizzleHwtRasN_BITS   4:0
#define csr_HwtSwizzleHwtRasN_MSB  4
#define csr_HwtSwizzleHwtRasN_LSB  0
#define csr_HwtSwizzleHwtRasN_MASK 0x1f
#define csr_Db9LcdlCalPhDetOut_RANGE  15:0
#define csr_Db9LcdlCalPhDetOut_BITS   15:0
#define csr_Db9LcdlCalPhDetOut_MSB  15
#define csr_Db9LcdlCalPhDetOut_LSB  0
#define csr_Db9LcdlCalPhDetOut_MASK 0xffff
#define csr_GenPrbsByte9_RANGE  15:0
#define csr_GenPrbsByte9_BITS   15:0
#define csr_GenPrbsByte9_MSB  15
#define csr_GenPrbsByte9_LSB  0
#define csr_GenPrbsByte9_MASK 0xffff
#define csr_SequenceReg0b5s1_RANGE  15:0
#define csr_SequenceReg0b5s1_BITS   15:0
#define csr_SequenceReg0b5s1_MSB  15
#define csr_SequenceReg0b5s1_LSB  0
#define csr_SequenceReg0b5s1_MASK 0xffff
#define csr_SequenceReg0b90s2_RANGE  8:0
#define csr_SequenceReg0b90s2_BITS   8:0
#define csr_SequenceReg0b90s2_MSB  8
#define csr_SequenceReg0b90s2_LSB  0
#define csr_SequenceReg0b90s2_MASK 0x1ff
#define csr_AcsmSeq1x25_RANGE  15:0
#define csr_AcsmSeq1x25_BITS   15:0
#define csr_AcsmSeq1x25_MSB  15
#define csr_AcsmSeq1x25_LSB  0
#define csr_AcsmSeq1x25_MASK 0xffff
#define csr_AcsmDdrCs25_RANGE  7:0
#define csr_AcsmDdrCs25_BITS   7:0
#define csr_AcsmDdrCs25_MSB  7
#define csr_AcsmDdrCs25_LSB  0
#define csr_AcsmDdrCs25_MASK 0xff
#define csr_AcsmSaveGen25_RANGE  8:8
#define csr_AcsmSaveGen25_BITS   0:0
#define csr_AcsmSaveGen25_MSB  8
#define csr_AcsmSaveGen25_LSB  8
#define csr_AcsmSaveGen25_MASK 0x100
#define csr_AcsmLoadChk25_RANGE  9:9
#define csr_AcsmLoadChk25_BITS   0:0
#define csr_AcsmLoadChk25_MSB  9
#define csr_AcsmLoadChk25_LSB  9
#define csr_AcsmLoadChk25_MASK 0x200
#define csr_AcsmNoRxEnb25_RANGE  10:10
#define csr_AcsmNoRxEnb25_BITS   0:0
#define csr_AcsmNoRxEnb25_MSB  10
#define csr_AcsmNoRxEnb25_LSB  10
#define csr_AcsmNoRxEnb25_MASK 0x400
#define csr_AcsmNoRxVal25_RANGE  11:11
#define csr_AcsmNoRxVal25_BITS   0:0
#define csr_AcsmNoRxVal25_MSB  11
#define csr_AcsmNoRxVal25_LSB  11
#define csr_AcsmNoRxVal25_MASK 0x800
#define csr_AcsmDdrBnk25_RANGE  15:12
#define csr_AcsmDdrBnk25_BITS   3:0
#define csr_AcsmDdrBnk25_MSB  15
#define csr_AcsmDdrBnk25_LSB  12
#define csr_AcsmDdrBnk25_MASK 0xf000
#define csr_HwtSwizzleHwtWeN_RANGE  4:0
#define csr_HwtSwizzleHwtWeN_BITS   4:0
#define csr_HwtSwizzleHwtWeN_MSB  4
#define csr_HwtSwizzleHwtWeN_LSB  0
#define csr_HwtSwizzleHwtWeN_MASK 0x1f
#define csr_GenPrbsByte10_RANGE  15:0
#define csr_GenPrbsByte10_BITS   15:0
#define csr_GenPrbsByte10_MSB  15
#define csr_GenPrbsByte10_LSB  0
#define csr_GenPrbsByte10_MASK 0xffff
#define csr_SequenceReg0b5s2_RANGE  8:0
#define csr_SequenceReg0b5s2_BITS   8:0
#define csr_SequenceReg0b5s2_MSB  8
#define csr_SequenceReg0b5s2_LSB  0
#define csr_SequenceReg0b5s2_MASK 0x1ff
#define csr_SequenceReg0b91s0_RANGE  15:0
#define csr_SequenceReg0b91s0_BITS   15:0
#define csr_SequenceReg0b91s0_MSB  15
#define csr_SequenceReg0b91s0_LSB  0
#define csr_SequenceReg0b91s0_MASK 0xffff
#define csr_AcsmSeq1x26_RANGE  15:0
#define csr_AcsmSeq1x26_BITS   15:0
#define csr_AcsmSeq1x26_MSB  15
#define csr_AcsmSeq1x26_LSB  0
#define csr_AcsmSeq1x26_MASK 0xffff
#define csr_AcsmDdrCs26_RANGE  7:0
#define csr_AcsmDdrCs26_BITS   7:0
#define csr_AcsmDdrCs26_MSB  7
#define csr_AcsmDdrCs26_LSB  0
#define csr_AcsmDdrCs26_MASK 0xff
#define csr_AcsmSaveGen26_RANGE  8:8
#define csr_AcsmSaveGen26_BITS   0:0
#define csr_AcsmSaveGen26_MSB  8
#define csr_AcsmSaveGen26_LSB  8
#define csr_AcsmSaveGen26_MASK 0x100
#define csr_AcsmLoadChk26_RANGE  9:9
#define csr_AcsmLoadChk26_BITS   0:0
#define csr_AcsmLoadChk26_MSB  9
#define csr_AcsmLoadChk26_LSB  9
#define csr_AcsmLoadChk26_MASK 0x200
#define csr_AcsmNoRxEnb26_RANGE  10:10
#define csr_AcsmNoRxEnb26_BITS   0:0
#define csr_AcsmNoRxEnb26_MSB  10
#define csr_AcsmNoRxEnb26_LSB  10
#define csr_AcsmNoRxEnb26_MASK 0x400
#define csr_AcsmNoRxVal26_RANGE  11:11
#define csr_AcsmNoRxVal26_BITS   0:0
#define csr_AcsmNoRxVal26_MSB  11
#define csr_AcsmNoRxVal26_LSB  11
#define csr_AcsmNoRxVal26_MASK 0x800
#define csr_AcsmDdrBnk26_RANGE  15:12
#define csr_AcsmDdrBnk26_BITS   3:0
#define csr_AcsmDdrBnk26_MSB  15
#define csr_AcsmDdrBnk26_LSB  12
#define csr_AcsmDdrBnk26_MASK 0xf000
#define csr_DbyteDllModeCntrl_RANGE  1:1
#define csr_DbyteDllModeCntrl_BITS   0:0
#define csr_DbyteDllModeCntrl_MSB  1
#define csr_DbyteDllModeCntrl_LSB  1
#define csr_DbyteDllModeCntrl_MASK 0x2
#define csr_DllRxPreambleMode_RANGE  1:1
#define csr_DllRxPreambleMode_BITS   0:0
#define csr_DllRxPreambleMode_MSB  1
#define csr_DllRxPreambleMode_LSB  1
#define csr_DllRxPreambleMode_MASK 0x2
#define csr_HwtSwizzleHwtParityIn_RANGE  4:0
#define csr_HwtSwizzleHwtParityIn_BITS   4:0
#define csr_HwtSwizzleHwtParityIn_MSB  4
#define csr_HwtSwizzleHwtParityIn_LSB  0
#define csr_HwtSwizzleHwtParityIn_MASK 0x1f
#define csr_GenPrbsByte11_RANGE  15:0
#define csr_GenPrbsByte11_BITS   15:0
#define csr_GenPrbsByte11_MSB  15
#define csr_GenPrbsByte11_LSB  0
#define csr_GenPrbsByte11_MASK 0xffff
#define csr_SequenceReg0b6s0_RANGE  15:0
#define csr_SequenceReg0b6s0_BITS   15:0
#define csr_SequenceReg0b6s0_MSB  15
#define csr_SequenceReg0b6s0_LSB  0
#define csr_SequenceReg0b6s0_MASK 0xffff
#define csr_SequenceReg0b91s1_RANGE  15:0
#define csr_SequenceReg0b91s1_BITS   15:0
#define csr_SequenceReg0b91s1_MSB  15
#define csr_SequenceReg0b91s1_LSB  0
#define csr_SequenceReg0b91s1_MASK 0xffff
#define csr_AcsmSeq1x27_RANGE  15:0
#define csr_AcsmSeq1x27_BITS   15:0
#define csr_AcsmSeq1x27_MSB  15
#define csr_AcsmSeq1x27_LSB  0
#define csr_AcsmSeq1x27_MASK 0xffff
#define csr_AcsmDdrCs27_RANGE  7:0
#define csr_AcsmDdrCs27_BITS   7:0
#define csr_AcsmDdrCs27_MSB  7
#define csr_AcsmDdrCs27_LSB  0
#define csr_AcsmDdrCs27_MASK 0xff
#define csr_AcsmSaveGen27_RANGE  8:8
#define csr_AcsmSaveGen27_BITS   0:0
#define csr_AcsmSaveGen27_MSB  8
#define csr_AcsmSaveGen27_LSB  8
#define csr_AcsmSaveGen27_MASK 0x100
#define csr_AcsmLoadChk27_RANGE  9:9
#define csr_AcsmLoadChk27_BITS   0:0
#define csr_AcsmLoadChk27_MSB  9
#define csr_AcsmLoadChk27_LSB  9
#define csr_AcsmLoadChk27_MASK 0x200
#define csr_AcsmNoRxEnb27_RANGE  10:10
#define csr_AcsmNoRxEnb27_BITS   0:0
#define csr_AcsmNoRxEnb27_MSB  10
#define csr_AcsmNoRxEnb27_LSB  10
#define csr_AcsmNoRxEnb27_MASK 0x400
#define csr_AcsmNoRxVal27_RANGE  11:11
#define csr_AcsmNoRxVal27_BITS   0:0
#define csr_AcsmNoRxVal27_MSB  11
#define csr_AcsmNoRxVal27_LSB  11
#define csr_AcsmNoRxVal27_MASK 0x800
#define csr_AcsmDdrBnk27_RANGE  15:12
#define csr_AcsmDdrBnk27_BITS   3:0
#define csr_AcsmDdrBnk27_MSB  15
#define csr_AcsmDdrBnk27_LSB  12
#define csr_AcsmDdrBnk27_MASK 0xf000
#define csr_DbyteRxEnTrain_RANGE  0:0
#define csr_DbyteRxEnTrain_BITS   0:0
#define csr_DbyteRxEnTrain_MSB  0
#define csr_DbyteRxEnTrain_LSB  0
#define csr_DbyteRxEnTrain_MASK 0x1
#define csr_RxEnTrain_RANGE  0:0
#define csr_RxEnTrain_BITS   0:0
#define csr_RxEnTrain_MSB  0
#define csr_RxEnTrain_LSB  0
#define csr_RxEnTrain_MASK 0x1
#define csr_GenPrbsByte12_RANGE  15:0
#define csr_GenPrbsByte12_BITS   15:0
#define csr_GenPrbsByte12_MSB  15
#define csr_GenPrbsByte12_LSB  0
#define csr_GenPrbsByte12_MASK 0xffff
#define csr_SequenceReg0b6s1_RANGE  15:0
#define csr_SequenceReg0b6s1_BITS   15:0
#define csr_SequenceReg0b6s1_MSB  15
#define csr_SequenceReg0b6s1_LSB  0
#define csr_SequenceReg0b6s1_MASK 0xffff
#define csr_SequenceReg0b91s2_RANGE  8:0
#define csr_SequenceReg0b91s2_BITS   8:0
#define csr_SequenceReg0b91s2_MSB  8
#define csr_SequenceReg0b91s2_LSB  0
#define csr_SequenceReg0b91s2_MASK 0x1ff
#define csr_AcsmSeq1x28_RANGE  15:0
#define csr_AcsmSeq1x28_BITS   15:0
#define csr_AcsmSeq1x28_MSB  15
#define csr_AcsmSeq1x28_LSB  0
#define csr_AcsmSeq1x28_MASK 0xffff
#define csr_AcsmDdrCs28_RANGE  7:0
#define csr_AcsmDdrCs28_BITS   7:0
#define csr_AcsmDdrCs28_MSB  7
#define csr_AcsmDdrCs28_LSB  0
#define csr_AcsmDdrCs28_MASK 0xff
#define csr_AcsmSaveGen28_RANGE  8:8
#define csr_AcsmSaveGen28_BITS   0:0
#define csr_AcsmSaveGen28_MSB  8
#define csr_AcsmSaveGen28_LSB  8
#define csr_AcsmSaveGen28_MASK 0x100
#define csr_AcsmLoadChk28_RANGE  9:9
#define csr_AcsmLoadChk28_BITS   0:0
#define csr_AcsmLoadChk28_MSB  9
#define csr_AcsmLoadChk28_LSB  9
#define csr_AcsmLoadChk28_MASK 0x200
#define csr_AcsmNoRxEnb28_RANGE  10:10
#define csr_AcsmNoRxEnb28_BITS   0:0
#define csr_AcsmNoRxEnb28_MSB  10
#define csr_AcsmNoRxEnb28_LSB  10
#define csr_AcsmNoRxEnb28_MASK 0x400
#define csr_AcsmNoRxVal28_RANGE  11:11
#define csr_AcsmNoRxVal28_BITS   0:0
#define csr_AcsmNoRxVal28_MSB  11
#define csr_AcsmNoRxVal28_LSB  11
#define csr_AcsmNoRxVal28_MASK 0x800
#define csr_AcsmDdrBnk28_RANGE  15:12
#define csr_AcsmDdrBnk28_BITS   3:0
#define csr_AcsmDdrBnk28_MSB  15
#define csr_AcsmDdrBnk28_LSB  12
#define csr_AcsmDdrBnk28_MASK 0xf000
#define csr_DfiHandshakeDelays0_RANGE  15:0
#define csr_DfiHandshakeDelays0_BITS   15:0
#define csr_DfiHandshakeDelays0_MSB  15
#define csr_DfiHandshakeDelays0_LSB  0
#define csr_DfiHandshakeDelays0_MASK 0xffff
#define csr_PhyUpdAckDelay0_RANGE  3:0
#define csr_PhyUpdAckDelay0_BITS   3:0
#define csr_PhyUpdAckDelay0_MSB  3
#define csr_PhyUpdAckDelay0_LSB  0
#define csr_PhyUpdAckDelay0_MASK 0xf
#define csr_PhyUpdReqDelay0_RANGE  7:4
#define csr_PhyUpdReqDelay0_BITS   3:0
#define csr_PhyUpdReqDelay0_MSB  7
#define csr_PhyUpdReqDelay0_LSB  4
#define csr_PhyUpdReqDelay0_MASK 0xf0
#define csr_CtrlUpdAckDelay0_RANGE  11:8
#define csr_CtrlUpdAckDelay0_BITS   3:0
#define csr_CtrlUpdAckDelay0_MSB  11
#define csr_CtrlUpdAckDelay0_LSB  8
#define csr_CtrlUpdAckDelay0_MASK 0xf00
#define csr_CtrlUpdReqDelay0_RANGE  15:12
#define csr_CtrlUpdReqDelay0_BITS   3:0
#define csr_CtrlUpdReqDelay0_MSB  15
#define csr_CtrlUpdReqDelay0_LSB  12
#define csr_CtrlUpdReqDelay0_MASK 0xf000
#define csr_GenPrbsByte13_RANGE  15:0
#define csr_GenPrbsByte13_BITS   15:0
#define csr_GenPrbsByte13_MSB  15
#define csr_GenPrbsByte13_LSB  0
#define csr_GenPrbsByte13_MASK 0xffff
#define csr_SequenceReg0b6s2_RANGE  8:0
#define csr_SequenceReg0b6s2_BITS   8:0
#define csr_SequenceReg0b6s2_MSB  8
#define csr_SequenceReg0b6s2_LSB  0
#define csr_SequenceReg0b6s2_MASK 0x1ff
#define csr_SequenceReg0b92s0_RANGE  15:0
#define csr_SequenceReg0b92s0_BITS   15:0
#define csr_SequenceReg0b92s0_MSB  15
#define csr_SequenceReg0b92s0_LSB  0
#define csr_SequenceReg0b92s0_MASK 0xffff
#define csr_AcsmSeq1x29_RANGE  15:0
#define csr_AcsmSeq1x29_BITS   15:0
#define csr_AcsmSeq1x29_MSB  15
#define csr_AcsmSeq1x29_LSB  0
#define csr_AcsmSeq1x29_MASK 0xffff
#define csr_AcsmDdrCs29_RANGE  7:0
#define csr_AcsmDdrCs29_BITS   7:0
#define csr_AcsmDdrCs29_MSB  7
#define csr_AcsmDdrCs29_LSB  0
#define csr_AcsmDdrCs29_MASK 0xff
#define csr_AcsmSaveGen29_RANGE  8:8
#define csr_AcsmSaveGen29_BITS   0:0
#define csr_AcsmSaveGen29_MSB  8
#define csr_AcsmSaveGen29_LSB  8
#define csr_AcsmSaveGen29_MASK 0x100
#define csr_AcsmLoadChk29_RANGE  9:9
#define csr_AcsmLoadChk29_BITS   0:0
#define csr_AcsmLoadChk29_MSB  9
#define csr_AcsmLoadChk29_LSB  9
#define csr_AcsmLoadChk29_MASK 0x200
#define csr_AcsmNoRxEnb29_RANGE  10:10
#define csr_AcsmNoRxEnb29_BITS   0:0
#define csr_AcsmNoRxEnb29_MSB  10
#define csr_AcsmNoRxEnb29_LSB  10
#define csr_AcsmNoRxEnb29_MASK 0x400
#define csr_AcsmNoRxVal29_RANGE  11:11
#define csr_AcsmNoRxVal29_BITS   0:0
#define csr_AcsmNoRxVal29_MSB  11
#define csr_AcsmNoRxVal29_LSB  11
#define csr_AcsmNoRxVal29_MASK 0x800
#define csr_AcsmDdrBnk29_RANGE  15:12
#define csr_AcsmDdrBnk29_BITS   3:0
#define csr_AcsmDdrBnk29_MSB  15
#define csr_AcsmDdrBnk29_LSB  12
#define csr_AcsmDdrBnk29_MASK 0xf000
#define csr_DfiHandshakeDelays1_RANGE  15:0
#define csr_DfiHandshakeDelays1_BITS   15:0
#define csr_DfiHandshakeDelays1_MSB  15
#define csr_DfiHandshakeDelays1_LSB  0
#define csr_DfiHandshakeDelays1_MASK 0xffff
#define csr_PhyUpdAckDelay1_RANGE  3:0
#define csr_PhyUpdAckDelay1_BITS   3:0
#define csr_PhyUpdAckDelay1_MSB  3
#define csr_PhyUpdAckDelay1_LSB  0
#define csr_PhyUpdAckDelay1_MASK 0xf
#define csr_PhyUpdReqDelay1_RANGE  7:4
#define csr_PhyUpdReqDelay1_BITS   3:0
#define csr_PhyUpdReqDelay1_MSB  7
#define csr_PhyUpdReqDelay1_LSB  4
#define csr_PhyUpdReqDelay1_MASK 0xf0
#define csr_CtrlUpdAckDelay1_RANGE  11:8
#define csr_CtrlUpdAckDelay1_BITS   3:0
#define csr_CtrlUpdAckDelay1_MSB  11
#define csr_CtrlUpdAckDelay1_LSB  8
#define csr_CtrlUpdAckDelay1_MASK 0xf00
#define csr_CtrlUpdReqDelay1_RANGE  15:12
#define csr_CtrlUpdReqDelay1_BITS   3:0
#define csr_CtrlUpdReqDelay1_MSB  15
#define csr_CtrlUpdReqDelay1_LSB  12
#define csr_CtrlUpdReqDelay1_MASK 0xf000
#define csr_GenPrbsByte14_RANGE  15:0
#define csr_GenPrbsByte14_BITS   15:0
#define csr_GenPrbsByte14_MSB  15
#define csr_GenPrbsByte14_LSB  0
#define csr_GenPrbsByte14_MASK 0xffff
#define csr_SequenceReg0b7s0_RANGE  15:0
#define csr_SequenceReg0b7s0_BITS   15:0
#define csr_SequenceReg0b7s0_MSB  15
#define csr_SequenceReg0b7s0_LSB  0
#define csr_SequenceReg0b7s0_MASK 0xffff
#define csr_SequenceReg0b92s1_RANGE  15:0
#define csr_SequenceReg0b92s1_BITS   15:0
#define csr_SequenceReg0b92s1_MSB  15
#define csr_SequenceReg0b92s1_LSB  0
#define csr_SequenceReg0b92s1_MASK 0xffff
#define csr_AcsmSeq1x30_RANGE  15:0
#define csr_AcsmSeq1x30_BITS   15:0
#define csr_AcsmSeq1x30_MSB  15
#define csr_AcsmSeq1x30_LSB  0
#define csr_AcsmSeq1x30_MASK 0xffff
#define csr_AcsmDdrCs30_RANGE  7:0
#define csr_AcsmDdrCs30_BITS   7:0
#define csr_AcsmDdrCs30_MSB  7
#define csr_AcsmDdrCs30_LSB  0
#define csr_AcsmDdrCs30_MASK 0xff
#define csr_AcsmSaveGen30_RANGE  8:8
#define csr_AcsmSaveGen30_BITS   0:0
#define csr_AcsmSaveGen30_MSB  8
#define csr_AcsmSaveGen30_LSB  8
#define csr_AcsmSaveGen30_MASK 0x100
#define csr_AcsmLoadChk30_RANGE  9:9
#define csr_AcsmLoadChk30_BITS   0:0
#define csr_AcsmLoadChk30_MSB  9
#define csr_AcsmLoadChk30_LSB  9
#define csr_AcsmLoadChk30_MASK 0x200
#define csr_AcsmNoRxEnb30_RANGE  10:10
#define csr_AcsmNoRxEnb30_BITS   0:0
#define csr_AcsmNoRxEnb30_MSB  10
#define csr_AcsmNoRxEnb30_LSB  10
#define csr_AcsmNoRxEnb30_MASK 0x400
#define csr_AcsmNoRxVal30_RANGE  11:11
#define csr_AcsmNoRxVal30_BITS   0:0
#define csr_AcsmNoRxVal30_MSB  11
#define csr_AcsmNoRxVal30_LSB  11
#define csr_AcsmNoRxVal30_MASK 0x800
#define csr_AcsmDdrBnk30_RANGE  15:12
#define csr_AcsmDdrBnk30_BITS   3:0
#define csr_AcsmDdrBnk30_MSB  15
#define csr_AcsmDdrBnk30_LSB  12
#define csr_AcsmDdrBnk30_MASK 0xf000
#define csr_RemoteImpCal_RANGE  1:0
#define csr_RemoteImpCal_BITS   1:0
#define csr_RemoteImpCal_MSB  1
#define csr_RemoteImpCal_LSB  0
#define csr_RemoteImpCal_MASK 0x3
#define csr_CalibSlave_RANGE  0:0
#define csr_CalibSlave_BITS   0:0
#define csr_CalibSlave_MSB  0
#define csr_CalibSlave_LSB  0
#define csr_CalibSlave_MASK 0x1
#define csr_SlaveCodeUpdated_RANGE  1:1
#define csr_SlaveCodeUpdated_BITS   0:0
#define csr_SlaveCodeUpdated_MSB  1
#define csr_SlaveCodeUpdated_LSB  1
#define csr_SlaveCodeUpdated_MASK 0x2
#define csr_AnLcdlCalPhDetOut_RANGE  11:0
#define csr_AnLcdlCalPhDetOut_BITS   11:0
#define csr_AnLcdlCalPhDetOut_MSB  11
#define csr_AnLcdlCalPhDetOut_LSB  0
#define csr_AnLcdlCalPhDetOut_MASK 0xfff
#define csr_GenPrbsByte15_RANGE  15:0
#define csr_GenPrbsByte15_BITS   15:0
#define csr_GenPrbsByte15_MSB  15
#define csr_GenPrbsByte15_LSB  0
#define csr_GenPrbsByte15_MASK 0xffff
#define csr_SequenceReg0b7s1_RANGE  15:0
#define csr_SequenceReg0b7s1_BITS   15:0
#define csr_SequenceReg0b7s1_MSB  15
#define csr_SequenceReg0b7s1_LSB  0
#define csr_SequenceReg0b7s1_MASK 0xffff
#define csr_SequenceReg0b92s2_RANGE  8:0
#define csr_SequenceReg0b92s2_BITS   8:0
#define csr_SequenceReg0b92s2_MSB  8
#define csr_SequenceReg0b92s2_LSB  0
#define csr_SequenceReg0b92s2_MASK 0x1ff
#define csr_AcsmSeq1x31_RANGE  15:0
#define csr_AcsmSeq1x31_BITS   15:0
#define csr_AcsmSeq1x31_MSB  15
#define csr_AcsmSeq1x31_LSB  0
#define csr_AcsmSeq1x31_MASK 0xffff
#define csr_AcsmDdrCs31_RANGE  7:0
#define csr_AcsmDdrCs31_BITS   7:0
#define csr_AcsmDdrCs31_MSB  7
#define csr_AcsmDdrCs31_LSB  0
#define csr_AcsmDdrCs31_MASK 0xff
#define csr_AcsmSaveGen31_RANGE  8:8
#define csr_AcsmSaveGen31_BITS   0:0
#define csr_AcsmSaveGen31_MSB  8
#define csr_AcsmSaveGen31_LSB  8
#define csr_AcsmSaveGen31_MASK 0x100
#define csr_AcsmLoadChk31_RANGE  9:9
#define csr_AcsmLoadChk31_BITS   0:0
#define csr_AcsmLoadChk31_MSB  9
#define csr_AcsmLoadChk31_LSB  9
#define csr_AcsmLoadChk31_MASK 0x200
#define csr_AcsmNoRxEnb31_RANGE  10:10
#define csr_AcsmNoRxEnb31_BITS   0:0
#define csr_AcsmNoRxEnb31_MSB  10
#define csr_AcsmNoRxEnb31_LSB  10
#define csr_AcsmNoRxEnb31_MASK 0x400
#define csr_AcsmNoRxVal31_RANGE  11:11
#define csr_AcsmNoRxVal31_BITS   0:0
#define csr_AcsmNoRxVal31_MSB  11
#define csr_AcsmNoRxVal31_LSB  11
#define csr_AcsmNoRxVal31_MASK 0x800
#define csr_AcsmDdrBnk31_RANGE  15:12
#define csr_AcsmDdrBnk31_BITS   3:0
#define csr_AcsmDdrBnk31_MSB  15
#define csr_AcsmDdrBnk31_LSB  12
#define csr_AcsmDdrBnk31_MASK 0xf000
#define csr_ACLoopbackCtl_RANGE  1:0
#define csr_ACLoopbackCtl_BITS   1:0
#define csr_ACLoopbackCtl_MSB  1
#define csr_ACLoopbackCtl_LSB  0
#define csr_ACLoopbackCtl_MASK 0x3
#define csr_Termination_RANGE  0:0
#define csr_Termination_BITS   0:0
#define csr_Termination_MSB  0
#define csr_Termination_LSB  0
#define csr_Termination_MASK 0x1
#define csr_NoiseCancel_RANGE  1:1
#define csr_NoiseCancel_BITS   0:0
#define csr_NoiseCancel_MSB  1
#define csr_NoiseCancel_LSB  1
#define csr_NoiseCancel_MASK 0x2
#define csr_SequenceReg0b7s2_RANGE  8:0
#define csr_SequenceReg0b7s2_BITS   8:0
#define csr_SequenceReg0b7s2_MSB  8
#define csr_SequenceReg0b7s2_LSB  0
#define csr_SequenceReg0b7s2_MASK 0x1ff
#define csr_SequenceReg0b93s0_RANGE  15:0
#define csr_SequenceReg0b93s0_BITS   15:0
#define csr_SequenceReg0b93s0_MSB  15
#define csr_SequenceReg0b93s0_LSB  0
#define csr_SequenceReg0b93s0_MASK 0xffff
#define csr_AcsmSeq2x0_RANGE  15:0
#define csr_AcsmSeq2x0_BITS   15:0
#define csr_AcsmSeq2x0_MSB  15
#define csr_AcsmSeq2x0_LSB  0
#define csr_AcsmSeq2x0_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x0_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x0_BITS   15:0
#define csr_AcsmDdrAdrx15x0x0_MSB  15
#define csr_AcsmDdrAdrx15x0x0_LSB  0
#define csr_AcsmDdrAdrx15x0x0_MASK 0xffff
#define csr_VrefDAC0_RANGE  6:0
#define csr_VrefDAC0_BITS   6:0
#define csr_VrefDAC0_MSB  6
#define csr_VrefDAC0_LSB  0
#define csr_VrefDAC0_MASK 0x7f
#define csr_SequenceReg0b8s0_RANGE  15:0
#define csr_SequenceReg0b8s0_BITS   15:0
#define csr_SequenceReg0b8s0_MSB  15
#define csr_SequenceReg0b8s0_LSB  0
#define csr_SequenceReg0b8s0_MASK 0xffff
#define csr_SequenceReg0b93s1_RANGE  15:0
#define csr_SequenceReg0b93s1_BITS   15:0
#define csr_SequenceReg0b93s1_MSB  15
#define csr_SequenceReg0b93s1_LSB  0
#define csr_SequenceReg0b93s1_MASK 0xffff
#define csr_AcsmSeq2x1_RANGE  15:0
#define csr_AcsmSeq2x1_BITS   15:0
#define csr_AcsmSeq2x1_MSB  15
#define csr_AcsmSeq2x1_LSB  0
#define csr_AcsmSeq2x1_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x1_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x1_BITS   15:0
#define csr_AcsmDdrAdrx15x0x1_MSB  15
#define csr_AcsmDdrAdrx15x0x1_LSB  0
#define csr_AcsmDdrAdrx15x0x1_MASK 0xffff
#define csr_TxImpedanceCtrl0_RANGE  11:0
#define csr_TxImpedanceCtrl0_BITS   11:0
#define csr_TxImpedanceCtrl0_MSB  11
#define csr_TxImpedanceCtrl0_LSB  0
#define csr_TxImpedanceCtrl0_MASK 0xfff
#define csr_DrvStrenDqP_RANGE  5:0
#define csr_DrvStrenDqP_BITS   5:0
#define csr_DrvStrenDqP_MSB  5
#define csr_DrvStrenDqP_LSB  0
#define csr_DrvStrenDqP_MASK 0x3f
#define csr_DrvStrenDqN_RANGE  11:6
#define csr_DrvStrenDqN_BITS   5:0
#define csr_DrvStrenDqN_MSB  11
#define csr_DrvStrenDqN_LSB  6
#define csr_DrvStrenDqN_MASK 0xfc0
#define csr_SequenceReg0b8s1_RANGE  15:0
#define csr_SequenceReg0b8s1_BITS   15:0
#define csr_SequenceReg0b8s1_MSB  15
#define csr_SequenceReg0b8s1_LSB  0
#define csr_SequenceReg0b8s1_MASK 0xffff
#define csr_SequenceReg0b93s2_RANGE  8:0
#define csr_SequenceReg0b93s2_BITS   8:0
#define csr_SequenceReg0b93s2_MSB  8
#define csr_SequenceReg0b93s2_LSB  0
#define csr_SequenceReg0b93s2_MASK 0x1ff
#define csr_AcsmSeq2x2_RANGE  15:0
#define csr_AcsmSeq2x2_BITS   15:0
#define csr_AcsmSeq2x2_MSB  15
#define csr_AcsmSeq2x2_LSB  0
#define csr_AcsmSeq2x2_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x2_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x2_BITS   15:0
#define csr_AcsmDdrAdrx15x0x2_MSB  15
#define csr_AcsmDdrAdrx15x0x2_LSB  0
#define csr_AcsmDdrAdrx15x0x2_MASK 0xffff
#define csr_SequenceReg0b8s2_RANGE  8:0
#define csr_SequenceReg0b8s2_BITS   8:0
#define csr_SequenceReg0b8s2_MSB  8
#define csr_SequenceReg0b8s2_LSB  0
#define csr_SequenceReg0b8s2_MASK 0x1ff
#define csr_SequenceReg0b94s0_RANGE  15:0
#define csr_SequenceReg0b94s0_BITS   15:0
#define csr_SequenceReg0b94s0_MSB  15
#define csr_SequenceReg0b94s0_LSB  0
#define csr_SequenceReg0b94s0_MASK 0xffff
#define csr_AcsmSeq2x3_RANGE  15:0
#define csr_AcsmSeq2x3_BITS   15:0
#define csr_AcsmSeq2x3_MSB  15
#define csr_AcsmSeq2x3_LSB  0
#define csr_AcsmSeq2x3_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x3_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x3_BITS   15:0
#define csr_AcsmDdrAdrx15x0x3_MSB  15
#define csr_AcsmDdrAdrx15x0x3_LSB  0
#define csr_AcsmDdrAdrx15x0x3_MASK 0xffff
#define csr_ATxImpedance_RANGE  9:0
#define csr_ATxImpedance_BITS   9:0
#define csr_ATxImpedance_MSB  9
#define csr_ATxImpedance_LSB  0
#define csr_ATxImpedance_MASK 0x3ff
#define csr_ADrvStrenP_RANGE  4:0
#define csr_ADrvStrenP_BITS   4:0
#define csr_ADrvStrenP_MSB  4
#define csr_ADrvStrenP_LSB  0
#define csr_ADrvStrenP_MASK 0x1f
#define csr_ADrvStrenN_RANGE  9:5
#define csr_ADrvStrenN_BITS   4:0
#define csr_ADrvStrenN_MSB  9
#define csr_ADrvStrenN_LSB  5
#define csr_ADrvStrenN_MASK 0x3e0
#define csr_DqDqsRcvCntrl_RANGE  15:0
#define csr_DqDqsRcvCntrl_BITS   15:0
#define csr_DqDqsRcvCntrl_MSB  15
#define csr_DqDqsRcvCntrl_LSB  0
#define csr_DqDqsRcvCntrl_MASK 0xffff
#define csr_SelAnalogVref_RANGE  0:0
#define csr_SelAnalogVref_BITS   0:0
#define csr_SelAnalogVref_MSB  0
#define csr_SelAnalogVref_LSB  0
#define csr_SelAnalogVref_MASK 0x1
#define csr_ExtVrefRange_RANGE  1:1
#define csr_ExtVrefRange_BITS   0:0
#define csr_ExtVrefRange_MSB  1
#define csr_ExtVrefRange_LSB  1
#define csr_ExtVrefRange_MASK 0x2
#define csr_DfeCtrl_RANGE  3:2
#define csr_DfeCtrl_BITS   1:0
#define csr_DfeCtrl_MSB  3
#define csr_DfeCtrl_LSB  2
#define csr_DfeCtrl_MASK 0xc
#define csr_MajorModeDbyte_RANGE  6:4
#define csr_MajorModeDbyte_BITS   2:0
#define csr_MajorModeDbyte_MSB  6
#define csr_MajorModeDbyte_LSB  4
#define csr_MajorModeDbyte_MASK 0x70
#define csr_GainCurrAdj_RANGE  11:7
#define csr_GainCurrAdj_BITS   4:0
#define csr_GainCurrAdj_MSB  11
#define csr_GainCurrAdj_LSB  7
#define csr_GainCurrAdj_MASK 0xf80
#define csr_Reserved_RANGE  15:12
#define csr_Reserved_BITS   3:0
#define csr_Reserved_MSB  15
#define csr_Reserved_LSB  12
#define csr_Reserved_MASK 0xf000
#define csr_SequenceReg0b9s0_RANGE  15:0
#define csr_SequenceReg0b9s0_BITS   15:0
#define csr_SequenceReg0b9s0_MSB  15
#define csr_SequenceReg0b9s0_LSB  0
#define csr_SequenceReg0b9s0_MASK 0xffff
#define csr_SequenceReg0b94s1_RANGE  15:0
#define csr_SequenceReg0b94s1_BITS   15:0
#define csr_SequenceReg0b94s1_MSB  15
#define csr_SequenceReg0b94s1_LSB  0
#define csr_SequenceReg0b94s1_MASK 0xffff
#define csr_AcsmSeq2x4_RANGE  15:0
#define csr_AcsmSeq2x4_BITS   15:0
#define csr_AcsmSeq2x4_MSB  15
#define csr_AcsmSeq2x4_LSB  0
#define csr_AcsmSeq2x4_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x4_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x4_BITS   15:0
#define csr_AcsmDdrAdrx15x0x4_MSB  15
#define csr_AcsmDdrAdrx15x0x4_LSB  0
#define csr_AcsmDdrAdrx15x0x4_MASK 0xffff
#define csr_SequenceReg0b9s1_RANGE  15:0
#define csr_SequenceReg0b9s1_BITS   15:0
#define csr_SequenceReg0b9s1_MSB  15
#define csr_SequenceReg0b9s1_LSB  0
#define csr_SequenceReg0b9s1_MASK 0xffff
#define csr_SequenceReg0b94s2_RANGE  8:0
#define csr_SequenceReg0b94s2_BITS   8:0
#define csr_SequenceReg0b94s2_MSB  8
#define csr_SequenceReg0b94s2_LSB  0
#define csr_SequenceReg0b94s2_MASK 0x1ff
#define csr_AcsmSeq2x5_RANGE  15:0
#define csr_AcsmSeq2x5_BITS   15:0
#define csr_AcsmSeq2x5_MSB  15
#define csr_AcsmSeq2x5_LSB  0
#define csr_AcsmSeq2x5_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x5_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x5_BITS   15:0
#define csr_AcsmDdrAdrx15x0x5_MSB  15
#define csr_AcsmDdrAdrx15x0x5_LSB  0
#define csr_AcsmDdrAdrx15x0x5_MASK 0xffff
#define csr_CalOffsets_RANGE  13:0
#define csr_CalOffsets_BITS   13:0
#define csr_CalOffsets_MSB  13
#define csr_CalOffsets_LSB  0
#define csr_CalOffsets_MASK 0x3fff
#define csr_CalCmpr5Offset_RANGE  5:0
#define csr_CalCmpr5Offset_BITS   5:0
#define csr_CalCmpr5Offset_MSB  5
#define csr_CalCmpr5Offset_LSB  0
#define csr_CalCmpr5Offset_MASK 0x3f
#define csr_CalDrvPdThOffset_RANGE  9:6
#define csr_CalDrvPdThOffset_BITS   3:0
#define csr_CalDrvPdThOffset_MSB  9
#define csr_CalDrvPdThOffset_LSB  6
#define csr_CalDrvPdThOffset_MASK 0x3c0
#define csr_CalDrvPuThOffset_RANGE  13:10
#define csr_CalDrvPuThOffset_BITS   3:0
#define csr_CalDrvPuThOffset_MSB  13
#define csr_CalDrvPuThOffset_LSB  10
#define csr_CalDrvPuThOffset_MASK 0x3c00
#define csr_SequenceReg0b9s2_RANGE  8:0
#define csr_SequenceReg0b9s2_BITS   8:0
#define csr_SequenceReg0b9s2_MSB  8
#define csr_SequenceReg0b9s2_LSB  0
#define csr_SequenceReg0b9s2_MASK 0x1ff
#define csr_SequenceReg0b95s0_RANGE  15:0
#define csr_SequenceReg0b95s0_BITS   15:0
#define csr_SequenceReg0b95s0_MSB  15
#define csr_SequenceReg0b95s0_LSB  0
#define csr_SequenceReg0b95s0_MASK 0xffff
#define csr_AcsmSeq2x6_RANGE  15:0
#define csr_AcsmSeq2x6_BITS   15:0
#define csr_AcsmSeq2x6_MSB  15
#define csr_AcsmSeq2x6_LSB  0
#define csr_AcsmSeq2x6_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x6_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x6_BITS   15:0
#define csr_AcsmDdrAdrx15x0x6_MSB  15
#define csr_AcsmDdrAdrx15x0x6_LSB  0
#define csr_AcsmDdrAdrx15x0x6_MASK 0xffff
#define csr_SequenceReg0b10s0_RANGE  15:0
#define csr_SequenceReg0b10s0_BITS   15:0
#define csr_SequenceReg0b10s0_MSB  15
#define csr_SequenceReg0b10s0_LSB  0
#define csr_SequenceReg0b10s0_MASK 0xffff
#define csr_SequenceReg0b95s1_RANGE  15:0
#define csr_SequenceReg0b95s1_BITS   15:0
#define csr_SequenceReg0b95s1_MSB  15
#define csr_SequenceReg0b95s1_LSB  0
#define csr_SequenceReg0b95s1_MASK 0xffff
#define csr_AcsmSeq2x7_RANGE  15:0
#define csr_AcsmSeq2x7_BITS   15:0
#define csr_AcsmSeq2x7_MSB  15
#define csr_AcsmSeq2x7_LSB  0
#define csr_AcsmSeq2x7_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x7_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x7_BITS   15:0
#define csr_AcsmDdrAdrx15x0x7_MSB  15
#define csr_AcsmDdrAdrx15x0x7_LSB  0
#define csr_AcsmDdrAdrx15x0x7_MASK 0xffff
#define csr_SarInitVals_RANGE  8:0
#define csr_SarInitVals_BITS   8:0
#define csr_SarInitVals_MSB  8
#define csr_SarInitVals_LSB  0
#define csr_SarInitVals_MASK 0x1ff
#define csr_SarInitOFFSET05_RANGE  2:0
#define csr_SarInitOFFSET05_BITS   2:0
#define csr_SarInitOFFSET05_MSB  2
#define csr_SarInitOFFSET05_LSB  0
#define csr_SarInitOFFSET05_MASK 0x7
#define csr_SarInitNINT_RANGE  5:3
#define csr_SarInitNINT_BITS   2:0
#define csr_SarInitNINT_MSB  5
#define csr_SarInitNINT_LSB  3
#define csr_SarInitNINT_MASK 0x38
#define csr_SarInitPEXT_RANGE  8:6
#define csr_SarInitPEXT_BITS   2:0
#define csr_SarInitPEXT_MSB  8
#define csr_SarInitPEXT_LSB  6
#define csr_SarInitPEXT_MASK 0x1c0
#define csr_SequenceReg0b10s1_RANGE  15:0
#define csr_SequenceReg0b10s1_BITS   15:0
#define csr_SequenceReg0b10s1_MSB  15
#define csr_SequenceReg0b10s1_LSB  0
#define csr_SequenceReg0b10s1_MASK 0xffff
#define csr_SequenceReg0b95s2_RANGE  8:0
#define csr_SequenceReg0b95s2_BITS   8:0
#define csr_SequenceReg0b95s2_MSB  8
#define csr_SequenceReg0b95s2_LSB  0
#define csr_SequenceReg0b95s2_MASK 0x1ff
#define csr_AcsmSeq2x8_RANGE  15:0
#define csr_AcsmSeq2x8_BITS   15:0
#define csr_AcsmSeq2x8_MSB  15
#define csr_AcsmSeq2x8_LSB  0
#define csr_AcsmSeq2x8_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x8_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x8_BITS   15:0
#define csr_AcsmDdrAdrx15x0x8_MSB  15
#define csr_AcsmDdrAdrx15x0x8_LSB  0
#define csr_AcsmDdrAdrx15x0x8_MASK 0xffff
#define csr_TxEqualizationMode_RANGE  1:0
#define csr_TxEqualizationMode_BITS   1:0
#define csr_TxEqualizationMode_MSB  1
#define csr_TxEqualizationMode_LSB  0
#define csr_TxEqualizationMode_MASK 0x3
#define csr_TxEqMode_RANGE  1:0
#define csr_TxEqMode_BITS   1:0
#define csr_TxEqMode_MSB  1
#define csr_TxEqMode_LSB  0
#define csr_TxEqMode_MASK 0x3
#define csr_SequenceReg0b10s2_RANGE  8:0
#define csr_SequenceReg0b10s2_BITS   8:0
#define csr_SequenceReg0b10s2_MSB  8
#define csr_SequenceReg0b10s2_LSB  0
#define csr_SequenceReg0b10s2_MASK 0x1ff
#define csr_SequenceReg0b96s0_RANGE  15:0
#define csr_SequenceReg0b96s0_BITS   15:0
#define csr_SequenceReg0b96s0_MSB  15
#define csr_SequenceReg0b96s0_LSB  0
#define csr_SequenceReg0b96s0_MASK 0xffff
#define csr_AcsmSeq2x9_RANGE  15:0
#define csr_AcsmSeq2x9_BITS   15:0
#define csr_AcsmSeq2x9_MSB  15
#define csr_AcsmSeq2x9_LSB  0
#define csr_AcsmSeq2x9_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x9_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x9_BITS   15:0
#define csr_AcsmDdrAdrx15x0x9_MSB  15
#define csr_AcsmDdrAdrx15x0x9_LSB  0
#define csr_AcsmDdrAdrx15x0x9_MASK 0xffff
#define csr_TxImpedanceCtrl1_RANGE  11:0
#define csr_TxImpedanceCtrl1_BITS   11:0
#define csr_TxImpedanceCtrl1_MSB  11
#define csr_TxImpedanceCtrl1_LSB  0
#define csr_TxImpedanceCtrl1_MASK 0xfff
#define csr_DrvStrenFSDqP_RANGE  5:0
#define csr_DrvStrenFSDqP_BITS   5:0
#define csr_DrvStrenFSDqP_MSB  5
#define csr_DrvStrenFSDqP_LSB  0
#define csr_DrvStrenFSDqP_MASK 0x3f
#define csr_DrvStrenFSDqN_RANGE  11:6
#define csr_DrvStrenFSDqN_BITS   5:0
#define csr_DrvStrenFSDqN_MSB  11
#define csr_DrvStrenFSDqN_LSB  6
#define csr_DrvStrenFSDqN_MASK 0xfc0
#define csr_CalPExtOvr_RANGE  4:0
#define csr_CalPExtOvr_BITS   4:0
#define csr_CalPExtOvr_MSB  4
#define csr_CalPExtOvr_LSB  0
#define csr_CalPExtOvr_MASK 0x1f
#define csr_SequenceReg0b11s0_RANGE  15:0
#define csr_SequenceReg0b11s0_BITS   15:0
#define csr_SequenceReg0b11s0_MSB  15
#define csr_SequenceReg0b11s0_LSB  0
#define csr_SequenceReg0b11s0_MASK 0xffff
#define csr_SequenceReg0b96s1_RANGE  15:0
#define csr_SequenceReg0b96s1_BITS   15:0
#define csr_SequenceReg0b96s1_MSB  15
#define csr_SequenceReg0b96s1_LSB  0
#define csr_SequenceReg0b96s1_MASK 0xffff
#define csr_AcsmSeq2x10_RANGE  15:0
#define csr_AcsmSeq2x10_BITS   15:0
#define csr_AcsmSeq2x10_MSB  15
#define csr_AcsmSeq2x10_LSB  0
#define csr_AcsmSeq2x10_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x10_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x10_BITS   15:0
#define csr_AcsmDdrAdrx15x0x10_MSB  15
#define csr_AcsmDdrAdrx15x0x10_LSB  0
#define csr_AcsmDdrAdrx15x0x10_MASK 0xffff
#define csr_DqDqsRcvCntrl1_RANGE  11:0
#define csr_DqDqsRcvCntrl1_BITS   11:0
#define csr_DqDqsRcvCntrl1_MSB  11
#define csr_DqDqsRcvCntrl1_LSB  0
#define csr_DqDqsRcvCntrl1_MASK 0xfff
#define csr_PowerDownRcvr_RANGE  8:0
#define csr_PowerDownRcvr_BITS   8:0
#define csr_PowerDownRcvr_MSB  8
#define csr_PowerDownRcvr_LSB  0
#define csr_PowerDownRcvr_MASK 0x1ff
#define csr_PowerDownRcvrDqs_RANGE  9:9
#define csr_PowerDownRcvrDqs_BITS   0:0
#define csr_PowerDownRcvrDqs_MSB  9
#define csr_PowerDownRcvrDqs_LSB  9
#define csr_PowerDownRcvrDqs_MASK 0x200
#define csr_RxPadStandbyEn_RANGE  10:10
#define csr_RxPadStandbyEn_BITS   0:0
#define csr_RxPadStandbyEn_MSB  10
#define csr_RxPadStandbyEn_LSB  10
#define csr_RxPadStandbyEn_MASK 0x400
#define csr_EnLPReqPDR_RANGE  11:11
#define csr_EnLPReqPDR_BITS   0:0
#define csr_EnLPReqPDR_MSB  11
#define csr_EnLPReqPDR_LSB  11
#define csr_EnLPReqPDR_MASK 0x800
#define csr_CalCmpr5Ovr_RANGE  7:0
#define csr_CalCmpr5Ovr_BITS   7:0
#define csr_CalCmpr5Ovr_MSB  7
#define csr_CalCmpr5Ovr_LSB  0
#define csr_CalCmpr5Ovr_MASK 0xff
#define csr_SequenceReg0b11s1_RANGE  15:0
#define csr_SequenceReg0b11s1_BITS   15:0
#define csr_SequenceReg0b11s1_MSB  15
#define csr_SequenceReg0b11s1_LSB  0
#define csr_SequenceReg0b11s1_MASK 0xffff
#define csr_SequenceReg0b96s2_RANGE  8:0
#define csr_SequenceReg0b96s2_BITS   8:0
#define csr_SequenceReg0b96s2_MSB  8
#define csr_SequenceReg0b96s2_LSB  0
#define csr_SequenceReg0b96s2_MASK 0x1ff
#define csr_AcsmSeq2x11_RANGE  15:0
#define csr_AcsmSeq2x11_BITS   15:0
#define csr_AcsmSeq2x11_MSB  15
#define csr_AcsmSeq2x11_LSB  0
#define csr_AcsmSeq2x11_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x11_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x11_BITS   15:0
#define csr_AcsmDdrAdrx15x0x11_MSB  15
#define csr_AcsmDdrAdrx15x0x11_LSB  0
#define csr_AcsmDdrAdrx15x0x11_MASK 0xffff
#define csr_TxImpedanceCtrl2_RANGE  11:0
#define csr_TxImpedanceCtrl2_BITS   11:0
#define csr_TxImpedanceCtrl2_MSB  11
#define csr_TxImpedanceCtrl2_LSB  0
#define csr_TxImpedanceCtrl2_MASK 0xfff
#define csr_DrvStrenEQHiDqP_RANGE  5:0
#define csr_DrvStrenEQHiDqP_BITS   5:0
#define csr_DrvStrenEQHiDqP_MSB  5
#define csr_DrvStrenEQHiDqP_LSB  0
#define csr_DrvStrenEQHiDqP_MASK 0x3f
#define csr_DrvStrenEQLoDqN_RANGE  11:6
#define csr_DrvStrenEQLoDqN_BITS   5:0
#define csr_DrvStrenEQLoDqN_MSB  11
#define csr_DrvStrenEQLoDqN_LSB  6
#define csr_DrvStrenEQLoDqN_MASK 0xfc0
#define csr_CalNIntOvr_RANGE  4:0
#define csr_CalNIntOvr_BITS   4:0
#define csr_CalNIntOvr_MSB  4
#define csr_CalNIntOvr_LSB  0
#define csr_CalNIntOvr_MASK 0x1f
#define csr_SequenceReg0b11s2_RANGE  8:0
#define csr_SequenceReg0b11s2_BITS   8:0
#define csr_SequenceReg0b11s2_MSB  8
#define csr_SequenceReg0b11s2_LSB  0
#define csr_SequenceReg0b11s2_MASK 0x1ff
#define csr_SequenceReg0b97s0_RANGE  15:0
#define csr_SequenceReg0b97s0_BITS   15:0
#define csr_SequenceReg0b97s0_MSB  15
#define csr_SequenceReg0b97s0_LSB  0
#define csr_SequenceReg0b97s0_MASK 0xffff
#define csr_AcsmSeq2x12_RANGE  15:0
#define csr_AcsmSeq2x12_BITS   15:0
#define csr_AcsmSeq2x12_MSB  15
#define csr_AcsmSeq2x12_LSB  0
#define csr_AcsmSeq2x12_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x12_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x12_BITS   15:0
#define csr_AcsmDdrAdrx15x0x12_MSB  15
#define csr_AcsmDdrAdrx15x0x12_LSB  0
#define csr_AcsmDdrAdrx15x0x12_MASK 0xffff
#define csr_DqDqsRcvCntrl2_RANGE  0:0
#define csr_DqDqsRcvCntrl2_BITS   0:0
#define csr_DqDqsRcvCntrl2_MSB  0
#define csr_DqDqsRcvCntrl2_LSB  0
#define csr_DqDqsRcvCntrl2_MASK 0x1
#define csr_EnRxAgressivePDR_RANGE  0:0
#define csr_EnRxAgressivePDR_BITS   0:0
#define csr_EnRxAgressivePDR_MSB  0
#define csr_EnRxAgressivePDR_LSB  0
#define csr_EnRxAgressivePDR_MASK 0x1
#define csr_SequenceReg0b12s0_RANGE  15:0
#define csr_SequenceReg0b12s0_BITS   15:0
#define csr_SequenceReg0b12s0_MSB  15
#define csr_SequenceReg0b12s0_LSB  0
#define csr_SequenceReg0b12s0_MASK 0xffff
#define csr_SequenceReg0b97s1_RANGE  15:0
#define csr_SequenceReg0b97s1_BITS   15:0
#define csr_SequenceReg0b97s1_MSB  15
#define csr_SequenceReg0b97s1_LSB  0
#define csr_SequenceReg0b97s1_MASK 0xffff
#define csr_AcsmSeq2x13_RANGE  15:0
#define csr_AcsmSeq2x13_BITS   15:0
#define csr_AcsmSeq2x13_MSB  15
#define csr_AcsmSeq2x13_LSB  0
#define csr_AcsmSeq2x13_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x13_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x13_BITS   15:0
#define csr_AcsmDdrAdrx15x0x13_MSB  15
#define csr_AcsmDdrAdrx15x0x13_LSB  0
#define csr_AcsmDdrAdrx15x0x13_MASK 0xffff
#define csr_TxOdtDrvStren_RANGE  11:0
#define csr_TxOdtDrvStren_BITS   11:0
#define csr_TxOdtDrvStren_MSB  11
#define csr_TxOdtDrvStren_LSB  0
#define csr_TxOdtDrvStren_MASK 0xfff
#define csr_ODTStrenP_RANGE  5:0
#define csr_ODTStrenP_BITS   5:0
#define csr_ODTStrenP_MSB  5
#define csr_ODTStrenP_LSB  0
#define csr_ODTStrenP_MASK 0x3f
#define csr_ODTStrenN_RANGE  11:6
#define csr_ODTStrenN_BITS   5:0
#define csr_ODTStrenN_MSB  11
#define csr_ODTStrenN_LSB  6
#define csr_ODTStrenN_MASK 0xfc0
#define csr_SequenceReg0b12s1_RANGE  15:0
#define csr_SequenceReg0b12s1_BITS   15:0
#define csr_SequenceReg0b12s1_MSB  15
#define csr_SequenceReg0b12s1_LSB  0
#define csr_SequenceReg0b12s1_MASK 0xffff
#define csr_SequenceReg0b97s2_RANGE  8:0
#define csr_SequenceReg0b97s2_BITS   8:0
#define csr_SequenceReg0b97s2_MSB  8
#define csr_SequenceReg0b97s2_LSB  0
#define csr_SequenceReg0b97s2_MASK 0x1ff
#define csr_AcsmSeq2x14_RANGE  15:0
#define csr_AcsmSeq2x14_BITS   15:0
#define csr_AcsmSeq2x14_MSB  15
#define csr_AcsmSeq2x14_LSB  0
#define csr_AcsmSeq2x14_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x14_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x14_BITS   15:0
#define csr_AcsmDdrAdrx15x0x14_MSB  15
#define csr_AcsmDdrAdrx15x0x14_LSB  0
#define csr_AcsmDdrAdrx15x0x14_MASK 0xffff
#define csr_SequenceReg0b12s2_RANGE  8:0
#define csr_SequenceReg0b12s2_BITS   8:0
#define csr_SequenceReg0b12s2_MSB  8
#define csr_SequenceReg0b12s2_LSB  0
#define csr_SequenceReg0b12s2_MASK 0x1ff
#define csr_SequenceReg0b98s0_RANGE  15:0
#define csr_SequenceReg0b98s0_BITS   15:0
#define csr_SequenceReg0b98s0_MSB  15
#define csr_SequenceReg0b98s0_LSB  0
#define csr_SequenceReg0b98s0_MASK 0xffff
#define csr_AcsmSeq2x15_RANGE  15:0
#define csr_AcsmSeq2x15_BITS   15:0
#define csr_AcsmSeq2x15_MSB  15
#define csr_AcsmSeq2x15_LSB  0
#define csr_AcsmSeq2x15_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x15_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x15_BITS   15:0
#define csr_AcsmDdrAdrx15x0x15_MSB  15
#define csr_AcsmDdrAdrx15x0x15_LSB  0
#define csr_AcsmDdrAdrx15x0x15_MASK 0xffff
#define csr_SequenceReg0b13s0_RANGE  15:0
#define csr_SequenceReg0b13s0_BITS   15:0
#define csr_SequenceReg0b13s0_MSB  15
#define csr_SequenceReg0b13s0_LSB  0
#define csr_SequenceReg0b13s0_MASK 0xffff
#define csr_SequenceReg0b98s1_RANGE  15:0
#define csr_SequenceReg0b98s1_BITS   15:0
#define csr_SequenceReg0b98s1_MSB  15
#define csr_SequenceReg0b98s1_LSB  0
#define csr_SequenceReg0b98s1_MASK 0xffff
#define csr_AcsmSeq2x16_RANGE  15:0
#define csr_AcsmSeq2x16_BITS   15:0
#define csr_AcsmSeq2x16_MSB  15
#define csr_AcsmSeq2x16_LSB  0
#define csr_AcsmSeq2x16_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x16_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x16_BITS   15:0
#define csr_AcsmDdrAdrx15x0x16_MSB  15
#define csr_AcsmDdrAdrx15x0x16_LSB  0
#define csr_AcsmDdrAdrx15x0x16_MASK 0xffff
#define csr_CalDrvStr0_RANGE  7:0
#define csr_CalDrvStr0_BITS   7:0
#define csr_CalDrvStr0_MSB  7
#define csr_CalDrvStr0_LSB  0
#define csr_CalDrvStr0_MASK 0xff
#define csr_CalDrvStrPd50_RANGE  3:0
#define csr_CalDrvStrPd50_BITS   3:0
#define csr_CalDrvStrPd50_MSB  3
#define csr_CalDrvStrPd50_LSB  0
#define csr_CalDrvStrPd50_MASK 0xf
#define csr_CalDrvStrPu50_RANGE  7:4
#define csr_CalDrvStrPu50_BITS   3:0
#define csr_CalDrvStrPu50_MSB  7
#define csr_CalDrvStrPu50_LSB  4
#define csr_CalDrvStrPu50_MASK 0xf0
#define csr_SequenceReg0b13s1_RANGE  15:0
#define csr_SequenceReg0b13s1_BITS   15:0
#define csr_SequenceReg0b13s1_MSB  15
#define csr_SequenceReg0b13s1_LSB  0
#define csr_SequenceReg0b13s1_MASK 0xffff
#define csr_SequenceReg0b98s2_RANGE  8:0
#define csr_SequenceReg0b98s2_BITS   8:0
#define csr_SequenceReg0b98s2_MSB  8
#define csr_SequenceReg0b98s2_LSB  0
#define csr_SequenceReg0b98s2_MASK 0x1ff
#define csr_AcsmSeq2x17_RANGE  15:0
#define csr_AcsmSeq2x17_BITS   15:0
#define csr_AcsmSeq2x17_MSB  15
#define csr_AcsmSeq2x17_LSB  0
#define csr_AcsmSeq2x17_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x17_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x17_BITS   15:0
#define csr_AcsmDdrAdrx15x0x17_MSB  15
#define csr_AcsmDdrAdrx15x0x17_LSB  0
#define csr_AcsmDdrAdrx15x0x17_MASK 0xffff
#define csr_SequenceReg0b13s2_RANGE  8:0
#define csr_SequenceReg0b13s2_BITS   8:0
#define csr_SequenceReg0b13s2_MSB  8
#define csr_SequenceReg0b13s2_LSB  0
#define csr_SequenceReg0b13s2_MASK 0x1ff
#define csr_SequenceReg0b99s0_RANGE  15:0
#define csr_SequenceReg0b99s0_BITS   15:0
#define csr_SequenceReg0b99s0_MSB  15
#define csr_SequenceReg0b99s0_LSB  0
#define csr_SequenceReg0b99s0_MASK 0xffff
#define csr_AcsmSeq2x18_RANGE  15:0
#define csr_AcsmSeq2x18_BITS   15:0
#define csr_AcsmSeq2x18_MSB  15
#define csr_AcsmSeq2x18_LSB  0
#define csr_AcsmSeq2x18_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x18_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x18_BITS   15:0
#define csr_AcsmDdrAdrx15x0x18_MSB  15
#define csr_AcsmDdrAdrx15x0x18_LSB  0
#define csr_AcsmDdrAdrx15x0x18_MASK 0xffff
#define csr_SequenceReg0b14s0_RANGE  15:0
#define csr_SequenceReg0b14s0_BITS   15:0
#define csr_SequenceReg0b14s0_MSB  15
#define csr_SequenceReg0b14s0_LSB  0
#define csr_SequenceReg0b14s0_MASK 0xffff
#define csr_SequenceReg0b99s1_RANGE  15:0
#define csr_SequenceReg0b99s1_BITS   15:0
#define csr_SequenceReg0b99s1_MSB  15
#define csr_SequenceReg0b99s1_LSB  0
#define csr_SequenceReg0b99s1_MASK 0xffff
#define csr_AcsmSeq2x19_RANGE  15:0
#define csr_AcsmSeq2x19_BITS   15:0
#define csr_AcsmSeq2x19_MSB  15
#define csr_AcsmSeq2x19_LSB  0
#define csr_AcsmSeq2x19_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x19_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x19_BITS   15:0
#define csr_AcsmDdrAdrx15x0x19_MSB  15
#define csr_AcsmDdrAdrx15x0x19_LSB  0
#define csr_AcsmDdrAdrx15x0x19_MASK 0xffff
#define csr_ATestPrbsErr_RANGE  3:0
#define csr_ATestPrbsErr_BITS   3:0
#define csr_ATestPrbsErr_MSB  3
#define csr_ATestPrbsErr_LSB  0
#define csr_ATestPrbsErr_MASK 0xf
#define csr_SequenceReg0b14s1_RANGE  15:0
#define csr_SequenceReg0b14s1_BITS   15:0
#define csr_SequenceReg0b14s1_MSB  15
#define csr_SequenceReg0b14s1_LSB  0
#define csr_SequenceReg0b14s1_MASK 0xffff
#define csr_SequenceReg0b99s2_RANGE  8:0
#define csr_SequenceReg0b99s2_BITS   8:0
#define csr_SequenceReg0b99s2_MSB  8
#define csr_SequenceReg0b99s2_LSB  0
#define csr_SequenceReg0b99s2_MASK 0x1ff
#define csr_AcsmSeq2x20_RANGE  15:0
#define csr_AcsmSeq2x20_BITS   15:0
#define csr_AcsmSeq2x20_MSB  15
#define csr_AcsmSeq2x20_LSB  0
#define csr_AcsmSeq2x20_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x20_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x20_BITS   15:0
#define csr_AcsmDdrAdrx15x0x20_MSB  15
#define csr_AcsmDdrAdrx15x0x20_LSB  0
#define csr_AcsmDdrAdrx15x0x20_MASK 0xffff
#define csr_SequenceReg0b14s2_RANGE  8:0
#define csr_SequenceReg0b14s2_BITS   8:0
#define csr_SequenceReg0b14s2_MSB  8
#define csr_SequenceReg0b14s2_LSB  0
#define csr_SequenceReg0b14s2_MASK 0x1ff
#define csr_SequenceReg0b100s0_RANGE  15:0
#define csr_SequenceReg0b100s0_BITS   15:0
#define csr_SequenceReg0b100s0_MSB  15
#define csr_SequenceReg0b100s0_LSB  0
#define csr_SequenceReg0b100s0_MASK 0xffff
#define csr_AcsmSeq2x21_RANGE  15:0
#define csr_AcsmSeq2x21_BITS   15:0
#define csr_AcsmSeq2x21_MSB  15
#define csr_AcsmSeq2x21_LSB  0
#define csr_AcsmSeq2x21_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x21_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x21_BITS   15:0
#define csr_AcsmDdrAdrx15x0x21_MSB  15
#define csr_AcsmDdrAdrx15x0x21_LSB  0
#define csr_AcsmDdrAdrx15x0x21_MASK 0xffff
#define csr_ProcOdtCtl_RANGE  1:0
#define csr_ProcOdtCtl_BITS   1:0
#define csr_ProcOdtCtl_MSB  1
#define csr_ProcOdtCtl_LSB  0
#define csr_ProcOdtCtl_MASK 0x3
#define csr_ProcOdtAlwaysOff_RANGE  0:0
#define csr_ProcOdtAlwaysOff_BITS   0:0
#define csr_ProcOdtAlwaysOff_MSB  0
#define csr_ProcOdtAlwaysOff_LSB  0
#define csr_ProcOdtAlwaysOff_MASK 0x1
#define csr_ProcOdtAlwaysOn_RANGE  1:1
#define csr_ProcOdtAlwaysOn_BITS   0:0
#define csr_ProcOdtAlwaysOn_MSB  1
#define csr_ProcOdtAlwaysOn_LSB  1
#define csr_ProcOdtAlwaysOn_MASK 0x2
#define csr_ATxSlewRate_RANGE  10:0
#define csr_ATxSlewRate_BITS   10:0
#define csr_ATxSlewRate_MSB  10
#define csr_ATxSlewRate_LSB  0
#define csr_ATxSlewRate_MASK 0x7ff
#define csr_ATxPreP_RANGE  3:0
#define csr_ATxPreP_BITS   3:0
#define csr_ATxPreP_MSB  3
#define csr_ATxPreP_LSB  0
#define csr_ATxPreP_MASK 0xf
#define csr_ATxPreN_RANGE  7:4
#define csr_ATxPreN_BITS   3:0
#define csr_ATxPreN_MSB  7
#define csr_ATxPreN_LSB  4
#define csr_ATxPreN_MASK 0xf0
#define csr_ATxPreDrvMode_RANGE  10:8
#define csr_ATxPreDrvMode_BITS   2:0
#define csr_ATxPreDrvMode_MSB  10
#define csr_ATxPreDrvMode_LSB  8
#define csr_ATxPreDrvMode_MASK 0x700
#define csr_SequenceReg0b15s0_RANGE  15:0
#define csr_SequenceReg0b15s0_BITS   15:0
#define csr_SequenceReg0b15s0_MSB  15
#define csr_SequenceReg0b15s0_LSB  0
#define csr_SequenceReg0b15s0_MASK 0xffff
#define csr_SequenceReg0b100s1_RANGE  15:0
#define csr_SequenceReg0b100s1_BITS   15:0
#define csr_SequenceReg0b100s1_MSB  15
#define csr_SequenceReg0b100s1_LSB  0
#define csr_SequenceReg0b100s1_MASK 0xffff
#define csr_AcsmSeq2x22_RANGE  15:0
#define csr_AcsmSeq2x22_BITS   15:0
#define csr_AcsmSeq2x22_MSB  15
#define csr_AcsmSeq2x22_LSB  0
#define csr_AcsmSeq2x22_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x22_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x22_BITS   15:0
#define csr_AcsmDdrAdrx15x0x22_MSB  15
#define csr_AcsmDdrAdrx15x0x22_LSB  0
#define csr_AcsmDdrAdrx15x0x22_MASK 0xffff
#define csr_ProcOdtTimeCtl_RANGE  5:0
#define csr_ProcOdtTimeCtl_BITS   5:0
#define csr_ProcOdtTimeCtl_MSB  5
#define csr_ProcOdtTimeCtl_LSB  0
#define csr_ProcOdtTimeCtl_MASK 0x3f
#define csr_POdtTailWidth_RANGE  1:0
#define csr_POdtTailWidth_BITS   1:0
#define csr_POdtTailWidth_MSB  1
#define csr_POdtTailWidth_LSB  0
#define csr_POdtTailWidth_MASK 0x3
#define csr_POdtStartDelay_RANGE  3:2
#define csr_POdtStartDelay_BITS   1:0
#define csr_POdtStartDelay_MSB  3
#define csr_POdtStartDelay_LSB  2
#define csr_POdtStartDelay_MASK 0xc
#define csr_POdtTailWidthExt_RANGE  5:4
#define csr_POdtTailWidthExt_BITS   1:0
#define csr_POdtTailWidthExt_MSB  5
#define csr_POdtTailWidthExt_LSB  4
#define csr_POdtTailWidthExt_MASK 0x30
#define csr_ATestPrbsErrCnt_RANGE  15:0
#define csr_ATestPrbsErrCnt_BITS   15:0
#define csr_ATestPrbsErrCnt_MSB  15
#define csr_ATestPrbsErrCnt_LSB  0
#define csr_ATestPrbsErrCnt_MASK 0xffff
#define csr_RxFifoCheckStatus_RANGE  1:0
#define csr_RxFifoCheckStatus_BITS   1:0
#define csr_RxFifoCheckStatus_MSB  1
#define csr_RxFifoCheckStatus_LSB  0
#define csr_RxFifoCheckStatus_MASK 0x3
#define csr_RxFifoLocErr_RANGE  0:0
#define csr_RxFifoLocErr_BITS   0:0
#define csr_RxFifoLocErr_MSB  0
#define csr_RxFifoLocErr_LSB  0
#define csr_RxFifoLocErr_MASK 0x1
#define csr_RxFifoLocUErr_RANGE  1:1
#define csr_RxFifoLocUErr_BITS   0:0
#define csr_RxFifoLocUErr_MSB  1
#define csr_RxFifoLocUErr_LSB  1
#define csr_RxFifoLocUErr_MASK 0x2
#define csr_SequenceReg0b15s1_RANGE  15:0
#define csr_SequenceReg0b15s1_BITS   15:0
#define csr_SequenceReg0b15s1_MSB  15
#define csr_SequenceReg0b15s1_LSB  0
#define csr_SequenceReg0b15s1_MASK 0xffff
#define csr_SequenceReg0b100s2_RANGE  8:0
#define csr_SequenceReg0b100s2_BITS   8:0
#define csr_SequenceReg0b100s2_MSB  8
#define csr_SequenceReg0b100s2_LSB  0
#define csr_SequenceReg0b100s2_MASK 0x1ff
#define csr_AcsmSeq2x23_RANGE  15:0
#define csr_AcsmSeq2x23_BITS   15:0
#define csr_AcsmSeq2x23_MSB  15
#define csr_AcsmSeq2x23_LSB  0
#define csr_AcsmSeq2x23_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x23_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x23_BITS   15:0
#define csr_AcsmDdrAdrx15x0x23_MSB  15
#define csr_AcsmDdrAdrx15x0x23_LSB  0
#define csr_AcsmDdrAdrx15x0x23_MASK 0xffff
#define csr_RxFifoCheckErrValues_RANGE  15:0
#define csr_RxFifoCheckErrValues_BITS   15:0
#define csr_RxFifoCheckErrValues_MSB  15
#define csr_RxFifoCheckErrValues_LSB  0
#define csr_RxFifoCheckErrValues_MASK 0xffff
#define csr_RxFifoRdLocErrValue_RANGE  3:0
#define csr_RxFifoRdLocErrValue_BITS   3:0
#define csr_RxFifoRdLocErrValue_MSB  3
#define csr_RxFifoRdLocErrValue_LSB  0
#define csr_RxFifoRdLocErrValue_MASK 0xf
#define csr_RxFifoWrLocErrValue_RANGE  7:4
#define csr_RxFifoWrLocErrValue_BITS   3:0
#define csr_RxFifoWrLocErrValue_MSB  7
#define csr_RxFifoWrLocErrValue_LSB  4
#define csr_RxFifoWrLocErrValue_MASK 0xf0
#define csr_RxFifoRdLocUErrValue_RANGE  11:8
#define csr_RxFifoRdLocUErrValue_BITS   3:0
#define csr_RxFifoRdLocUErrValue_MSB  11
#define csr_RxFifoRdLocUErrValue_LSB  8
#define csr_RxFifoRdLocUErrValue_MASK 0xf00
#define csr_RxFifoWrLocUErrValue_RANGE  15:12
#define csr_RxFifoWrLocUErrValue_BITS   3:0
#define csr_RxFifoWrLocUErrValue_MSB  15
#define csr_RxFifoWrLocUErrValue_LSB  12
#define csr_RxFifoWrLocUErrValue_MASK 0xf000
#define csr_SequenceReg0b15s2_RANGE  8:0
#define csr_SequenceReg0b15s2_BITS   8:0
#define csr_SequenceReg0b15s2_MSB  8
#define csr_SequenceReg0b15s2_LSB  0
#define csr_SequenceReg0b15s2_MASK 0x1ff
#define csr_SequenceReg0b101s0_RANGE  15:0
#define csr_SequenceReg0b101s0_BITS   15:0
#define csr_SequenceReg0b101s0_MSB  15
#define csr_SequenceReg0b101s0_LSB  0
#define csr_SequenceReg0b101s0_MASK 0xffff
#define csr_AcsmSeq2x24_RANGE  15:0
#define csr_AcsmSeq2x24_BITS   15:0
#define csr_AcsmSeq2x24_MSB  15
#define csr_AcsmSeq2x24_LSB  0
#define csr_AcsmSeq2x24_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x24_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x24_BITS   15:0
#define csr_AcsmDdrAdrx15x0x24_MSB  15
#define csr_AcsmDdrAdrx15x0x24_LSB  0
#define csr_AcsmDdrAdrx15x0x24_MASK 0xffff
#define csr_RxFifoInfo_RANGE  15:0
#define csr_RxFifoInfo_BITS   15:0
#define csr_RxFifoInfo_MSB  15
#define csr_RxFifoInfo_LSB  0
#define csr_RxFifoInfo_MASK 0xffff
#define csr_RxFifoRdLoc_RANGE  3:0
#define csr_RxFifoRdLoc_BITS   3:0
#define csr_RxFifoRdLoc_MSB  3
#define csr_RxFifoRdLoc_LSB  0
#define csr_RxFifoRdLoc_MASK 0xf
#define csr_RxFifoWrLoc_RANGE  7:4
#define csr_RxFifoWrLoc_BITS   3:0
#define csr_RxFifoWrLoc_MSB  7
#define csr_RxFifoWrLoc_LSB  4
#define csr_RxFifoWrLoc_MASK 0xf0
#define csr_RxFifoRdLocU_RANGE  11:8
#define csr_RxFifoRdLocU_BITS   3:0
#define csr_RxFifoRdLocU_MSB  11
#define csr_RxFifoRdLocU_LSB  8
#define csr_RxFifoRdLocU_MASK 0xf00
#define csr_RxFifoWrLocU_RANGE  15:12
#define csr_RxFifoWrLocU_BITS   3:0
#define csr_RxFifoWrLocU_MSB  15
#define csr_RxFifoWrLocU_LSB  12
#define csr_RxFifoWrLocU_MASK 0xf000
#define csr_SequenceReg0b16s0_RANGE  15:0
#define csr_SequenceReg0b16s0_BITS   15:0
#define csr_SequenceReg0b16s0_MSB  15
#define csr_SequenceReg0b16s0_LSB  0
#define csr_SequenceReg0b16s0_MASK 0xffff
#define csr_SequenceReg0b101s1_RANGE  15:0
#define csr_SequenceReg0b101s1_BITS   15:0
#define csr_SequenceReg0b101s1_MSB  15
#define csr_SequenceReg0b101s1_LSB  0
#define csr_SequenceReg0b101s1_MASK 0xffff
#define csr_AcsmSeq2x25_RANGE  15:0
#define csr_AcsmSeq2x25_BITS   15:0
#define csr_AcsmSeq2x25_MSB  15
#define csr_AcsmSeq2x25_LSB  0
#define csr_AcsmSeq2x25_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x25_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x25_BITS   15:0
#define csr_AcsmDdrAdrx15x0x25_MSB  15
#define csr_AcsmDdrAdrx15x0x25_LSB  0
#define csr_AcsmDdrAdrx15x0x25_MASK 0xffff
#define csr_RxFifoVisibility_RANGE  4:0
#define csr_RxFifoVisibility_BITS   4:0
#define csr_RxFifoVisibility_MSB  4
#define csr_RxFifoVisibility_LSB  0
#define csr_RxFifoVisibility_MASK 0x1f
#define csr_RxFifoRdPtr_RANGE  2:0
#define csr_RxFifoRdPtr_BITS   2:0
#define csr_RxFifoRdPtr_MSB  2
#define csr_RxFifoRdPtr_LSB  0
#define csr_RxFifoRdPtr_MASK 0x7
#define csr_RxFifoRdPtrOvr_RANGE  3:3
#define csr_RxFifoRdPtrOvr_BITS   0:0
#define csr_RxFifoRdPtrOvr_MSB  3
#define csr_RxFifoRdPtrOvr_LSB  3
#define csr_RxFifoRdPtrOvr_MASK 0x8
#define csr_RxFifoRdEn_RANGE  4:4
#define csr_RxFifoRdEn_BITS   0:0
#define csr_RxFifoRdEn_MSB  4
#define csr_RxFifoRdEn_LSB  4
#define csr_RxFifoRdEn_MASK 0x10
#define csr_SequenceReg0b16s1_RANGE  15:0
#define csr_SequenceReg0b16s1_BITS   15:0
#define csr_SequenceReg0b16s1_MSB  15
#define csr_SequenceReg0b16s1_LSB  0
#define csr_SequenceReg0b16s1_MASK 0xffff
#define csr_SequenceReg0b101s2_RANGE  8:0
#define csr_SequenceReg0b101s2_BITS   8:0
#define csr_SequenceReg0b101s2_MSB  8
#define csr_SequenceReg0b101s2_LSB  0
#define csr_SequenceReg0b101s2_MASK 0x1ff
#define csr_AcsmSeq2x26_RANGE  15:0
#define csr_AcsmSeq2x26_BITS   15:0
#define csr_AcsmSeq2x26_MSB  15
#define csr_AcsmSeq2x26_LSB  0
#define csr_AcsmSeq2x26_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x26_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x26_BITS   15:0
#define csr_AcsmDdrAdrx15x0x26_MSB  15
#define csr_AcsmDdrAdrx15x0x26_LSB  0
#define csr_AcsmDdrAdrx15x0x26_MASK 0xffff
#define csr_RxFifoContentsDQ3210_RANGE  15:0
#define csr_RxFifoContentsDQ3210_BITS   15:0
#define csr_RxFifoContentsDQ3210_MSB  15
#define csr_RxFifoContentsDQ3210_LSB  0
#define csr_RxFifoContentsDQ3210_MASK 0xffff
#define csr_SequenceReg0b16s2_RANGE  8:0
#define csr_SequenceReg0b16s2_BITS   8:0
#define csr_SequenceReg0b16s2_MSB  8
#define csr_SequenceReg0b16s2_LSB  0
#define csr_SequenceReg0b16s2_MASK 0x1ff
#define csr_SequenceReg0b102s0_RANGE  15:0
#define csr_SequenceReg0b102s0_BITS   15:0
#define csr_SequenceReg0b102s0_MSB  15
#define csr_SequenceReg0b102s0_LSB  0
#define csr_SequenceReg0b102s0_MASK 0xffff
#define csr_MemAlertControl_RANGE  15:0
#define csr_MemAlertControl_BITS   15:0
#define csr_MemAlertControl_MSB  15
#define csr_MemAlertControl_LSB  0
#define csr_MemAlertControl_MASK 0xffff
#define csr_MALERTVrefLevel_RANGE  6:0
#define csr_MALERTVrefLevel_BITS   6:0
#define csr_MALERTVrefLevel_MSB  6
#define csr_MALERTVrefLevel_LSB  0
#define csr_MALERTVrefLevel_MASK 0x7f
#define csr_MALERTVrefExtEn_RANGE  7:7
#define csr_MALERTVrefExtEn_BITS   0:0
#define csr_MALERTVrefExtEn_MSB  7
#define csr_MALERTVrefExtEn_LSB  7
#define csr_MALERTVrefExtEn_MASK 0x80
#define csr_MALERTPuStren_RANGE  11:8
#define csr_MALERTPuStren_BITS   3:0
#define csr_MALERTPuStren_MSB  11
#define csr_MALERTPuStren_LSB  8
#define csr_MALERTPuStren_MASK 0xf00
#define csr_MALERTPuEn_RANGE  12:12
#define csr_MALERTPuEn_BITS   0:0
#define csr_MALERTPuEn_MSB  12
#define csr_MALERTPuEn_LSB  12
#define csr_MALERTPuEn_MASK 0x1000
#define csr_MALERTRxEn_RANGE  13:13
#define csr_MALERTRxEn_BITS   0:0
#define csr_MALERTRxEn_MSB  13
#define csr_MALERTRxEn_LSB  13
#define csr_MALERTRxEn_MASK 0x2000
#define csr_MALERTDisableVal_RANGE  14:14
#define csr_MALERTDisableVal_BITS   0:0
#define csr_MALERTDisableVal_MSB  14
#define csr_MALERTDisableVal_LSB  14
#define csr_MALERTDisableVal_MASK 0x4000
#define csr_MALERTForceError_RANGE  15:15
#define csr_MALERTForceError_BITS   0:0
#define csr_MALERTForceError_MSB  15
#define csr_MALERTForceError_LSB  15
#define csr_MALERTForceError_MASK 0x8000
#define csr_AcsmSeq2x27_RANGE  15:0
#define csr_AcsmSeq2x27_BITS   15:0
#define csr_AcsmSeq2x27_MSB  15
#define csr_AcsmSeq2x27_LSB  0
#define csr_AcsmSeq2x27_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x27_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x27_BITS   15:0
#define csr_AcsmDdrAdrx15x0x27_MSB  15
#define csr_AcsmDdrAdrx15x0x27_LSB  0
#define csr_AcsmDdrAdrx15x0x27_MASK 0xffff
#define csr_RxFifoContentsDQ7654_RANGE  15:0
#define csr_RxFifoContentsDQ7654_BITS   15:0
#define csr_RxFifoContentsDQ7654_MSB  15
#define csr_RxFifoContentsDQ7654_LSB  0
#define csr_RxFifoContentsDQ7654_MASK 0xffff
#define csr_SequenceReg0b17s0_RANGE  15:0
#define csr_SequenceReg0b17s0_BITS   15:0
#define csr_SequenceReg0b17s0_MSB  15
#define csr_SequenceReg0b17s0_LSB  0
#define csr_SequenceReg0b17s0_MASK 0xffff
#define csr_SequenceReg0b102s1_RANGE  15:0
#define csr_SequenceReg0b102s1_BITS   15:0
#define csr_SequenceReg0b102s1_MSB  15
#define csr_SequenceReg0b102s1_LSB  0
#define csr_SequenceReg0b102s1_MASK 0xffff
#define csr_MemAlertControl2_RANGE  0:0
#define csr_MemAlertControl2_BITS   0:0
#define csr_MemAlertControl2_MSB  0
#define csr_MemAlertControl2_LSB  0
#define csr_MemAlertControl2_MASK 0x1
#define csr_MALERTSyncBypass_RANGE  0:0
#define csr_MALERTSyncBypass_BITS   0:0
#define csr_MALERTSyncBypass_MSB  0
#define csr_MALERTSyncBypass_LSB  0
#define csr_MALERTSyncBypass_MASK 0x1
#define csr_AcsmSeq2x28_RANGE  15:0
#define csr_AcsmSeq2x28_BITS   15:0
#define csr_AcsmSeq2x28_MSB  15
#define csr_AcsmSeq2x28_LSB  0
#define csr_AcsmSeq2x28_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x28_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x28_BITS   15:0
#define csr_AcsmDdrAdrx15x0x28_MSB  15
#define csr_AcsmDdrAdrx15x0x28_LSB  0
#define csr_AcsmDdrAdrx15x0x28_MASK 0xffff
#define csr_RxFifoContentsDBI_RANGE  3:0
#define csr_RxFifoContentsDBI_BITS   3:0
#define csr_RxFifoContentsDBI_MSB  3
#define csr_RxFifoContentsDBI_LSB  0
#define csr_RxFifoContentsDBI_MASK 0xf
#define csr_SequenceReg0b17s1_RANGE  15:0
#define csr_SequenceReg0b17s1_BITS   15:0
#define csr_SequenceReg0b17s1_MSB  15
#define csr_SequenceReg0b17s1_LSB  0
#define csr_SequenceReg0b17s1_MASK 0xffff
#define csr_SequenceReg0b102s2_RANGE  8:0
#define csr_SequenceReg0b102s2_BITS   8:0
#define csr_SequenceReg0b102s2_MSB  8
#define csr_SequenceReg0b102s2_LSB  0
#define csr_SequenceReg0b102s2_MASK 0x1ff
#define csr_AcsmSeq2x29_RANGE  15:0
#define csr_AcsmSeq2x29_BITS   15:0
#define csr_AcsmSeq2x29_MSB  15
#define csr_AcsmSeq2x29_LSB  0
#define csr_AcsmSeq2x29_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x29_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x29_BITS   15:0
#define csr_AcsmDdrAdrx15x0x29_MSB  15
#define csr_AcsmDdrAdrx15x0x29_LSB  0
#define csr_AcsmDdrAdrx15x0x29_MASK 0xffff
#define csr_SequenceReg0b17s2_RANGE  8:0
#define csr_SequenceReg0b17s2_BITS   8:0
#define csr_SequenceReg0b17s2_MSB  8
#define csr_SequenceReg0b17s2_LSB  0
#define csr_SequenceReg0b17s2_MASK 0x1ff
#define csr_SequenceReg0b103s0_RANGE  15:0
#define csr_SequenceReg0b103s0_BITS   15:0
#define csr_SequenceReg0b103s0_MSB  15
#define csr_SequenceReg0b103s0_LSB  0
#define csr_SequenceReg0b103s0_MASK 0xffff
#define csr_AcsmSeq2x30_RANGE  15:0
#define csr_AcsmSeq2x30_BITS   15:0
#define csr_AcsmSeq2x30_MSB  15
#define csr_AcsmSeq2x30_LSB  0
#define csr_AcsmSeq2x30_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x30_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x30_BITS   15:0
#define csr_AcsmDdrAdrx15x0x30_MSB  15
#define csr_AcsmDdrAdrx15x0x30_LSB  0
#define csr_AcsmDdrAdrx15x0x30_MASK 0xffff
#define csr_SequenceReg0b18s0_RANGE  15:0
#define csr_SequenceReg0b18s0_BITS   15:0
#define csr_SequenceReg0b18s0_MSB  15
#define csr_SequenceReg0b18s0_LSB  0
#define csr_SequenceReg0b18s0_MASK 0xffff
#define csr_SequenceReg0b103s1_RANGE  15:0
#define csr_SequenceReg0b103s1_BITS   15:0
#define csr_SequenceReg0b103s1_MSB  15
#define csr_SequenceReg0b103s1_LSB  0
#define csr_SequenceReg0b103s1_MASK 0xffff
#define csr_AcsmSeq2x31_RANGE  15:0
#define csr_AcsmSeq2x31_BITS   15:0
#define csr_AcsmSeq2x31_MSB  15
#define csr_AcsmSeq2x31_LSB  0
#define csr_AcsmSeq2x31_MASK 0xffff
#define csr_AcsmDdrAdrx15x0x31_RANGE  15:0
#define csr_AcsmDdrAdrx15x0x31_BITS   15:0
#define csr_AcsmDdrAdrx15x0x31_MSB  15
#define csr_AcsmDdrAdrx15x0x31_LSB  0
#define csr_AcsmDdrAdrx15x0x31_MASK 0xffff
#define csr_TxSlewRate_RANGE  10:0
#define csr_TxSlewRate_BITS   10:0
#define csr_TxSlewRate_MSB  10
#define csr_TxSlewRate_LSB  0
#define csr_TxSlewRate_MASK 0x7ff
#define csr_TxPreP_RANGE  3:0
#define csr_TxPreP_BITS   3:0
#define csr_TxPreP_MSB  3
#define csr_TxPreP_LSB  0
#define csr_TxPreP_MASK 0xf
#define csr_TxPreN_RANGE  7:4
#define csr_TxPreN_BITS   3:0
#define csr_TxPreN_MSB  7
#define csr_TxPreN_LSB  4
#define csr_TxPreN_MASK 0xf0
#define csr_TxPreDrvMode_RANGE  10:8
#define csr_TxPreDrvMode_BITS   2:0
#define csr_TxPreDrvMode_MSB  10
#define csr_TxPreDrvMode_LSB  8
#define csr_TxPreDrvMode_MASK 0x700
#define csr_PrbsGenCtl_RANGE  6:0
#define csr_PrbsGenCtl_BITS   6:0
#define csr_PrbsGenCtl_MSB  6
#define csr_PrbsGenCtl_LSB  0
#define csr_PrbsGenCtl_MASK 0x7f
#define csr_PpgcMode_RANGE  0:0
#define csr_PpgcMode_BITS   0:0
#define csr_PpgcMode_MSB  0
#define csr_PpgcMode_LSB  0
#define csr_PpgcMode_MASK 0x1
#define csr_PpgcDmMode_RANGE  1:1
#define csr_PpgcDmMode_BITS   0:0
#define csr_PpgcDmMode_MSB  1
#define csr_PpgcDmMode_LSB  1
#define csr_PpgcDmMode_MASK 0x2
#define csr_PpgcLdffMode_RANGE  2:2
#define csr_PpgcLdffMode_BITS   0:0
#define csr_PpgcLdffMode_MSB  2
#define csr_PpgcLdffMode_LSB  2
#define csr_PpgcLdffMode_MASK 0x4
#define csr_PpgcSel23bPrbs_RANGE  3:3
#define csr_PpgcSel23bPrbs_BITS   0:0
#define csr_PpgcSel23bPrbs_MSB  3
#define csr_PpgcSel23bPrbs_LSB  3
#define csr_PpgcSel23bPrbs_MASK 0x8
#define csr_PpgcPatAdv_RANGE  5:4
#define csr_PpgcPatAdv_BITS   1:0
#define csr_PpgcPatAdv_MSB  5
#define csr_PpgcPatAdv_LSB  4
#define csr_PpgcPatAdv_MASK 0x30
#define csr_PpgcEnbPatStressMode_RANGE  6:6
#define csr_PpgcEnbPatStressMode_BITS   0:0
#define csr_PpgcEnbPatStressMode_MSB  6
#define csr_PpgcEnbPatStressMode_LSB  6
#define csr_PpgcEnbPatStressMode_MASK 0x40
#define csr_SequenceReg0b18s1_RANGE  15:0
#define csr_SequenceReg0b18s1_BITS   15:0
#define csr_SequenceReg0b18s1_MSB  15
#define csr_SequenceReg0b18s1_LSB  0
#define csr_SequenceReg0b18s1_MASK 0xffff
#define csr_SequenceReg0b103s2_RANGE  8:0
#define csr_SequenceReg0b103s2_BITS   8:0
#define csr_SequenceReg0b103s2_MSB  8
#define csr_SequenceReg0b103s2_LSB  0
#define csr_SequenceReg0b103s2_MASK 0x1ff
#define csr_MemResetL_RANGE  1:0
#define csr_MemResetL_BITS   1:0
#define csr_MemResetL_MSB  1
#define csr_MemResetL_LSB  0
#define csr_MemResetL_MASK 0x3
#define csr_MemResetLValue_RANGE  0:0
#define csr_MemResetLValue_BITS   0:0
#define csr_MemResetLValue_MSB  0
#define csr_MemResetLValue_LSB  0
#define csr_MemResetLValue_MASK 0x1
#define csr_ProtectMemReset_RANGE  1:1
#define csr_ProtectMemReset_BITS   0:0
#define csr_ProtectMemReset_MSB  1
#define csr_ProtectMemReset_LSB  1
#define csr_ProtectMemReset_MASK 0x2
#define csr_AcsmSeq3x0_RANGE  15:0
#define csr_AcsmSeq3x0_BITS   15:0
#define csr_AcsmSeq3x0_MSB  15
#define csr_AcsmSeq3x0_LSB  0
#define csr_AcsmSeq3x0_MASK 0xffff
#define csr_AcsmCmdRepCnt0_RANGE  7:0
#define csr_AcsmCmdRepCnt0_BITS   7:0
#define csr_AcsmCmdRepCnt0_MSB  7
#define csr_AcsmCmdRepCnt0_LSB  0
#define csr_AcsmCmdRepCnt0_MASK 0xff
#define csr_AcsmAdrAdv0_RANGE  9:8
#define csr_AcsmAdrAdv0_BITS   1:0
#define csr_AcsmAdrAdv0_MSB  9
#define csr_AcsmAdrAdv0_LSB  8
#define csr_AcsmAdrAdv0_MASK 0x300
#define csr_AcsmBnkAdv0_RANGE  11:10
#define csr_AcsmBnkAdv0_BITS   1:0
#define csr_AcsmBnkAdv0_MSB  11
#define csr_AcsmBnkAdv0_LSB  10
#define csr_AcsmBnkAdv0_MASK 0xc00
#define csr_AcsmAdrSelLoad0_RANGE  13:12
#define csr_AcsmAdrSelLoad0_BITS   1:0
#define csr_AcsmAdrSelLoad0_MSB  13
#define csr_AcsmAdrSelLoad0_LSB  12
#define csr_AcsmAdrSelLoad0_MASK 0x3000
#define csr_AcsmBnkSelLoad0_RANGE  14:14
#define csr_AcsmBnkSelLoad0_BITS   0:0
#define csr_AcsmBnkSelLoad0_MSB  14
#define csr_AcsmBnkSelLoad0_LSB  14
#define csr_AcsmBnkSelLoad0_MASK 0x4000
#define csr_AcsmLongBubble0_RANGE  15:15
#define csr_AcsmLongBubble0_BITS   0:0
#define csr_AcsmLongBubble0_MSB  15
#define csr_AcsmLongBubble0_LSB  15
#define csr_AcsmLongBubble0_MASK 0x8000
#define csr_PrbsGenStateLo_RANGE  15:0
#define csr_PrbsGenStateLo_BITS   15:0
#define csr_PrbsGenStateLo_MSB  15
#define csr_PrbsGenStateLo_LSB  0
#define csr_PrbsGenStateLo_MASK 0xffff
#define csr_SequenceReg0b18s2_RANGE  8:0
#define csr_SequenceReg0b18s2_BITS   8:0
#define csr_SequenceReg0b18s2_MSB  8
#define csr_SequenceReg0b18s2_LSB  0
#define csr_SequenceReg0b18s2_MASK 0x1ff
#define csr_SequenceReg0b104s0_RANGE  15:0
#define csr_SequenceReg0b104s0_BITS   15:0
#define csr_SequenceReg0b104s0_MSB  15
#define csr_SequenceReg0b104s0_LSB  0
#define csr_SequenceReg0b104s0_MASK 0xffff
#define csr_AcsmSeq3x1_RANGE  15:0
#define csr_AcsmSeq3x1_BITS   15:0
#define csr_AcsmSeq3x1_MSB  15
#define csr_AcsmSeq3x1_LSB  0
#define csr_AcsmSeq3x1_MASK 0xffff
#define csr_AcsmCmdRepCnt1_RANGE  7:0
#define csr_AcsmCmdRepCnt1_BITS   7:0
#define csr_AcsmCmdRepCnt1_MSB  7
#define csr_AcsmCmdRepCnt1_LSB  0
#define csr_AcsmCmdRepCnt1_MASK 0xff
#define csr_AcsmAdrAdv1_RANGE  9:8
#define csr_AcsmAdrAdv1_BITS   1:0
#define csr_AcsmAdrAdv1_MSB  9
#define csr_AcsmAdrAdv1_LSB  8
#define csr_AcsmAdrAdv1_MASK 0x300
#define csr_AcsmBnkAdv1_RANGE  11:10
#define csr_AcsmBnkAdv1_BITS   1:0
#define csr_AcsmBnkAdv1_MSB  11
#define csr_AcsmBnkAdv1_LSB  10
#define csr_AcsmBnkAdv1_MASK 0xc00
#define csr_AcsmAdrSelLoad1_RANGE  13:12
#define csr_AcsmAdrSelLoad1_BITS   1:0
#define csr_AcsmAdrSelLoad1_MSB  13
#define csr_AcsmAdrSelLoad1_LSB  12
#define csr_AcsmAdrSelLoad1_MASK 0x3000
#define csr_AcsmBnkSelLoad1_RANGE  14:14
#define csr_AcsmBnkSelLoad1_BITS   0:0
#define csr_AcsmBnkSelLoad1_MSB  14
#define csr_AcsmBnkSelLoad1_LSB  14
#define csr_AcsmBnkSelLoad1_MASK 0x4000
#define csr_AcsmLongBubble1_RANGE  15:15
#define csr_AcsmLongBubble1_BITS   0:0
#define csr_AcsmLongBubble1_MSB  15
#define csr_AcsmLongBubble1_LSB  15
#define csr_AcsmLongBubble1_MASK 0x8000
#define csr_TrainingIncDecDtsmEn_RANGE  8:0
#define csr_TrainingIncDecDtsmEn_BITS   8:0
#define csr_TrainingIncDecDtsmEn_MSB  8
#define csr_TrainingIncDecDtsmEn_LSB  0
#define csr_TrainingIncDecDtsmEn_MASK 0x1ff
#define csr_PrbsGenStateHi_RANGE  6:0
#define csr_PrbsGenStateHi_BITS   6:0
#define csr_PrbsGenStateHi_MSB  6
#define csr_PrbsGenStateHi_LSB  0
#define csr_PrbsGenStateHi_MASK 0x7f
#define csr_SequenceReg0b19s0_RANGE  15:0
#define csr_SequenceReg0b19s0_BITS   15:0
#define csr_SequenceReg0b19s0_MSB  15
#define csr_SequenceReg0b19s0_LSB  0
#define csr_SequenceReg0b19s0_MASK 0xffff
#define csr_SequenceReg0b104s1_RANGE  15:0
#define csr_SequenceReg0b104s1_BITS   15:0
#define csr_SequenceReg0b104s1_MSB  15
#define csr_SequenceReg0b104s1_LSB  0
#define csr_SequenceReg0b104s1_MASK 0xffff
#define csr_AcsmSeq3x2_RANGE  15:0
#define csr_AcsmSeq3x2_BITS   15:0
#define csr_AcsmSeq3x2_MSB  15
#define csr_AcsmSeq3x2_LSB  0
#define csr_AcsmSeq3x2_MASK 0xffff
#define csr_AcsmCmdRepCnt2_RANGE  7:0
#define csr_AcsmCmdRepCnt2_BITS   7:0
#define csr_AcsmCmdRepCnt2_MSB  7
#define csr_AcsmCmdRepCnt2_LSB  0
#define csr_AcsmCmdRepCnt2_MASK 0xff
#define csr_AcsmAdrAdv2_RANGE  9:8
#define csr_AcsmAdrAdv2_BITS   1:0
#define csr_AcsmAdrAdv2_MSB  9
#define csr_AcsmAdrAdv2_LSB  8
#define csr_AcsmAdrAdv2_MASK 0x300
#define csr_AcsmBnkAdv2_RANGE  11:10
#define csr_AcsmBnkAdv2_BITS   1:0
#define csr_AcsmBnkAdv2_MSB  11
#define csr_AcsmBnkAdv2_LSB  10
#define csr_AcsmBnkAdv2_MASK 0xc00
#define csr_AcsmAdrSelLoad2_RANGE  13:12
#define csr_AcsmAdrSelLoad2_BITS   1:0
#define csr_AcsmAdrSelLoad2_MSB  13
#define csr_AcsmAdrSelLoad2_LSB  12
#define csr_AcsmAdrSelLoad2_MASK 0x3000
#define csr_AcsmBnkSelLoad2_RANGE  14:14
#define csr_AcsmBnkSelLoad2_BITS   0:0
#define csr_AcsmBnkSelLoad2_MSB  14
#define csr_AcsmBnkSelLoad2_LSB  14
#define csr_AcsmBnkSelLoad2_MASK 0x4000
#define csr_AcsmLongBubble2_RANGE  15:15
#define csr_AcsmLongBubble2_BITS   0:0
#define csr_AcsmLongBubble2_MSB  15
#define csr_AcsmLongBubble2_LSB  15
#define csr_AcsmLongBubble2_MASK 0x8000
#define csr_PrbsChkStateLo_RANGE  15:0
#define csr_PrbsChkStateLo_BITS   15:0
#define csr_PrbsChkStateLo_MSB  15
#define csr_PrbsChkStateLo_LSB  0
#define csr_PrbsChkStateLo_MASK 0xffff
#define csr_SequenceReg0b19s1_RANGE  15:0
#define csr_SequenceReg0b19s1_BITS   15:0
#define csr_SequenceReg0b19s1_MSB  15
#define csr_SequenceReg0b19s1_LSB  0
#define csr_SequenceReg0b19s1_MASK 0xffff
#define csr_SequenceReg0b104s2_RANGE  8:0
#define csr_SequenceReg0b104s2_BITS   8:0
#define csr_SequenceReg0b104s2_MSB  8
#define csr_SequenceReg0b104s2_LSB  0
#define csr_SequenceReg0b104s2_MASK 0x1ff
#define csr_AcsmSeq3x3_RANGE  15:0
#define csr_AcsmSeq3x3_BITS   15:0
#define csr_AcsmSeq3x3_MSB  15
#define csr_AcsmSeq3x3_LSB  0
#define csr_AcsmSeq3x3_MASK 0xffff
#define csr_AcsmCmdRepCnt3_RANGE  7:0
#define csr_AcsmCmdRepCnt3_BITS   7:0
#define csr_AcsmCmdRepCnt3_MSB  7
#define csr_AcsmCmdRepCnt3_LSB  0
#define csr_AcsmCmdRepCnt3_MASK 0xff
#define csr_AcsmAdrAdv3_RANGE  9:8
#define csr_AcsmAdrAdv3_BITS   1:0
#define csr_AcsmAdrAdv3_MSB  9
#define csr_AcsmAdrAdv3_LSB  8
#define csr_AcsmAdrAdv3_MASK 0x300
#define csr_AcsmBnkAdv3_RANGE  11:10
#define csr_AcsmBnkAdv3_BITS   1:0
#define csr_AcsmBnkAdv3_MSB  11
#define csr_AcsmBnkAdv3_LSB  10
#define csr_AcsmBnkAdv3_MASK 0xc00
#define csr_AcsmAdrSelLoad3_RANGE  13:12
#define csr_AcsmAdrSelLoad3_BITS   1:0
#define csr_AcsmAdrSelLoad3_MSB  13
#define csr_AcsmAdrSelLoad3_LSB  12
#define csr_AcsmAdrSelLoad3_MASK 0x3000
#define csr_AcsmBnkSelLoad3_RANGE  14:14
#define csr_AcsmBnkSelLoad3_BITS   0:0
#define csr_AcsmBnkSelLoad3_MSB  14
#define csr_AcsmBnkSelLoad3_LSB  14
#define csr_AcsmBnkSelLoad3_MASK 0x4000
#define csr_AcsmLongBubble3_RANGE  15:15
#define csr_AcsmLongBubble3_BITS   0:0
#define csr_AcsmLongBubble3_MSB  15
#define csr_AcsmLongBubble3_LSB  15
#define csr_AcsmLongBubble3_MASK 0x8000
#define csr_PrbsChkStateHi_RANGE  6:0
#define csr_PrbsChkStateHi_BITS   6:0
#define csr_PrbsChkStateHi_MSB  6
#define csr_PrbsChkStateHi_LSB  0
#define csr_PrbsChkStateHi_MASK 0x7f
#define csr_SequenceReg0b19s2_RANGE  8:0
#define csr_SequenceReg0b19s2_BITS   8:0
#define csr_SequenceReg0b19s2_MSB  8
#define csr_SequenceReg0b19s2_LSB  0
#define csr_SequenceReg0b19s2_MASK 0x1ff
#define csr_SequenceReg0b105s0_RANGE  15:0
#define csr_SequenceReg0b105s0_BITS   15:0
#define csr_SequenceReg0b105s0_MSB  15
#define csr_SequenceReg0b105s0_LSB  0
#define csr_SequenceReg0b105s0_MASK 0xffff
#define csr_AcsmSeq3x4_RANGE  15:0
#define csr_AcsmSeq3x4_BITS   15:0
#define csr_AcsmSeq3x4_MSB  15
#define csr_AcsmSeq3x4_LSB  0
#define csr_AcsmSeq3x4_MASK 0xffff
#define csr_AcsmCmdRepCnt4_RANGE  7:0
#define csr_AcsmCmdRepCnt4_BITS   7:0
#define csr_AcsmCmdRepCnt4_MSB  7
#define csr_AcsmCmdRepCnt4_LSB  0
#define csr_AcsmCmdRepCnt4_MASK 0xff
#define csr_AcsmAdrAdv4_RANGE  9:8
#define csr_AcsmAdrAdv4_BITS   1:0
#define csr_AcsmAdrAdv4_MSB  9
#define csr_AcsmAdrAdv4_LSB  8
#define csr_AcsmAdrAdv4_MASK 0x300
#define csr_AcsmBnkAdv4_RANGE  11:10
#define csr_AcsmBnkAdv4_BITS   1:0
#define csr_AcsmBnkAdv4_MSB  11
#define csr_AcsmBnkAdv4_LSB  10
#define csr_AcsmBnkAdv4_MASK 0xc00
#define csr_AcsmAdrSelLoad4_RANGE  13:12
#define csr_AcsmAdrSelLoad4_BITS   1:0
#define csr_AcsmAdrSelLoad4_MSB  13
#define csr_AcsmAdrSelLoad4_LSB  12
#define csr_AcsmAdrSelLoad4_MASK 0x3000
#define csr_AcsmBnkSelLoad4_RANGE  14:14
#define csr_AcsmBnkSelLoad4_BITS   0:0
#define csr_AcsmBnkSelLoad4_MSB  14
#define csr_AcsmBnkSelLoad4_LSB  14
#define csr_AcsmBnkSelLoad4_MASK 0x4000
#define csr_AcsmLongBubble4_RANGE  15:15
#define csr_AcsmLongBubble4_BITS   0:0
#define csr_AcsmLongBubble4_MSB  15
#define csr_AcsmLongBubble4_LSB  15
#define csr_AcsmLongBubble4_MASK 0x8000
#define csr_PrbsGenCtl1_RANGE  8:0
#define csr_PrbsGenCtl1_BITS   8:0
#define csr_PrbsGenCtl1_MSB  8
#define csr_PrbsGenCtl1_LSB  0
#define csr_PrbsGenCtl1_MASK 0x1ff
#define csr_PpgcModeLane_RANGE  8:0
#define csr_PpgcModeLane_BITS   8:0
#define csr_PpgcModeLane_MSB  8
#define csr_PpgcModeLane_LSB  0
#define csr_PpgcModeLane_MASK 0x1ff
#define csr_SequenceReg0b20s0_RANGE  15:0
#define csr_SequenceReg0b20s0_BITS   15:0
#define csr_SequenceReg0b20s0_MSB  15
#define csr_SequenceReg0b20s0_LSB  0
#define csr_SequenceReg0b20s0_MASK 0xffff
#define csr_SequenceReg0b105s1_RANGE  15:0
#define csr_SequenceReg0b105s1_BITS   15:0
#define csr_SequenceReg0b105s1_MSB  15
#define csr_SequenceReg0b105s1_LSB  0
#define csr_SequenceReg0b105s1_MASK 0xffff
#define csr_AcsmSeq3x5_RANGE  15:0
#define csr_AcsmSeq3x5_BITS   15:0
#define csr_AcsmSeq3x5_MSB  15
#define csr_AcsmSeq3x5_LSB  0
#define csr_AcsmSeq3x5_MASK 0xffff
#define csr_AcsmCmdRepCnt5_RANGE  7:0
#define csr_AcsmCmdRepCnt5_BITS   7:0
#define csr_AcsmCmdRepCnt5_MSB  7
#define csr_AcsmCmdRepCnt5_LSB  0
#define csr_AcsmCmdRepCnt5_MASK 0xff
#define csr_AcsmAdrAdv5_RANGE  9:8
#define csr_AcsmAdrAdv5_BITS   1:0
#define csr_AcsmAdrAdv5_MSB  9
#define csr_AcsmAdrAdv5_LSB  8
#define csr_AcsmAdrAdv5_MASK 0x300
#define csr_AcsmBnkAdv5_RANGE  11:10
#define csr_AcsmBnkAdv5_BITS   1:0
#define csr_AcsmBnkAdv5_MSB  11
#define csr_AcsmBnkAdv5_LSB  10
#define csr_AcsmBnkAdv5_MASK 0xc00
#define csr_AcsmAdrSelLoad5_RANGE  13:12
#define csr_AcsmAdrSelLoad5_BITS   1:0
#define csr_AcsmAdrSelLoad5_MSB  13
#define csr_AcsmAdrSelLoad5_LSB  12
#define csr_AcsmAdrSelLoad5_MASK 0x3000
#define csr_AcsmBnkSelLoad5_RANGE  14:14
#define csr_AcsmBnkSelLoad5_BITS   0:0
#define csr_AcsmBnkSelLoad5_MSB  14
#define csr_AcsmBnkSelLoad5_LSB  14
#define csr_AcsmBnkSelLoad5_MASK 0x4000
#define csr_AcsmLongBubble5_RANGE  15:15
#define csr_AcsmLongBubble5_BITS   0:0
#define csr_AcsmLongBubble5_MSB  15
#define csr_AcsmLongBubble5_LSB  15
#define csr_AcsmLongBubble5_MASK 0x8000
#define csr_PrbsGenCtl2_RANGE  15:0
#define csr_PrbsGenCtl2_BITS   15:0
#define csr_PrbsGenCtl2_MSB  15
#define csr_PrbsGenCtl2_LSB  0
#define csr_PrbsGenCtl2_MASK 0xffff
#define csr_PpgcMskPeriodLim_RANGE  15:0
#define csr_PpgcMskPeriodLim_BITS   15:0
#define csr_PpgcMskPeriodLim_MSB  15
#define csr_PpgcMskPeriodLim_LSB  0
#define csr_PpgcMskPeriodLim_MASK 0xffff
#define csr_SequenceReg0b20s1_RANGE  15:0
#define csr_SequenceReg0b20s1_BITS   15:0
#define csr_SequenceReg0b20s1_MSB  15
#define csr_SequenceReg0b20s1_LSB  0
#define csr_SequenceReg0b20s1_MASK 0xffff
#define csr_SequenceReg0b105s2_RANGE  8:0
#define csr_SequenceReg0b105s2_BITS   8:0
#define csr_SequenceReg0b105s2_MSB  8
#define csr_SequenceReg0b105s2_LSB  0
#define csr_SequenceReg0b105s2_MASK 0x1ff
#define csr_AcsmSeq3x6_RANGE  15:0
#define csr_AcsmSeq3x6_BITS   15:0
#define csr_AcsmSeq3x6_MSB  15
#define csr_AcsmSeq3x6_LSB  0
#define csr_AcsmSeq3x6_MASK 0xffff
#define csr_AcsmCmdRepCnt6_RANGE  7:0
#define csr_AcsmCmdRepCnt6_BITS   7:0
#define csr_AcsmCmdRepCnt6_MSB  7
#define csr_AcsmCmdRepCnt6_LSB  0
#define csr_AcsmCmdRepCnt6_MASK 0xff
#define csr_AcsmAdrAdv6_RANGE  9:8
#define csr_AcsmAdrAdv6_BITS   1:0
#define csr_AcsmAdrAdv6_MSB  9
#define csr_AcsmAdrAdv6_LSB  8
#define csr_AcsmAdrAdv6_MASK 0x300
#define csr_AcsmBnkAdv6_RANGE  11:10
#define csr_AcsmBnkAdv6_BITS   1:0
#define csr_AcsmBnkAdv6_MSB  11
#define csr_AcsmBnkAdv6_LSB  10
#define csr_AcsmBnkAdv6_MASK 0xc00
#define csr_AcsmAdrSelLoad6_RANGE  13:12
#define csr_AcsmAdrSelLoad6_BITS   1:0
#define csr_AcsmAdrSelLoad6_MSB  13
#define csr_AcsmAdrSelLoad6_LSB  12
#define csr_AcsmAdrSelLoad6_MASK 0x3000
#define csr_AcsmBnkSelLoad6_RANGE  14:14
#define csr_AcsmBnkSelLoad6_BITS   0:0
#define csr_AcsmBnkSelLoad6_MSB  14
#define csr_AcsmBnkSelLoad6_LSB  14
#define csr_AcsmBnkSelLoad6_MASK 0x4000
#define csr_AcsmLongBubble6_RANGE  15:15
#define csr_AcsmLongBubble6_BITS   0:0
#define csr_AcsmLongBubble6_MSB  15
#define csr_AcsmLongBubble6_LSB  15
#define csr_AcsmLongBubble6_MASK 0x8000
#define csr_SequenceReg0b20s2_RANGE  8:0
#define csr_SequenceReg0b20s2_BITS   8:0
#define csr_SequenceReg0b20s2_MSB  8
#define csr_SequenceReg0b20s2_LSB  0
#define csr_SequenceReg0b20s2_MASK 0x1ff
#define csr_SequenceReg0b106s0_RANGE  15:0
#define csr_SequenceReg0b106s0_BITS   15:0
#define csr_SequenceReg0b106s0_MSB  15
#define csr_SequenceReg0b106s0_LSB  0
#define csr_SequenceReg0b106s0_MASK 0xffff
#define csr_AcsmSeq3x7_RANGE  15:0
#define csr_AcsmSeq3x7_BITS   15:0
#define csr_AcsmSeq3x7_MSB  15
#define csr_AcsmSeq3x7_LSB  0
#define csr_AcsmSeq3x7_MASK 0xffff
#define csr_AcsmCmdRepCnt7_RANGE  7:0
#define csr_AcsmCmdRepCnt7_BITS   7:0
#define csr_AcsmCmdRepCnt7_MSB  7
#define csr_AcsmCmdRepCnt7_LSB  0
#define csr_AcsmCmdRepCnt7_MASK 0xff
#define csr_AcsmAdrAdv7_RANGE  9:8
#define csr_AcsmAdrAdv7_BITS   1:0
#define csr_AcsmAdrAdv7_MSB  9
#define csr_AcsmAdrAdv7_LSB  8
#define csr_AcsmAdrAdv7_MASK 0x300
#define csr_AcsmBnkAdv7_RANGE  11:10
#define csr_AcsmBnkAdv7_BITS   1:0
#define csr_AcsmBnkAdv7_MSB  11
#define csr_AcsmBnkAdv7_LSB  10
#define csr_AcsmBnkAdv7_MASK 0xc00
#define csr_AcsmAdrSelLoad7_RANGE  13:12
#define csr_AcsmAdrSelLoad7_BITS   1:0
#define csr_AcsmAdrSelLoad7_MSB  13
#define csr_AcsmAdrSelLoad7_LSB  12
#define csr_AcsmAdrSelLoad7_MASK 0x3000
#define csr_AcsmBnkSelLoad7_RANGE  14:14
#define csr_AcsmBnkSelLoad7_BITS   0:0
#define csr_AcsmBnkSelLoad7_MSB  14
#define csr_AcsmBnkSelLoad7_LSB  14
#define csr_AcsmBnkSelLoad7_MASK 0x4000
#define csr_AcsmLongBubble7_RANGE  15:15
#define csr_AcsmLongBubble7_BITS   0:0
#define csr_AcsmLongBubble7_MSB  15
#define csr_AcsmLongBubble7_LSB  15
#define csr_AcsmLongBubble7_MASK 0x8000
#define csr_RxPBDlyTg0_RANGE  6:0
#define csr_RxPBDlyTg0_BITS   6:0
#define csr_RxPBDlyTg0_MSB  6
#define csr_RxPBDlyTg0_LSB  0
#define csr_RxPBDlyTg0_MASK 0x7f
#define csr_SequenceReg0b21s0_RANGE  15:0
#define csr_SequenceReg0b21s0_BITS   15:0
#define csr_SequenceReg0b21s0_MSB  15
#define csr_SequenceReg0b21s0_LSB  0
#define csr_SequenceReg0b21s0_MASK 0xffff
#define csr_SequenceReg0b106s1_RANGE  15:0
#define csr_SequenceReg0b106s1_BITS   15:0
#define csr_SequenceReg0b106s1_MSB  15
#define csr_SequenceReg0b106s1_LSB  0
#define csr_SequenceReg0b106s1_MASK 0xffff
#define csr_AcsmSeq3x8_RANGE  15:0
#define csr_AcsmSeq3x8_BITS   15:0
#define csr_AcsmSeq3x8_MSB  15
#define csr_AcsmSeq3x8_LSB  0
#define csr_AcsmSeq3x8_MASK 0xffff
#define csr_AcsmCmdRepCnt8_RANGE  7:0
#define csr_AcsmCmdRepCnt8_BITS   7:0
#define csr_AcsmCmdRepCnt8_MSB  7
#define csr_AcsmCmdRepCnt8_LSB  0
#define csr_AcsmCmdRepCnt8_MASK 0xff
#define csr_AcsmAdrAdv8_RANGE  9:8
#define csr_AcsmAdrAdv8_BITS   1:0
#define csr_AcsmAdrAdv8_MSB  9
#define csr_AcsmAdrAdv8_LSB  8
#define csr_AcsmAdrAdv8_MASK 0x300
#define csr_AcsmBnkAdv8_RANGE  11:10
#define csr_AcsmBnkAdv8_BITS   1:0
#define csr_AcsmBnkAdv8_MSB  11
#define csr_AcsmBnkAdv8_LSB  10
#define csr_AcsmBnkAdv8_MASK 0xc00
#define csr_AcsmAdrSelLoad8_RANGE  13:12
#define csr_AcsmAdrSelLoad8_BITS   1:0
#define csr_AcsmAdrSelLoad8_MSB  13
#define csr_AcsmAdrSelLoad8_LSB  12
#define csr_AcsmAdrSelLoad8_MASK 0x3000
#define csr_AcsmBnkSelLoad8_RANGE  14:14
#define csr_AcsmBnkSelLoad8_BITS   0:0
#define csr_AcsmBnkSelLoad8_MSB  14
#define csr_AcsmBnkSelLoad8_LSB  14
#define csr_AcsmBnkSelLoad8_MASK 0x4000
#define csr_AcsmLongBubble8_RANGE  15:15
#define csr_AcsmLongBubble8_BITS   0:0
#define csr_AcsmLongBubble8_MSB  15
#define csr_AcsmLongBubble8_LSB  15
#define csr_AcsmLongBubble8_MASK 0x8000
#define csr_RxPBDlyTg1_RANGE  6:0
#define csr_RxPBDlyTg1_BITS   6:0
#define csr_RxPBDlyTg1_MSB  6
#define csr_RxPBDlyTg1_LSB  0
#define csr_RxPBDlyTg1_MASK 0x7f
#define csr_SequenceReg0b21s1_RANGE  15:0
#define csr_SequenceReg0b21s1_BITS   15:0
#define csr_SequenceReg0b21s1_MSB  15
#define csr_SequenceReg0b21s1_LSB  0
#define csr_SequenceReg0b21s1_MASK 0xffff
#define csr_SequenceReg0b106s2_RANGE  8:0
#define csr_SequenceReg0b106s2_BITS   8:0
#define csr_SequenceReg0b106s2_MSB  8
#define csr_SequenceReg0b106s2_LSB  0
#define csr_SequenceReg0b106s2_MASK 0x1ff
#define csr_AcsmSeq3x9_RANGE  15:0
#define csr_AcsmSeq3x9_BITS   15:0
#define csr_AcsmSeq3x9_MSB  15
#define csr_AcsmSeq3x9_LSB  0
#define csr_AcsmSeq3x9_MASK 0xffff
#define csr_AcsmCmdRepCnt9_RANGE  7:0
#define csr_AcsmCmdRepCnt9_BITS   7:0
#define csr_AcsmCmdRepCnt9_MSB  7
#define csr_AcsmCmdRepCnt9_LSB  0
#define csr_AcsmCmdRepCnt9_MASK 0xff
#define csr_AcsmAdrAdv9_RANGE  9:8
#define csr_AcsmAdrAdv9_BITS   1:0
#define csr_AcsmAdrAdv9_MSB  9
#define csr_AcsmAdrAdv9_LSB  8
#define csr_AcsmAdrAdv9_MASK 0x300
#define csr_AcsmBnkAdv9_RANGE  11:10
#define csr_AcsmBnkAdv9_BITS   1:0
#define csr_AcsmBnkAdv9_MSB  11
#define csr_AcsmBnkAdv9_LSB  10
#define csr_AcsmBnkAdv9_MASK 0xc00
#define csr_AcsmAdrSelLoad9_RANGE  13:12
#define csr_AcsmAdrSelLoad9_BITS   1:0
#define csr_AcsmAdrSelLoad9_MSB  13
#define csr_AcsmAdrSelLoad9_LSB  12
#define csr_AcsmAdrSelLoad9_MASK 0x3000
#define csr_AcsmBnkSelLoad9_RANGE  14:14
#define csr_AcsmBnkSelLoad9_BITS   0:0
#define csr_AcsmBnkSelLoad9_MSB  14
#define csr_AcsmBnkSelLoad9_LSB  14
#define csr_AcsmBnkSelLoad9_MASK 0x4000
#define csr_AcsmLongBubble9_RANGE  15:15
#define csr_AcsmLongBubble9_BITS   0:0
#define csr_AcsmLongBubble9_MSB  15
#define csr_AcsmLongBubble9_LSB  15
#define csr_AcsmLongBubble9_MASK 0x8000
#define csr_RxPBDlyTg2_RANGE  6:0
#define csr_RxPBDlyTg2_BITS   6:0
#define csr_RxPBDlyTg2_MSB  6
#define csr_RxPBDlyTg2_LSB  0
#define csr_RxPBDlyTg2_MASK 0x7f
#define csr_SequenceReg0b21s2_RANGE  8:0
#define csr_SequenceReg0b21s2_BITS   8:0
#define csr_SequenceReg0b21s2_MSB  8
#define csr_SequenceReg0b21s2_LSB  0
#define csr_SequenceReg0b21s2_MASK 0x1ff
#define csr_SequenceReg0b107s0_RANGE  15:0
#define csr_SequenceReg0b107s0_BITS   15:0
#define csr_SequenceReg0b107s0_MSB  15
#define csr_SequenceReg0b107s0_LSB  0
#define csr_SequenceReg0b107s0_MASK 0xffff
#define csr_AcsmSeq3x10_RANGE  15:0
#define csr_AcsmSeq3x10_BITS   15:0
#define csr_AcsmSeq3x10_MSB  15
#define csr_AcsmSeq3x10_LSB  0
#define csr_AcsmSeq3x10_MASK 0xffff
#define csr_AcsmCmdRepCnt10_RANGE  7:0
#define csr_AcsmCmdRepCnt10_BITS   7:0
#define csr_AcsmCmdRepCnt10_MSB  7
#define csr_AcsmCmdRepCnt10_LSB  0
#define csr_AcsmCmdRepCnt10_MASK 0xff
#define csr_AcsmAdrAdv10_RANGE  9:8
#define csr_AcsmAdrAdv10_BITS   1:0
#define csr_AcsmAdrAdv10_MSB  9
#define csr_AcsmAdrAdv10_LSB  8
#define csr_AcsmAdrAdv10_MASK 0x300
#define csr_AcsmBnkAdv10_RANGE  11:10
#define csr_AcsmBnkAdv10_BITS   1:0
#define csr_AcsmBnkAdv10_MSB  11
#define csr_AcsmBnkAdv10_LSB  10
#define csr_AcsmBnkAdv10_MASK 0xc00
#define csr_AcsmAdrSelLoad10_RANGE  13:12
#define csr_AcsmAdrSelLoad10_BITS   1:0
#define csr_AcsmAdrSelLoad10_MSB  13
#define csr_AcsmAdrSelLoad10_LSB  12
#define csr_AcsmAdrSelLoad10_MASK 0x3000
#define csr_AcsmBnkSelLoad10_RANGE  14:14
#define csr_AcsmBnkSelLoad10_BITS   0:0
#define csr_AcsmBnkSelLoad10_MSB  14
#define csr_AcsmBnkSelLoad10_LSB  14
#define csr_AcsmBnkSelLoad10_MASK 0x4000
#define csr_AcsmLongBubble10_RANGE  15:15
#define csr_AcsmLongBubble10_BITS   0:0
#define csr_AcsmLongBubble10_MSB  15
#define csr_AcsmLongBubble10_LSB  15
#define csr_AcsmLongBubble10_MASK 0x8000
#define csr_RxPBDlyTg3_RANGE  6:0
#define csr_RxPBDlyTg3_BITS   6:0
#define csr_RxPBDlyTg3_MSB  6
#define csr_RxPBDlyTg3_LSB  0
#define csr_RxPBDlyTg3_MASK 0x7f
#define csr_SequenceReg0b22s0_RANGE  15:0
#define csr_SequenceReg0b22s0_BITS   15:0
#define csr_SequenceReg0b22s0_MSB  15
#define csr_SequenceReg0b22s0_LSB  0
#define csr_SequenceReg0b22s0_MASK 0xffff
#define csr_SequenceReg0b107s1_RANGE  15:0
#define csr_SequenceReg0b107s1_BITS   15:0
#define csr_SequenceReg0b107s1_MSB  15
#define csr_SequenceReg0b107s1_LSB  0
#define csr_SequenceReg0b107s1_MASK 0xffff
#define csr_AcsmSeq3x11_RANGE  15:0
#define csr_AcsmSeq3x11_BITS   15:0
#define csr_AcsmSeq3x11_MSB  15
#define csr_AcsmSeq3x11_LSB  0
#define csr_AcsmSeq3x11_MASK 0xffff
#define csr_AcsmCmdRepCnt11_RANGE  7:0
#define csr_AcsmCmdRepCnt11_BITS   7:0
#define csr_AcsmCmdRepCnt11_MSB  7
#define csr_AcsmCmdRepCnt11_LSB  0
#define csr_AcsmCmdRepCnt11_MASK 0xff
#define csr_AcsmAdrAdv11_RANGE  9:8
#define csr_AcsmAdrAdv11_BITS   1:0
#define csr_AcsmAdrAdv11_MSB  9
#define csr_AcsmAdrAdv11_LSB  8
#define csr_AcsmAdrAdv11_MASK 0x300
#define csr_AcsmBnkAdv11_RANGE  11:10
#define csr_AcsmBnkAdv11_BITS   1:0
#define csr_AcsmBnkAdv11_MSB  11
#define csr_AcsmBnkAdv11_LSB  10
#define csr_AcsmBnkAdv11_MASK 0xc00
#define csr_AcsmAdrSelLoad11_RANGE  13:12
#define csr_AcsmAdrSelLoad11_BITS   1:0
#define csr_AcsmAdrSelLoad11_MSB  13
#define csr_AcsmAdrSelLoad11_LSB  12
#define csr_AcsmAdrSelLoad11_MASK 0x3000
#define csr_AcsmBnkSelLoad11_RANGE  14:14
#define csr_AcsmBnkSelLoad11_BITS   0:0
#define csr_AcsmBnkSelLoad11_MSB  14
#define csr_AcsmBnkSelLoad11_LSB  14
#define csr_AcsmBnkSelLoad11_MASK 0x4000
#define csr_AcsmLongBubble11_RANGE  15:15
#define csr_AcsmLongBubble11_BITS   0:0
#define csr_AcsmLongBubble11_MSB  15
#define csr_AcsmLongBubble11_LSB  15
#define csr_AcsmLongBubble11_MASK 0x8000
#define csr_SequenceReg0b22s1_RANGE  15:0
#define csr_SequenceReg0b22s1_BITS   15:0
#define csr_SequenceReg0b22s1_MSB  15
#define csr_SequenceReg0b22s1_LSB  0
#define csr_SequenceReg0b22s1_MASK 0xffff
#define csr_SequenceReg0b107s2_RANGE  8:0
#define csr_SequenceReg0b107s2_BITS   8:0
#define csr_SequenceReg0b107s2_MSB  8
#define csr_SequenceReg0b107s2_LSB  0
#define csr_SequenceReg0b107s2_MASK 0x1ff
#define csr_AcsmSeq3x12_RANGE  15:0
#define csr_AcsmSeq3x12_BITS   15:0
#define csr_AcsmSeq3x12_MSB  15
#define csr_AcsmSeq3x12_LSB  0
#define csr_AcsmSeq3x12_MASK 0xffff
#define csr_AcsmCmdRepCnt12_RANGE  7:0
#define csr_AcsmCmdRepCnt12_BITS   7:0
#define csr_AcsmCmdRepCnt12_MSB  7
#define csr_AcsmCmdRepCnt12_LSB  0
#define csr_AcsmCmdRepCnt12_MASK 0xff
#define csr_AcsmAdrAdv12_RANGE  9:8
#define csr_AcsmAdrAdv12_BITS   1:0
#define csr_AcsmAdrAdv12_MSB  9
#define csr_AcsmAdrAdv12_LSB  8
#define csr_AcsmAdrAdv12_MASK 0x300
#define csr_AcsmBnkAdv12_RANGE  11:10
#define csr_AcsmBnkAdv12_BITS   1:0
#define csr_AcsmBnkAdv12_MSB  11
#define csr_AcsmBnkAdv12_LSB  10
#define csr_AcsmBnkAdv12_MASK 0xc00
#define csr_AcsmAdrSelLoad12_RANGE  13:12
#define csr_AcsmAdrSelLoad12_BITS   1:0
#define csr_AcsmAdrSelLoad12_MSB  13
#define csr_AcsmAdrSelLoad12_LSB  12
#define csr_AcsmAdrSelLoad12_MASK 0x3000
#define csr_AcsmBnkSelLoad12_RANGE  14:14
#define csr_AcsmBnkSelLoad12_BITS   0:0
#define csr_AcsmBnkSelLoad12_MSB  14
#define csr_AcsmBnkSelLoad12_LSB  14
#define csr_AcsmBnkSelLoad12_MASK 0x4000
#define csr_AcsmLongBubble12_RANGE  15:15
#define csr_AcsmLongBubble12_BITS   0:0
#define csr_AcsmLongBubble12_MSB  15
#define csr_AcsmLongBubble12_LSB  15
#define csr_AcsmLongBubble12_MASK 0x8000
#define csr_SequenceReg0b22s2_RANGE  8:0
#define csr_SequenceReg0b22s2_BITS   8:0
#define csr_SequenceReg0b22s2_MSB  8
#define csr_SequenceReg0b22s2_LSB  0
#define csr_SequenceReg0b22s2_MASK 0x1ff
#define csr_SequenceReg0b108s0_RANGE  15:0
#define csr_SequenceReg0b108s0_BITS   15:0
#define csr_SequenceReg0b108s0_MSB  15
#define csr_SequenceReg0b108s0_LSB  0
#define csr_SequenceReg0b108s0_MASK 0xffff
#define csr_AcsmSeq3x13_RANGE  15:0
#define csr_AcsmSeq3x13_BITS   15:0
#define csr_AcsmSeq3x13_MSB  15
#define csr_AcsmSeq3x13_LSB  0
#define csr_AcsmSeq3x13_MASK 0xffff
#define csr_AcsmCmdRepCnt13_RANGE  7:0
#define csr_AcsmCmdRepCnt13_BITS   7:0
#define csr_AcsmCmdRepCnt13_MSB  7
#define csr_AcsmCmdRepCnt13_LSB  0
#define csr_AcsmCmdRepCnt13_MASK 0xff
#define csr_AcsmAdrAdv13_RANGE  9:8
#define csr_AcsmAdrAdv13_BITS   1:0
#define csr_AcsmAdrAdv13_MSB  9
#define csr_AcsmAdrAdv13_LSB  8
#define csr_AcsmAdrAdv13_MASK 0x300
#define csr_AcsmBnkAdv13_RANGE  11:10
#define csr_AcsmBnkAdv13_BITS   1:0
#define csr_AcsmBnkAdv13_MSB  11
#define csr_AcsmBnkAdv13_LSB  10
#define csr_AcsmBnkAdv13_MASK 0xc00
#define csr_AcsmAdrSelLoad13_RANGE  13:12
#define csr_AcsmAdrSelLoad13_BITS   1:0
#define csr_AcsmAdrSelLoad13_MSB  13
#define csr_AcsmAdrSelLoad13_LSB  12
#define csr_AcsmAdrSelLoad13_MASK 0x3000
#define csr_AcsmBnkSelLoad13_RANGE  14:14
#define csr_AcsmBnkSelLoad13_BITS   0:0
#define csr_AcsmBnkSelLoad13_MSB  14
#define csr_AcsmBnkSelLoad13_LSB  14
#define csr_AcsmBnkSelLoad13_MASK 0x4000
#define csr_AcsmLongBubble13_RANGE  15:15
#define csr_AcsmLongBubble13_BITS   0:0
#define csr_AcsmLongBubble13_MSB  15
#define csr_AcsmLongBubble13_LSB  15
#define csr_AcsmLongBubble13_MASK 0x8000
#define csr_SequenceReg0b23s0_RANGE  15:0
#define csr_SequenceReg0b23s0_BITS   15:0
#define csr_SequenceReg0b23s0_MSB  15
#define csr_SequenceReg0b23s0_LSB  0
#define csr_SequenceReg0b23s0_MASK 0xffff
#define csr_SequenceReg0b108s1_RANGE  15:0
#define csr_SequenceReg0b108s1_BITS   15:0
#define csr_SequenceReg0b108s1_MSB  15
#define csr_SequenceReg0b108s1_LSB  0
#define csr_SequenceReg0b108s1_MASK 0xffff
#define csr_PUBMODE_RANGE  0:0
#define csr_PUBMODE_BITS   0:0
#define csr_PUBMODE_MSB  0
#define csr_PUBMODE_LSB  0
#define csr_PUBMODE_MASK 0x1
#define csr_HwtMemSrc_RANGE  0:0
#define csr_HwtMemSrc_BITS   0:0
#define csr_HwtMemSrc_MSB  0
#define csr_HwtMemSrc_LSB  0
#define csr_HwtMemSrc_MASK 0x1
#define csr_AcsmSeq3x14_RANGE  15:0
#define csr_AcsmSeq3x14_BITS   15:0
#define csr_AcsmSeq3x14_MSB  15
#define csr_AcsmSeq3x14_LSB  0
#define csr_AcsmSeq3x14_MASK 0xffff
#define csr_AcsmCmdRepCnt14_RANGE  7:0
#define csr_AcsmCmdRepCnt14_BITS   7:0
#define csr_AcsmCmdRepCnt14_MSB  7
#define csr_AcsmCmdRepCnt14_LSB  0
#define csr_AcsmCmdRepCnt14_MASK 0xff
#define csr_AcsmAdrAdv14_RANGE  9:8
#define csr_AcsmAdrAdv14_BITS   1:0
#define csr_AcsmAdrAdv14_MSB  9
#define csr_AcsmAdrAdv14_LSB  8
#define csr_AcsmAdrAdv14_MASK 0x300
#define csr_AcsmBnkAdv14_RANGE  11:10
#define csr_AcsmBnkAdv14_BITS   1:0
#define csr_AcsmBnkAdv14_MSB  11
#define csr_AcsmBnkAdv14_LSB  10
#define csr_AcsmBnkAdv14_MASK 0xc00
#define csr_AcsmAdrSelLoad14_RANGE  13:12
#define csr_AcsmAdrSelLoad14_BITS   1:0
#define csr_AcsmAdrSelLoad14_MSB  13
#define csr_AcsmAdrSelLoad14_LSB  12
#define csr_AcsmAdrSelLoad14_MASK 0x3000
#define csr_AcsmBnkSelLoad14_RANGE  14:14
#define csr_AcsmBnkSelLoad14_BITS   0:0
#define csr_AcsmBnkSelLoad14_MSB  14
#define csr_AcsmBnkSelLoad14_LSB  14
#define csr_AcsmBnkSelLoad14_MASK 0x4000
#define csr_AcsmLongBubble14_RANGE  15:15
#define csr_AcsmLongBubble14_BITS   0:0
#define csr_AcsmLongBubble14_MSB  15
#define csr_AcsmLongBubble14_LSB  15
#define csr_AcsmLongBubble14_MASK 0x8000
#define csr_SequenceReg0b23s1_RANGE  15:0
#define csr_SequenceReg0b23s1_BITS   15:0
#define csr_SequenceReg0b23s1_MSB  15
#define csr_SequenceReg0b23s1_LSB  0
#define csr_SequenceReg0b23s1_MASK 0xffff
#define csr_SequenceReg0b108s2_RANGE  8:0
#define csr_SequenceReg0b108s2_BITS   8:0
#define csr_SequenceReg0b108s2_MSB  8
#define csr_SequenceReg0b108s2_LSB  0
#define csr_SequenceReg0b108s2_MASK 0x1ff
#define csr_MiscPhyStatus_RANGE  1:0
#define csr_MiscPhyStatus_BITS   1:0
#define csr_MiscPhyStatus_MSB  1
#define csr_MiscPhyStatus_LSB  0
#define csr_MiscPhyStatus_MASK 0x3
#define csr_DctSane_RANGE  0:0
#define csr_DctSane_BITS   0:0
#define csr_DctSane_MSB  0
#define csr_DctSane_LSB  0
#define csr_DctSane_MASK 0x1
#define csr_PORMemReset_RANGE  1:1
#define csr_PORMemReset_BITS   0:0
#define csr_PORMemReset_MSB  1
#define csr_PORMemReset_LSB  1
#define csr_PORMemReset_MASK 0x2
#define csr_AcsmSeq3x15_RANGE  15:0
#define csr_AcsmSeq3x15_BITS   15:0
#define csr_AcsmSeq3x15_MSB  15
#define csr_AcsmSeq3x15_LSB  0
#define csr_AcsmSeq3x15_MASK 0xffff
#define csr_AcsmCmdRepCnt15_RANGE  7:0
#define csr_AcsmCmdRepCnt15_BITS   7:0
#define csr_AcsmCmdRepCnt15_MSB  7
#define csr_AcsmCmdRepCnt15_LSB  0
#define csr_AcsmCmdRepCnt15_MASK 0xff
#define csr_AcsmAdrAdv15_RANGE  9:8
#define csr_AcsmAdrAdv15_BITS   1:0
#define csr_AcsmAdrAdv15_MSB  9
#define csr_AcsmAdrAdv15_LSB  8
#define csr_AcsmAdrAdv15_MASK 0x300
#define csr_AcsmBnkAdv15_RANGE  11:10
#define csr_AcsmBnkAdv15_BITS   1:0
#define csr_AcsmBnkAdv15_MSB  11
#define csr_AcsmBnkAdv15_LSB  10
#define csr_AcsmBnkAdv15_MASK 0xc00
#define csr_AcsmAdrSelLoad15_RANGE  13:12
#define csr_AcsmAdrSelLoad15_BITS   1:0
#define csr_AcsmAdrSelLoad15_MSB  13
#define csr_AcsmAdrSelLoad15_LSB  12
#define csr_AcsmAdrSelLoad15_MASK 0x3000
#define csr_AcsmBnkSelLoad15_RANGE  14:14
#define csr_AcsmBnkSelLoad15_BITS   0:0
#define csr_AcsmBnkSelLoad15_MSB  14
#define csr_AcsmBnkSelLoad15_LSB  14
#define csr_AcsmBnkSelLoad15_MASK 0x4000
#define csr_AcsmLongBubble15_RANGE  15:15
#define csr_AcsmLongBubble15_BITS   0:0
#define csr_AcsmLongBubble15_MSB  15
#define csr_AcsmLongBubble15_LSB  15
#define csr_AcsmLongBubble15_MASK 0x8000
#define csr_CoreLoopbackSel_RANGE  0:0
#define csr_CoreLoopbackSel_BITS   0:0
#define csr_CoreLoopbackSel_MSB  0
#define csr_CoreLoopbackSel_LSB  0
#define csr_CoreLoopbackSel_MASK 0x1
#define csr_SequenceReg0b23s2_RANGE  8:0
#define csr_SequenceReg0b23s2_BITS   8:0
#define csr_SequenceReg0b23s2_MSB  8
#define csr_SequenceReg0b23s2_LSB  0
#define csr_SequenceReg0b23s2_MASK 0x1ff
#define csr_SequenceReg0b109s0_RANGE  15:0
#define csr_SequenceReg0b109s0_BITS   15:0
#define csr_SequenceReg0b109s0_MSB  15
#define csr_SequenceReg0b109s0_LSB  0
#define csr_SequenceReg0b109s0_MASK 0xffff
#define csr_AcsmSeq3x16_RANGE  15:0
#define csr_AcsmSeq3x16_BITS   15:0
#define csr_AcsmSeq3x16_MSB  15
#define csr_AcsmSeq3x16_LSB  0
#define csr_AcsmSeq3x16_MASK 0xffff
#define csr_AcsmCmdRepCnt16_RANGE  7:0
#define csr_AcsmCmdRepCnt16_BITS   7:0
#define csr_AcsmCmdRepCnt16_MSB  7
#define csr_AcsmCmdRepCnt16_LSB  0
#define csr_AcsmCmdRepCnt16_MASK 0xff
#define csr_AcsmAdrAdv16_RANGE  9:8
#define csr_AcsmAdrAdv16_BITS   1:0
#define csr_AcsmAdrAdv16_MSB  9
#define csr_AcsmAdrAdv16_LSB  8
#define csr_AcsmAdrAdv16_MASK 0x300
#define csr_AcsmBnkAdv16_RANGE  11:10
#define csr_AcsmBnkAdv16_BITS   1:0
#define csr_AcsmBnkAdv16_MSB  11
#define csr_AcsmBnkAdv16_LSB  10
#define csr_AcsmBnkAdv16_MASK 0xc00
#define csr_AcsmAdrSelLoad16_RANGE  13:12
#define csr_AcsmAdrSelLoad16_BITS   1:0
#define csr_AcsmAdrSelLoad16_MSB  13
#define csr_AcsmAdrSelLoad16_LSB  12
#define csr_AcsmAdrSelLoad16_MASK 0x3000
#define csr_AcsmBnkSelLoad16_RANGE  14:14
#define csr_AcsmBnkSelLoad16_BITS   0:0
#define csr_AcsmBnkSelLoad16_MSB  14
#define csr_AcsmBnkSelLoad16_LSB  14
#define csr_AcsmBnkSelLoad16_MASK 0x4000
#define csr_AcsmLongBubble16_RANGE  15:15
#define csr_AcsmLongBubble16_BITS   0:0
#define csr_AcsmLongBubble16_MSB  15
#define csr_AcsmLongBubble16_LSB  15
#define csr_AcsmLongBubble16_MASK 0x8000
#define csr_DllTrainParam_RANGE  1:0
#define csr_DllTrainParam_BITS   1:0
#define csr_DllTrainParam_MSB  1
#define csr_DllTrainParam_LSB  0
#define csr_DllTrainParam_MASK 0x3
#define csr_ExtendPhdTime_RANGE  1:0
#define csr_ExtendPhdTime_BITS   1:0
#define csr_ExtendPhdTime_MSB  1
#define csr_ExtendPhdTime_LSB  0
#define csr_ExtendPhdTime_MASK 0x3
#define csr_SequenceReg0b24s0_RANGE  15:0
#define csr_SequenceReg0b24s0_BITS   15:0
#define csr_SequenceReg0b24s0_MSB  15
#define csr_SequenceReg0b24s0_LSB  0
#define csr_SequenceReg0b24s0_MASK 0xffff
#define csr_SequenceReg0b109s1_RANGE  15:0
#define csr_SequenceReg0b109s1_BITS   15:0
#define csr_SequenceReg0b109s1_MSB  15
#define csr_SequenceReg0b109s1_LSB  0
#define csr_SequenceReg0b109s1_MASK 0xffff
#define csr_AcsmSeq3x17_RANGE  15:0
#define csr_AcsmSeq3x17_BITS   15:0
#define csr_AcsmSeq3x17_MSB  15
#define csr_AcsmSeq3x17_LSB  0
#define csr_AcsmSeq3x17_MASK 0xffff
#define csr_AcsmCmdRepCnt17_RANGE  7:0
#define csr_AcsmCmdRepCnt17_BITS   7:0
#define csr_AcsmCmdRepCnt17_MSB  7
#define csr_AcsmCmdRepCnt17_LSB  0
#define csr_AcsmCmdRepCnt17_MASK 0xff
#define csr_AcsmAdrAdv17_RANGE  9:8
#define csr_AcsmAdrAdv17_BITS   1:0
#define csr_AcsmAdrAdv17_MSB  9
#define csr_AcsmAdrAdv17_LSB  8
#define csr_AcsmAdrAdv17_MASK 0x300
#define csr_AcsmBnkAdv17_RANGE  11:10
#define csr_AcsmBnkAdv17_BITS   1:0
#define csr_AcsmBnkAdv17_MSB  11
#define csr_AcsmBnkAdv17_LSB  10
#define csr_AcsmBnkAdv17_MASK 0xc00
#define csr_AcsmAdrSelLoad17_RANGE  13:12
#define csr_AcsmAdrSelLoad17_BITS   1:0
#define csr_AcsmAdrSelLoad17_MSB  13
#define csr_AcsmAdrSelLoad17_LSB  12
#define csr_AcsmAdrSelLoad17_MASK 0x3000
#define csr_AcsmBnkSelLoad17_RANGE  14:14
#define csr_AcsmBnkSelLoad17_BITS   0:0
#define csr_AcsmBnkSelLoad17_MSB  14
#define csr_AcsmBnkSelLoad17_LSB  14
#define csr_AcsmBnkSelLoad17_MASK 0x4000
#define csr_AcsmLongBubble17_RANGE  15:15
#define csr_AcsmLongBubble17_BITS   0:0
#define csr_AcsmLongBubble17_MSB  15
#define csr_AcsmLongBubble17_LSB  15
#define csr_AcsmLongBubble17_MASK 0x8000
#define csr_HwtLpCsEnA_RANGE  1:0
#define csr_HwtLpCsEnA_BITS   1:0
#define csr_HwtLpCsEnA_MSB  1
#define csr_HwtLpCsEnA_LSB  0
#define csr_HwtLpCsEnA_MASK 0x3
#define csr_SequenceReg0b24s1_RANGE  15:0
#define csr_SequenceReg0b24s1_BITS   15:0
#define csr_SequenceReg0b24s1_MSB  15
#define csr_SequenceReg0b24s1_LSB  0
#define csr_SequenceReg0b24s1_MASK 0xffff
#define csr_SequenceReg0b109s2_RANGE  8:0
#define csr_SequenceReg0b109s2_BITS   8:0
#define csr_SequenceReg0b109s2_MSB  8
#define csr_SequenceReg0b109s2_LSB  0
#define csr_SequenceReg0b109s2_MASK 0x1ff
#define csr_AcsmSeq3x18_RANGE  15:0
#define csr_AcsmSeq3x18_BITS   15:0
#define csr_AcsmSeq3x18_MSB  15
#define csr_AcsmSeq3x18_LSB  0
#define csr_AcsmSeq3x18_MASK 0xffff
#define csr_AcsmCmdRepCnt18_RANGE  7:0
#define csr_AcsmCmdRepCnt18_BITS   7:0
#define csr_AcsmCmdRepCnt18_MSB  7
#define csr_AcsmCmdRepCnt18_LSB  0
#define csr_AcsmCmdRepCnt18_MASK 0xff
#define csr_AcsmAdrAdv18_RANGE  9:8
#define csr_AcsmAdrAdv18_BITS   1:0
#define csr_AcsmAdrAdv18_MSB  9
#define csr_AcsmAdrAdv18_LSB  8
#define csr_AcsmAdrAdv18_MASK 0x300
#define csr_AcsmBnkAdv18_RANGE  11:10
#define csr_AcsmBnkAdv18_BITS   1:0
#define csr_AcsmBnkAdv18_MSB  11
#define csr_AcsmBnkAdv18_LSB  10
#define csr_AcsmBnkAdv18_MASK 0xc00
#define csr_AcsmAdrSelLoad18_RANGE  13:12
#define csr_AcsmAdrSelLoad18_BITS   1:0
#define csr_AcsmAdrSelLoad18_MSB  13
#define csr_AcsmAdrSelLoad18_LSB  12
#define csr_AcsmAdrSelLoad18_MASK 0x3000
#define csr_AcsmBnkSelLoad18_RANGE  14:14
#define csr_AcsmBnkSelLoad18_BITS   0:0
#define csr_AcsmBnkSelLoad18_MSB  14
#define csr_AcsmBnkSelLoad18_LSB  14
#define csr_AcsmBnkSelLoad18_MASK 0x4000
#define csr_AcsmLongBubble18_RANGE  15:15
#define csr_AcsmLongBubble18_BITS   0:0
#define csr_AcsmLongBubble18_MSB  15
#define csr_AcsmLongBubble18_LSB  15
#define csr_AcsmLongBubble18_MASK 0x8000
#define csr_HwtLpCsEnB_RANGE  1:0
#define csr_HwtLpCsEnB_BITS   1:0
#define csr_HwtLpCsEnB_MSB  1
#define csr_HwtLpCsEnB_LSB  0
#define csr_HwtLpCsEnB_MASK 0x3
#define csr_SequenceReg0b24s2_RANGE  8:0
#define csr_SequenceReg0b24s2_BITS   8:0
#define csr_SequenceReg0b24s2_MSB  8
#define csr_SequenceReg0b24s2_LSB  0
#define csr_SequenceReg0b24s2_MASK 0x1ff
#define csr_SequenceReg0b110s0_RANGE  15:0
#define csr_SequenceReg0b110s0_BITS   15:0
#define csr_SequenceReg0b110s0_MSB  15
#define csr_SequenceReg0b110s0_LSB  0
#define csr_SequenceReg0b110s0_MASK 0xffff
#define csr_AcsmSeq3x19_RANGE  15:0
#define csr_AcsmSeq3x19_BITS   15:0
#define csr_AcsmSeq3x19_MSB  15
#define csr_AcsmSeq3x19_LSB  0
#define csr_AcsmSeq3x19_MASK 0xffff
#define csr_AcsmCmdRepCnt19_RANGE  7:0
#define csr_AcsmCmdRepCnt19_BITS   7:0
#define csr_AcsmCmdRepCnt19_MSB  7
#define csr_AcsmCmdRepCnt19_LSB  0
#define csr_AcsmCmdRepCnt19_MASK 0xff
#define csr_AcsmAdrAdv19_RANGE  9:8
#define csr_AcsmAdrAdv19_BITS   1:0
#define csr_AcsmAdrAdv19_MSB  9
#define csr_AcsmAdrAdv19_LSB  8
#define csr_AcsmAdrAdv19_MASK 0x300
#define csr_AcsmBnkAdv19_RANGE  11:10
#define csr_AcsmBnkAdv19_BITS   1:0
#define csr_AcsmBnkAdv19_MSB  11
#define csr_AcsmBnkAdv19_LSB  10
#define csr_AcsmBnkAdv19_MASK 0xc00
#define csr_AcsmAdrSelLoad19_RANGE  13:12
#define csr_AcsmAdrSelLoad19_BITS   1:0
#define csr_AcsmAdrSelLoad19_MSB  13
#define csr_AcsmAdrSelLoad19_LSB  12
#define csr_AcsmAdrSelLoad19_MASK 0x3000
#define csr_AcsmBnkSelLoad19_RANGE  14:14
#define csr_AcsmBnkSelLoad19_BITS   0:0
#define csr_AcsmBnkSelLoad19_MSB  14
#define csr_AcsmBnkSelLoad19_LSB  14
#define csr_AcsmBnkSelLoad19_MASK 0x4000
#define csr_AcsmLongBubble19_RANGE  15:15
#define csr_AcsmLongBubble19_BITS   0:0
#define csr_AcsmLongBubble19_MSB  15
#define csr_AcsmLongBubble19_LSB  15
#define csr_AcsmLongBubble19_MASK 0x8000
#define csr_HwtLpCsEnBypass_RANGE  0:0
#define csr_HwtLpCsEnBypass_BITS   0:0
#define csr_HwtLpCsEnBypass_MSB  0
#define csr_HwtLpCsEnBypass_LSB  0
#define csr_HwtLpCsEnBypass_MASK 0x1
#define csr_SequenceReg0b25s0_RANGE  15:0
#define csr_SequenceReg0b25s0_BITS   15:0
#define csr_SequenceReg0b25s0_MSB  15
#define csr_SequenceReg0b25s0_LSB  0
#define csr_SequenceReg0b25s0_MASK 0xffff
#define csr_SequenceReg0b110s1_RANGE  15:0
#define csr_SequenceReg0b110s1_BITS   15:0
#define csr_SequenceReg0b110s1_MSB  15
#define csr_SequenceReg0b110s1_LSB  0
#define csr_SequenceReg0b110s1_MASK 0xffff
#define csr_AcsmSeq3x20_RANGE  15:0
#define csr_AcsmSeq3x20_BITS   15:0
#define csr_AcsmSeq3x20_MSB  15
#define csr_AcsmSeq3x20_LSB  0
#define csr_AcsmSeq3x20_MASK 0xffff
#define csr_AcsmCmdRepCnt20_RANGE  7:0
#define csr_AcsmCmdRepCnt20_BITS   7:0
#define csr_AcsmCmdRepCnt20_MSB  7
#define csr_AcsmCmdRepCnt20_LSB  0
#define csr_AcsmCmdRepCnt20_MASK 0xff
#define csr_AcsmAdrAdv20_RANGE  9:8
#define csr_AcsmAdrAdv20_BITS   1:0
#define csr_AcsmAdrAdv20_MSB  9
#define csr_AcsmAdrAdv20_LSB  8
#define csr_AcsmAdrAdv20_MASK 0x300
#define csr_AcsmBnkAdv20_RANGE  11:10
#define csr_AcsmBnkAdv20_BITS   1:0
#define csr_AcsmBnkAdv20_MSB  11
#define csr_AcsmBnkAdv20_LSB  10
#define csr_AcsmBnkAdv20_MASK 0xc00
#define csr_AcsmAdrSelLoad20_RANGE  13:12
#define csr_AcsmAdrSelLoad20_BITS   1:0
#define csr_AcsmAdrSelLoad20_MSB  13
#define csr_AcsmAdrSelLoad20_LSB  12
#define csr_AcsmAdrSelLoad20_MASK 0x3000
#define csr_AcsmBnkSelLoad20_RANGE  14:14
#define csr_AcsmBnkSelLoad20_BITS   0:0
#define csr_AcsmBnkSelLoad20_MSB  14
#define csr_AcsmBnkSelLoad20_LSB  14
#define csr_AcsmBnkSelLoad20_MASK 0x4000
#define csr_AcsmLongBubble20_RANGE  15:15
#define csr_AcsmLongBubble20_BITS   0:0
#define csr_AcsmLongBubble20_MSB  15
#define csr_AcsmLongBubble20_LSB  15
#define csr_AcsmLongBubble20_MASK 0x8000
#define csr_DfiCAMode_RANGE  3:0
#define csr_DfiCAMode_BITS   3:0
#define csr_DfiCAMode_MSB  3
#define csr_DfiCAMode_LSB  0
#define csr_DfiCAMode_MASK 0xf
#define csr_DfiLp3CAMode_RANGE  0:0
#define csr_DfiLp3CAMode_BITS   0:0
#define csr_DfiLp3CAMode_MSB  0
#define csr_DfiLp3CAMode_LSB  0
#define csr_DfiLp3CAMode_MASK 0x1
#define csr_DfiD4CAMode_RANGE  1:1
#define csr_DfiD4CAMode_BITS   0:0
#define csr_DfiD4CAMode_MSB  1
#define csr_DfiD4CAMode_LSB  1
#define csr_DfiD4CAMode_MASK 0x2
#define csr_DfiLp4CAMode_RANGE  2:2
#define csr_DfiLp4CAMode_BITS   0:0
#define csr_DfiLp4CAMode_MSB  2
#define csr_DfiLp4CAMode_LSB  2
#define csr_DfiLp4CAMode_MASK 0x4
#define csr_DfiD4AltCAMode_RANGE  3:3
#define csr_DfiD4AltCAMode_BITS   0:0
#define csr_DfiD4AltCAMode_MSB  3
#define csr_DfiD4AltCAMode_LSB  3
#define csr_DfiD4AltCAMode_MASK 0x8
#define csr_SequenceReg0b25s1_RANGE  15:0
#define csr_SequenceReg0b25s1_BITS   15:0
#define csr_SequenceReg0b25s1_MSB  15
#define csr_SequenceReg0b25s1_LSB  0
#define csr_SequenceReg0b25s1_MASK 0xffff
#define csr_SequenceReg0b110s2_RANGE  8:0
#define csr_SequenceReg0b110s2_BITS   8:0
#define csr_SequenceReg0b110s2_MSB  8
#define csr_SequenceReg0b110s2_LSB  0
#define csr_SequenceReg0b110s2_MASK 0x1ff
#define csr_AcsmSeq3x21_RANGE  15:0
#define csr_AcsmSeq3x21_BITS   15:0
#define csr_AcsmSeq3x21_MSB  15
#define csr_AcsmSeq3x21_LSB  0
#define csr_AcsmSeq3x21_MASK 0xffff
#define csr_AcsmCmdRepCnt21_RANGE  7:0
#define csr_AcsmCmdRepCnt21_BITS   7:0
#define csr_AcsmCmdRepCnt21_MSB  7
#define csr_AcsmCmdRepCnt21_LSB  0
#define csr_AcsmCmdRepCnt21_MASK 0xff
#define csr_AcsmAdrAdv21_RANGE  9:8
#define csr_AcsmAdrAdv21_BITS   1:0
#define csr_AcsmAdrAdv21_MSB  9
#define csr_AcsmAdrAdv21_LSB  8
#define csr_AcsmAdrAdv21_MASK 0x300
#define csr_AcsmBnkAdv21_RANGE  11:10
#define csr_AcsmBnkAdv21_BITS   1:0
#define csr_AcsmBnkAdv21_MSB  11
#define csr_AcsmBnkAdv21_LSB  10
#define csr_AcsmBnkAdv21_MASK 0xc00
#define csr_AcsmAdrSelLoad21_RANGE  13:12
#define csr_AcsmAdrSelLoad21_BITS   1:0
#define csr_AcsmAdrSelLoad21_MSB  13
#define csr_AcsmAdrSelLoad21_LSB  12
#define csr_AcsmAdrSelLoad21_MASK 0x3000
#define csr_AcsmBnkSelLoad21_RANGE  14:14
#define csr_AcsmBnkSelLoad21_BITS   0:0
#define csr_AcsmBnkSelLoad21_MSB  14
#define csr_AcsmBnkSelLoad21_LSB  14
#define csr_AcsmBnkSelLoad21_MASK 0x4000
#define csr_AcsmLongBubble21_RANGE  15:15
#define csr_AcsmLongBubble21_BITS   0:0
#define csr_AcsmLongBubble21_MSB  15
#define csr_AcsmLongBubble21_LSB  15
#define csr_AcsmLongBubble21_MASK 0x8000
#define csr_HwtCACtl_RANGE  0:0
#define csr_HwtCACtl_BITS   0:0
#define csr_HwtCACtl_MSB  0
#define csr_HwtCACtl_LSB  0
#define csr_HwtCACtl_MASK 0x1
#define csr_HwtDisDynAdrTri_RANGE  0:0
#define csr_HwtDisDynAdrTri_BITS   0:0
#define csr_HwtDisDynAdrTri_MSB  0
#define csr_HwtDisDynAdrTri_LSB  0
#define csr_HwtDisDynAdrTri_MASK 0x1
#define csr_SequenceReg0b25s2_RANGE  8:0
#define csr_SequenceReg0b25s2_BITS   8:0
#define csr_SequenceReg0b25s2_MSB  8
#define csr_SequenceReg0b25s2_LSB  0
#define csr_SequenceReg0b25s2_MASK 0x1ff
#define csr_SequenceReg0b111s0_RANGE  15:0
#define csr_SequenceReg0b111s0_BITS   15:0
#define csr_SequenceReg0b111s0_MSB  15
#define csr_SequenceReg0b111s0_LSB  0
#define csr_SequenceReg0b111s0_MASK 0xffff
#define csr_AcsmSeq3x22_RANGE  15:0
#define csr_AcsmSeq3x22_BITS   15:0
#define csr_AcsmSeq3x22_MSB  15
#define csr_AcsmSeq3x22_LSB  0
#define csr_AcsmSeq3x22_MASK 0xffff
#define csr_AcsmCmdRepCnt22_RANGE  7:0
#define csr_AcsmCmdRepCnt22_BITS   7:0
#define csr_AcsmCmdRepCnt22_MSB  7
#define csr_AcsmCmdRepCnt22_LSB  0
#define csr_AcsmCmdRepCnt22_MASK 0xff
#define csr_AcsmAdrAdv22_RANGE  9:8
#define csr_AcsmAdrAdv22_BITS   1:0
#define csr_AcsmAdrAdv22_MSB  9
#define csr_AcsmAdrAdv22_LSB  8
#define csr_AcsmAdrAdv22_MASK 0x300
#define csr_AcsmBnkAdv22_RANGE  11:10
#define csr_AcsmBnkAdv22_BITS   1:0
#define csr_AcsmBnkAdv22_MSB  11
#define csr_AcsmBnkAdv22_LSB  10
#define csr_AcsmBnkAdv22_MASK 0xc00
#define csr_AcsmAdrSelLoad22_RANGE  13:12
#define csr_AcsmAdrSelLoad22_BITS   1:0
#define csr_AcsmAdrSelLoad22_MSB  13
#define csr_AcsmAdrSelLoad22_LSB  12
#define csr_AcsmAdrSelLoad22_MASK 0x3000
#define csr_AcsmBnkSelLoad22_RANGE  14:14
#define csr_AcsmBnkSelLoad22_BITS   0:0
#define csr_AcsmBnkSelLoad22_MSB  14
#define csr_AcsmBnkSelLoad22_LSB  14
#define csr_AcsmBnkSelLoad22_MASK 0x4000
#define csr_AcsmLongBubble22_RANGE  15:15
#define csr_AcsmLongBubble22_BITS   0:0
#define csr_AcsmLongBubble22_MSB  15
#define csr_AcsmLongBubble22_LSB  15
#define csr_AcsmLongBubble22_MASK 0x8000
#define csr_HwtCAMode_RANGE  5:0
#define csr_HwtCAMode_BITS   5:0
#define csr_HwtCAMode_MSB  5
#define csr_HwtCAMode_LSB  0
#define csr_HwtCAMode_MASK 0x3f
#define csr_HwtLp3CAMode_RANGE  0:0
#define csr_HwtLp3CAMode_BITS   0:0
#define csr_HwtLp3CAMode_MSB  0
#define csr_HwtLp3CAMode_LSB  0
#define csr_HwtLp3CAMode_MASK 0x1
#define csr_HwtD4CAMode_RANGE  1:1
#define csr_HwtD4CAMode_BITS   0:0
#define csr_HwtD4CAMode_MSB  1
#define csr_HwtD4CAMode_LSB  1
#define csr_HwtD4CAMode_MASK 0x2
#define csr_HwtLp4CAMode_RANGE  2:2
#define csr_HwtLp4CAMode_BITS   0:0
#define csr_HwtLp4CAMode_MSB  2
#define csr_HwtLp4CAMode_LSB  2
#define csr_HwtLp4CAMode_MASK 0x4
#define csr_HwtD4AltCAMode_RANGE  3:3
#define csr_HwtD4AltCAMode_BITS   0:0
#define csr_HwtD4AltCAMode_MSB  3
#define csr_HwtD4AltCAMode_LSB  3
#define csr_HwtD4AltCAMode_MASK 0x8
#define csr_HwtCsInvert_RANGE  4:4
#define csr_HwtCsInvert_BITS   0:0
#define csr_HwtCsInvert_MSB  4
#define csr_HwtCsInvert_LSB  4
#define csr_HwtCsInvert_MASK 0x10
#define csr_HwtDBIInvert_RANGE  5:5
#define csr_HwtDBIInvert_BITS   0:0
#define csr_HwtDBIInvert_MSB  5
#define csr_HwtDBIInvert_LSB  5
#define csr_HwtDBIInvert_MASK 0x20
#define csr_SequenceReg0b26s0_RANGE  15:0
#define csr_SequenceReg0b26s0_BITS   15:0
#define csr_SequenceReg0b26s0_MSB  15
#define csr_SequenceReg0b26s0_LSB  0
#define csr_SequenceReg0b26s0_MASK 0xffff
#define csr_SequenceReg0b111s1_RANGE  15:0
#define csr_SequenceReg0b111s1_BITS   15:0
#define csr_SequenceReg0b111s1_MSB  15
#define csr_SequenceReg0b111s1_LSB  0
#define csr_SequenceReg0b111s1_MASK 0xffff
#define csr_AcsmSeq3x23_RANGE  15:0
#define csr_AcsmSeq3x23_BITS   15:0
#define csr_AcsmSeq3x23_MSB  15
#define csr_AcsmSeq3x23_LSB  0
#define csr_AcsmSeq3x23_MASK 0xffff
#define csr_AcsmCmdRepCnt23_RANGE  7:0
#define csr_AcsmCmdRepCnt23_BITS   7:0
#define csr_AcsmCmdRepCnt23_MSB  7
#define csr_AcsmCmdRepCnt23_LSB  0
#define csr_AcsmCmdRepCnt23_MASK 0xff
#define csr_AcsmAdrAdv23_RANGE  9:8
#define csr_AcsmAdrAdv23_BITS   1:0
#define csr_AcsmAdrAdv23_MSB  9
#define csr_AcsmAdrAdv23_LSB  8
#define csr_AcsmAdrAdv23_MASK 0x300
#define csr_AcsmBnkAdv23_RANGE  11:10
#define csr_AcsmBnkAdv23_BITS   1:0
#define csr_AcsmBnkAdv23_MSB  11
#define csr_AcsmBnkAdv23_LSB  10
#define csr_AcsmBnkAdv23_MASK 0xc00
#define csr_AcsmAdrSelLoad23_RANGE  13:12
#define csr_AcsmAdrSelLoad23_BITS   1:0
#define csr_AcsmAdrSelLoad23_MSB  13
#define csr_AcsmAdrSelLoad23_LSB  12
#define csr_AcsmAdrSelLoad23_MASK 0x3000
#define csr_AcsmBnkSelLoad23_RANGE  14:14
#define csr_AcsmBnkSelLoad23_BITS   0:0
#define csr_AcsmBnkSelLoad23_MSB  14
#define csr_AcsmBnkSelLoad23_LSB  14
#define csr_AcsmBnkSelLoad23_MASK 0x4000
#define csr_AcsmLongBubble23_RANGE  15:15
#define csr_AcsmLongBubble23_BITS   0:0
#define csr_AcsmLongBubble23_MSB  15
#define csr_AcsmLongBubble23_LSB  15
#define csr_AcsmLongBubble23_MASK 0x8000
#define csr_SequenceReg0b26s1_RANGE  15:0
#define csr_SequenceReg0b26s1_BITS   15:0
#define csr_SequenceReg0b26s1_MSB  15
#define csr_SequenceReg0b26s1_LSB  0
#define csr_SequenceReg0b26s1_MASK 0xffff
#define csr_SequenceReg0b111s2_RANGE  8:0
#define csr_SequenceReg0b111s2_BITS   8:0
#define csr_SequenceReg0b111s2_MSB  8
#define csr_SequenceReg0b111s2_LSB  0
#define csr_SequenceReg0b111s2_MASK 0x1ff
#define csr_AcsmSeq3x24_RANGE  15:0
#define csr_AcsmSeq3x24_BITS   15:0
#define csr_AcsmSeq3x24_MSB  15
#define csr_AcsmSeq3x24_LSB  0
#define csr_AcsmSeq3x24_MASK 0xffff
#define csr_AcsmCmdRepCnt24_RANGE  7:0
#define csr_AcsmCmdRepCnt24_BITS   7:0
#define csr_AcsmCmdRepCnt24_MSB  7
#define csr_AcsmCmdRepCnt24_LSB  0
#define csr_AcsmCmdRepCnt24_MASK 0xff
#define csr_AcsmAdrAdv24_RANGE  9:8
#define csr_AcsmAdrAdv24_BITS   1:0
#define csr_AcsmAdrAdv24_MSB  9
#define csr_AcsmAdrAdv24_LSB  8
#define csr_AcsmAdrAdv24_MASK 0x300
#define csr_AcsmBnkAdv24_RANGE  11:10
#define csr_AcsmBnkAdv24_BITS   1:0
#define csr_AcsmBnkAdv24_MSB  11
#define csr_AcsmBnkAdv24_LSB  10
#define csr_AcsmBnkAdv24_MASK 0xc00
#define csr_AcsmAdrSelLoad24_RANGE  13:12
#define csr_AcsmAdrSelLoad24_BITS   1:0
#define csr_AcsmAdrSelLoad24_MSB  13
#define csr_AcsmAdrSelLoad24_LSB  12
#define csr_AcsmAdrSelLoad24_MASK 0x3000
#define csr_AcsmBnkSelLoad24_RANGE  14:14
#define csr_AcsmBnkSelLoad24_BITS   0:0
#define csr_AcsmBnkSelLoad24_MSB  14
#define csr_AcsmBnkSelLoad24_LSB  14
#define csr_AcsmBnkSelLoad24_MASK 0x4000
#define csr_AcsmLongBubble24_RANGE  15:15
#define csr_AcsmLongBubble24_BITS   0:0
#define csr_AcsmLongBubble24_MSB  15
#define csr_AcsmLongBubble24_LSB  15
#define csr_AcsmLongBubble24_MASK 0x8000
#define csr_DllControl_RANGE  2:0
#define csr_DllControl_BITS   2:0
#define csr_DllControl_MSB  2
#define csr_DllControl_LSB  0
#define csr_DllControl_MASK 0x7
#define csr_DllResetRelock_RANGE  0:0
#define csr_DllResetRelock_BITS   0:0
#define csr_DllResetRelock_MSB  0
#define csr_DllResetRelock_LSB  0
#define csr_DllResetRelock_MASK 0x1
#define csr_DllResetSlave_RANGE  1:1
#define csr_DllResetSlave_BITS   0:0
#define csr_DllResetSlave_MSB  1
#define csr_DllResetSlave_LSB  1
#define csr_DllResetSlave_MASK 0x2
#define csr_DllResetRSVD_RANGE  2:2
#define csr_DllResetRSVD_BITS   0:0
#define csr_DllResetRSVD_MSB  2
#define csr_DllResetRSVD_LSB  2
#define csr_DllResetRSVD_MASK 0x4
#define csr_SequenceReg0b26s2_RANGE  8:0
#define csr_SequenceReg0b26s2_BITS   8:0
#define csr_SequenceReg0b26s2_MSB  8
#define csr_SequenceReg0b26s2_LSB  0
#define csr_SequenceReg0b26s2_MASK 0x1ff
#define csr_SequenceReg0b112s0_RANGE  15:0
#define csr_SequenceReg0b112s0_BITS   15:0
#define csr_SequenceReg0b112s0_MSB  15
#define csr_SequenceReg0b112s0_LSB  0
#define csr_SequenceReg0b112s0_MASK 0xffff
#define csr_AcsmSeq3x25_RANGE  15:0
#define csr_AcsmSeq3x25_BITS   15:0
#define csr_AcsmSeq3x25_MSB  15
#define csr_AcsmSeq3x25_LSB  0
#define csr_AcsmSeq3x25_MASK 0xffff
#define csr_AcsmCmdRepCnt25_RANGE  7:0
#define csr_AcsmCmdRepCnt25_BITS   7:0
#define csr_AcsmCmdRepCnt25_MSB  7
#define csr_AcsmCmdRepCnt25_LSB  0
#define csr_AcsmCmdRepCnt25_MASK 0xff
#define csr_AcsmAdrAdv25_RANGE  9:8
#define csr_AcsmAdrAdv25_BITS   1:0
#define csr_AcsmAdrAdv25_MSB  9
#define csr_AcsmAdrAdv25_LSB  8
#define csr_AcsmAdrAdv25_MASK 0x300
#define csr_AcsmBnkAdv25_RANGE  11:10
#define csr_AcsmBnkAdv25_BITS   1:0
#define csr_AcsmBnkAdv25_MSB  11
#define csr_AcsmBnkAdv25_LSB  10
#define csr_AcsmBnkAdv25_MASK 0xc00
#define csr_AcsmAdrSelLoad25_RANGE  13:12
#define csr_AcsmAdrSelLoad25_BITS   1:0
#define csr_AcsmAdrSelLoad25_MSB  13
#define csr_AcsmAdrSelLoad25_LSB  12
#define csr_AcsmAdrSelLoad25_MASK 0x3000
#define csr_AcsmBnkSelLoad25_RANGE  14:14
#define csr_AcsmBnkSelLoad25_BITS   0:0
#define csr_AcsmBnkSelLoad25_MSB  14
#define csr_AcsmBnkSelLoad25_LSB  14
#define csr_AcsmBnkSelLoad25_MASK 0x4000
#define csr_AcsmLongBubble25_RANGE  15:15
#define csr_AcsmLongBubble25_BITS   0:0
#define csr_AcsmLongBubble25_MSB  15
#define csr_AcsmLongBubble25_LSB  15
#define csr_AcsmLongBubble25_MASK 0x8000
#define csr_PulseDllUpdatePhase_RANGE  7:0
#define csr_PulseDllUpdatePhase_BITS   7:0
#define csr_PulseDllUpdatePhase_MSB  7
#define csr_PulseDllUpdatePhase_LSB  0
#define csr_PulseDllUpdatePhase_MASK 0xff
#define csr_PulseDbyteDllUpdatePhase_RANGE  0:0
#define csr_PulseDbyteDllUpdatePhase_BITS   0:0
#define csr_PulseDbyteDllUpdatePhase_MSB  0
#define csr_PulseDbyteDllUpdatePhase_LSB  0
#define csr_PulseDbyteDllUpdatePhase_MASK 0x1
#define csr_PulseACkDllUpdatePhase_RANGE  1:1
#define csr_PulseACkDllUpdatePhase_BITS   0:0
#define csr_PulseACkDllUpdatePhase_MSB  1
#define csr_PulseACkDllUpdatePhase_LSB  1
#define csr_PulseACkDllUpdatePhase_MASK 0x2
#define csr_PulseACaDllUpdatePhase_RANGE  2:2
#define csr_PulseACaDllUpdatePhase_BITS   0:0
#define csr_PulseACaDllUpdatePhase_MSB  2
#define csr_PulseACaDllUpdatePhase_LSB  2
#define csr_PulseACaDllUpdatePhase_MASK 0x4
#define csr_UpdatePhaseDestReserved_RANGE  5:3
#define csr_UpdatePhaseDestReserved_BITS   2:0
#define csr_UpdatePhaseDestReserved_MSB  5
#define csr_UpdatePhaseDestReserved_LSB  3
#define csr_UpdatePhaseDestReserved_MASK 0x38
#define csr_TrainUpdatePhaseOnLongBubble_RANGE  6:6
#define csr_TrainUpdatePhaseOnLongBubble_BITS   0:0
#define csr_TrainUpdatePhaseOnLongBubble_MSB  6
#define csr_TrainUpdatePhaseOnLongBubble_LSB  6
#define csr_TrainUpdatePhaseOnLongBubble_MASK 0x40
#define csr_AlwaysUpdateLcdlPhase_RANGE  7:7
#define csr_AlwaysUpdateLcdlPhase_BITS   0:0
#define csr_AlwaysUpdateLcdlPhase_MSB  7
#define csr_AlwaysUpdateLcdlPhase_LSB  7
#define csr_AlwaysUpdateLcdlPhase_MASK 0x80
#define csr_HwtControlOvr0_RANGE  12:0
#define csr_HwtControlOvr0_BITS   12:0
#define csr_HwtControlOvr0_MSB  12
#define csr_HwtControlOvr0_LSB  0
#define csr_HwtControlOvr0_MASK 0x1fff
#define csr_HwtCs0Ovr0_RANGE  0:0
#define csr_HwtCs0Ovr0_BITS   0:0
#define csr_HwtCs0Ovr0_MSB  0
#define csr_HwtCs0Ovr0_LSB  0
#define csr_HwtCs0Ovr0_MASK 0x1
#define csr_HwtCs1Ovr0_RANGE  1:1
#define csr_HwtCs1Ovr0_BITS   0:0
#define csr_HwtCs1Ovr0_MSB  1
#define csr_HwtCs1Ovr0_LSB  1
#define csr_HwtCs1Ovr0_MASK 0x2
#define csr_HwtCs2Ovr0_RANGE  2:2
#define csr_HwtCs2Ovr0_BITS   0:0
#define csr_HwtCs2Ovr0_MSB  2
#define csr_HwtCs2Ovr0_LSB  2
#define csr_HwtCs2Ovr0_MASK 0x4
#define csr_HwtCs3Ovr0_RANGE  3:3
#define csr_HwtCs3Ovr0_BITS   0:0
#define csr_HwtCs3Ovr0_MSB  3
#define csr_HwtCs3Ovr0_LSB  3
#define csr_HwtCs3Ovr0_MASK 0x8
#define csr_HwtCke0Ovr0_RANGE  4:4
#define csr_HwtCke0Ovr0_BITS   0:0
#define csr_HwtCke0Ovr0_MSB  4
#define csr_HwtCke0Ovr0_LSB  4
#define csr_HwtCke0Ovr0_MASK 0x10
#define csr_HwtCke1Ovr0_RANGE  5:5
#define csr_HwtCke1Ovr0_BITS   0:0
#define csr_HwtCke1Ovr0_MSB  5
#define csr_HwtCke1Ovr0_LSB  5
#define csr_HwtCke1Ovr0_MASK 0x20
#define csr_HwtCke2Ovr0_RANGE  6:6
#define csr_HwtCke2Ovr0_BITS   0:0
#define csr_HwtCke2Ovr0_MSB  6
#define csr_HwtCke2Ovr0_LSB  6
#define csr_HwtCke2Ovr0_MASK 0x40
#define csr_HwtCke3Ovr0_RANGE  7:7
#define csr_HwtCke3Ovr0_BITS   0:0
#define csr_HwtCke3Ovr0_MSB  7
#define csr_HwtCke3Ovr0_LSB  7
#define csr_HwtCke3Ovr0_MASK 0x80
#define csr_HwtOdt0Ovr0_RANGE  8:8
#define csr_HwtOdt0Ovr0_BITS   0:0
#define csr_HwtOdt0Ovr0_MSB  8
#define csr_HwtOdt0Ovr0_LSB  8
#define csr_HwtOdt0Ovr0_MASK 0x100
#define csr_HwtOdt1Ovr0_RANGE  9:9
#define csr_HwtOdt1Ovr0_BITS   0:0
#define csr_HwtOdt1Ovr0_MSB  9
#define csr_HwtOdt1Ovr0_LSB  9
#define csr_HwtOdt1Ovr0_MASK 0x200
#define csr_HwtOdt2Ovr0_RANGE  10:10
#define csr_HwtOdt2Ovr0_BITS   0:0
#define csr_HwtOdt2Ovr0_MSB  10
#define csr_HwtOdt2Ovr0_LSB  10
#define csr_HwtOdt2Ovr0_MASK 0x400
#define csr_HwtOdt3Ovr0_RANGE  11:11
#define csr_HwtOdt3Ovr0_BITS   0:0
#define csr_HwtOdt3Ovr0_MSB  11
#define csr_HwtOdt3Ovr0_LSB  11
#define csr_HwtOdt3Ovr0_MASK 0x800
#define csr_HwtParityOvr0_RANGE  12:12
#define csr_HwtParityOvr0_BITS   0:0
#define csr_HwtParityOvr0_MSB  12
#define csr_HwtParityOvr0_LSB  12
#define csr_HwtParityOvr0_MASK 0x1000
#define csr_SequenceReg0b27s0_RANGE  15:0
#define csr_SequenceReg0b27s0_BITS   15:0
#define csr_SequenceReg0b27s0_MSB  15
#define csr_SequenceReg0b27s0_LSB  0
#define csr_SequenceReg0b27s0_MASK 0xffff
#define csr_SequenceReg0b112s1_RANGE  15:0
#define csr_SequenceReg0b112s1_BITS   15:0
#define csr_SequenceReg0b112s1_MSB  15
#define csr_SequenceReg0b112s1_LSB  0
#define csr_SequenceReg0b112s1_MASK 0xffff
#define csr_AcsmSeq3x26_RANGE  15:0
#define csr_AcsmSeq3x26_BITS   15:0
#define csr_AcsmSeq3x26_MSB  15
#define csr_AcsmSeq3x26_LSB  0
#define csr_AcsmSeq3x26_MASK 0xffff
#define csr_AcsmCmdRepCnt26_RANGE  7:0
#define csr_AcsmCmdRepCnt26_BITS   7:0
#define csr_AcsmCmdRepCnt26_MSB  7
#define csr_AcsmCmdRepCnt26_LSB  0
#define csr_AcsmCmdRepCnt26_MASK 0xff
#define csr_AcsmAdrAdv26_RANGE  9:8
#define csr_AcsmAdrAdv26_BITS   1:0
#define csr_AcsmAdrAdv26_MSB  9
#define csr_AcsmAdrAdv26_LSB  8
#define csr_AcsmAdrAdv26_MASK 0x300
#define csr_AcsmBnkAdv26_RANGE  11:10
#define csr_AcsmBnkAdv26_BITS   1:0
#define csr_AcsmBnkAdv26_MSB  11
#define csr_AcsmBnkAdv26_LSB  10
#define csr_AcsmBnkAdv26_MASK 0xc00
#define csr_AcsmAdrSelLoad26_RANGE  13:12
#define csr_AcsmAdrSelLoad26_BITS   1:0
#define csr_AcsmAdrSelLoad26_MSB  13
#define csr_AcsmAdrSelLoad26_LSB  12
#define csr_AcsmAdrSelLoad26_MASK 0x3000
#define csr_AcsmBnkSelLoad26_RANGE  14:14
#define csr_AcsmBnkSelLoad26_BITS   0:0
#define csr_AcsmBnkSelLoad26_MSB  14
#define csr_AcsmBnkSelLoad26_LSB  14
#define csr_AcsmBnkSelLoad26_MASK 0x4000
#define csr_AcsmLongBubble26_RANGE  15:15
#define csr_AcsmLongBubble26_BITS   0:0
#define csr_AcsmLongBubble26_MSB  15
#define csr_AcsmLongBubble26_LSB  15
#define csr_AcsmLongBubble26_MASK 0x8000
#define csr_HwtControlOvr1_RANGE  12:0
#define csr_HwtControlOvr1_BITS   12:0
#define csr_HwtControlOvr1_MSB  12
#define csr_HwtControlOvr1_LSB  0
#define csr_HwtControlOvr1_MASK 0x1fff
#define csr_HwtCs0Ovr1_RANGE  0:0
#define csr_HwtCs0Ovr1_BITS   0:0
#define csr_HwtCs0Ovr1_MSB  0
#define csr_HwtCs0Ovr1_LSB  0
#define csr_HwtCs0Ovr1_MASK 0x1
#define csr_HwtCs1Ovr1_RANGE  1:1
#define csr_HwtCs1Ovr1_BITS   0:0
#define csr_HwtCs1Ovr1_MSB  1
#define csr_HwtCs1Ovr1_LSB  1
#define csr_HwtCs1Ovr1_MASK 0x2
#define csr_HwtCs2Ovr1_RANGE  2:2
#define csr_HwtCs2Ovr1_BITS   0:0
#define csr_HwtCs2Ovr1_MSB  2
#define csr_HwtCs2Ovr1_LSB  2
#define csr_HwtCs2Ovr1_MASK 0x4
#define csr_HwtCs3Ovr1_RANGE  3:3
#define csr_HwtCs3Ovr1_BITS   0:0
#define csr_HwtCs3Ovr1_MSB  3
#define csr_HwtCs3Ovr1_LSB  3
#define csr_HwtCs3Ovr1_MASK 0x8
#define csr_HwtCke0Ovr1_RANGE  4:4
#define csr_HwtCke0Ovr1_BITS   0:0
#define csr_HwtCke0Ovr1_MSB  4
#define csr_HwtCke0Ovr1_LSB  4
#define csr_HwtCke0Ovr1_MASK 0x10
#define csr_HwtCke1Ovr1_RANGE  5:5
#define csr_HwtCke1Ovr1_BITS   0:0
#define csr_HwtCke1Ovr1_MSB  5
#define csr_HwtCke1Ovr1_LSB  5
#define csr_HwtCke1Ovr1_MASK 0x20
#define csr_HwtCke2Ovr1_RANGE  6:6
#define csr_HwtCke2Ovr1_BITS   0:0
#define csr_HwtCke2Ovr1_MSB  6
#define csr_HwtCke2Ovr1_LSB  6
#define csr_HwtCke2Ovr1_MASK 0x40
#define csr_HwtCke3Ovr1_RANGE  7:7
#define csr_HwtCke3Ovr1_BITS   0:0
#define csr_HwtCke3Ovr1_MSB  7
#define csr_HwtCke3Ovr1_LSB  7
#define csr_HwtCke3Ovr1_MASK 0x80
#define csr_HwtOdt0Ovr1_RANGE  8:8
#define csr_HwtOdt0Ovr1_BITS   0:0
#define csr_HwtOdt0Ovr1_MSB  8
#define csr_HwtOdt0Ovr1_LSB  8
#define csr_HwtOdt0Ovr1_MASK 0x100
#define csr_HwtOdt1Ovr1_RANGE  9:9
#define csr_HwtOdt1Ovr1_BITS   0:0
#define csr_HwtOdt1Ovr1_MSB  9
#define csr_HwtOdt1Ovr1_LSB  9
#define csr_HwtOdt1Ovr1_MASK 0x200
#define csr_HwtOdt2Ovr1_RANGE  10:10
#define csr_HwtOdt2Ovr1_BITS   0:0
#define csr_HwtOdt2Ovr1_MSB  10
#define csr_HwtOdt2Ovr1_LSB  10
#define csr_HwtOdt2Ovr1_MASK 0x400
#define csr_HwtOdt3Ovr1_RANGE  11:11
#define csr_HwtOdt3Ovr1_BITS   0:0
#define csr_HwtOdt3Ovr1_MSB  11
#define csr_HwtOdt3Ovr1_LSB  11
#define csr_HwtOdt3Ovr1_MASK 0x800
#define csr_HwtParityOvr1_RANGE  12:12
#define csr_HwtParityOvr1_BITS   0:0
#define csr_HwtParityOvr1_MSB  12
#define csr_HwtParityOvr1_LSB  12
#define csr_HwtParityOvr1_MASK 0x1000
#define csr_SequenceReg0b27s1_RANGE  15:0
#define csr_SequenceReg0b27s1_BITS   15:0
#define csr_SequenceReg0b27s1_MSB  15
#define csr_SequenceReg0b27s1_LSB  0
#define csr_SequenceReg0b27s1_MASK 0xffff
#define csr_SequenceReg0b112s2_RANGE  8:0
#define csr_SequenceReg0b112s2_BITS   8:0
#define csr_SequenceReg0b112s2_MSB  8
#define csr_SequenceReg0b112s2_LSB  0
#define csr_SequenceReg0b112s2_MASK 0x1ff
#define csr_AcsmSeq3x27_RANGE  15:0
#define csr_AcsmSeq3x27_BITS   15:0
#define csr_AcsmSeq3x27_MSB  15
#define csr_AcsmSeq3x27_LSB  0
#define csr_AcsmSeq3x27_MASK 0xffff
#define csr_AcsmCmdRepCnt27_RANGE  7:0
#define csr_AcsmCmdRepCnt27_BITS   7:0
#define csr_AcsmCmdRepCnt27_MSB  7
#define csr_AcsmCmdRepCnt27_LSB  0
#define csr_AcsmCmdRepCnt27_MASK 0xff
#define csr_AcsmAdrAdv27_RANGE  9:8
#define csr_AcsmAdrAdv27_BITS   1:0
#define csr_AcsmAdrAdv27_MSB  9
#define csr_AcsmAdrAdv27_LSB  8
#define csr_AcsmAdrAdv27_MASK 0x300
#define csr_AcsmBnkAdv27_RANGE  11:10
#define csr_AcsmBnkAdv27_BITS   1:0
#define csr_AcsmBnkAdv27_MSB  11
#define csr_AcsmBnkAdv27_LSB  10
#define csr_AcsmBnkAdv27_MASK 0xc00
#define csr_AcsmAdrSelLoad27_RANGE  13:12
#define csr_AcsmAdrSelLoad27_BITS   1:0
#define csr_AcsmAdrSelLoad27_MSB  13
#define csr_AcsmAdrSelLoad27_LSB  12
#define csr_AcsmAdrSelLoad27_MASK 0x3000
#define csr_AcsmBnkSelLoad27_RANGE  14:14
#define csr_AcsmBnkSelLoad27_BITS   0:0
#define csr_AcsmBnkSelLoad27_MSB  14
#define csr_AcsmBnkSelLoad27_LSB  14
#define csr_AcsmBnkSelLoad27_MASK 0x4000
#define csr_AcsmLongBubble27_RANGE  15:15
#define csr_AcsmLongBubble27_BITS   0:0
#define csr_AcsmLongBubble27_MSB  15
#define csr_AcsmLongBubble27_LSB  15
#define csr_AcsmLongBubble27_MASK 0x8000
#define csr_SequenceReg0b27s2_RANGE  8:0
#define csr_SequenceReg0b27s2_BITS   8:0
#define csr_SequenceReg0b27s2_MSB  8
#define csr_SequenceReg0b27s2_LSB  0
#define csr_SequenceReg0b27s2_MASK 0x1ff
#define csr_SequenceReg0b113s0_RANGE  15:0
#define csr_SequenceReg0b113s0_BITS   15:0
#define csr_SequenceReg0b113s0_MSB  15
#define csr_SequenceReg0b113s0_LSB  0
#define csr_SequenceReg0b113s0_MASK 0xffff
#define csr_AcsmSeq3x28_RANGE  15:0
#define csr_AcsmSeq3x28_BITS   15:0
#define csr_AcsmSeq3x28_MSB  15
#define csr_AcsmSeq3x28_LSB  0
#define csr_AcsmSeq3x28_MASK 0xffff
#define csr_AcsmCmdRepCnt28_RANGE  7:0
#define csr_AcsmCmdRepCnt28_BITS   7:0
#define csr_AcsmCmdRepCnt28_MSB  7
#define csr_AcsmCmdRepCnt28_LSB  0
#define csr_AcsmCmdRepCnt28_MASK 0xff
#define csr_AcsmAdrAdv28_RANGE  9:8
#define csr_AcsmAdrAdv28_BITS   1:0
#define csr_AcsmAdrAdv28_MSB  9
#define csr_AcsmAdrAdv28_LSB  8
#define csr_AcsmAdrAdv28_MASK 0x300
#define csr_AcsmBnkAdv28_RANGE  11:10
#define csr_AcsmBnkAdv28_BITS   1:0
#define csr_AcsmBnkAdv28_MSB  11
#define csr_AcsmBnkAdv28_LSB  10
#define csr_AcsmBnkAdv28_MASK 0xc00
#define csr_AcsmAdrSelLoad28_RANGE  13:12
#define csr_AcsmAdrSelLoad28_BITS   1:0
#define csr_AcsmAdrSelLoad28_MSB  13
#define csr_AcsmAdrSelLoad28_LSB  12
#define csr_AcsmAdrSelLoad28_MASK 0x3000
#define csr_AcsmBnkSelLoad28_RANGE  14:14
#define csr_AcsmBnkSelLoad28_BITS   0:0
#define csr_AcsmBnkSelLoad28_MSB  14
#define csr_AcsmBnkSelLoad28_LSB  14
#define csr_AcsmBnkSelLoad28_MASK 0x4000
#define csr_AcsmLongBubble28_RANGE  15:15
#define csr_AcsmLongBubble28_BITS   0:0
#define csr_AcsmLongBubble28_MSB  15
#define csr_AcsmLongBubble28_LSB  15
#define csr_AcsmLongBubble28_MASK 0x8000
#define csr_DllGainCtl_RANGE  11:0
#define csr_DllGainCtl_BITS   11:0
#define csr_DllGainCtl_MSB  11
#define csr_DllGainCtl_LSB  0
#define csr_DllGainCtl_MASK 0xfff
#define csr_DllGainIV_RANGE  3:0
#define csr_DllGainIV_BITS   3:0
#define csr_DllGainIV_MSB  3
#define csr_DllGainIV_LSB  0
#define csr_DllGainIV_MASK 0xf
#define csr_DllGainTV_RANGE  7:4
#define csr_DllGainTV_BITS   3:0
#define csr_DllGainTV_MSB  7
#define csr_DllGainTV_LSB  4
#define csr_DllGainTV_MASK 0xf0
#define csr_DllSeedSel_RANGE  11:8
#define csr_DllSeedSel_BITS   3:0
#define csr_DllSeedSel_MSB  11
#define csr_DllSeedSel_LSB  8
#define csr_DllSeedSel_MASK 0xf00
#define csr_SequenceReg0b28s0_RANGE  15:0
#define csr_SequenceReg0b28s0_BITS   15:0
#define csr_SequenceReg0b28s0_MSB  15
#define csr_SequenceReg0b28s0_LSB  0
#define csr_SequenceReg0b28s0_MASK 0xffff
#define csr_SequenceReg0b113s1_RANGE  15:0
#define csr_SequenceReg0b113s1_BITS   15:0
#define csr_SequenceReg0b113s1_MSB  15
#define csr_SequenceReg0b113s1_LSB  0
#define csr_SequenceReg0b113s1_MASK 0xffff
#define csr_AcsmSeq3x29_RANGE  15:0
#define csr_AcsmSeq3x29_BITS   15:0
#define csr_AcsmSeq3x29_MSB  15
#define csr_AcsmSeq3x29_LSB  0
#define csr_AcsmSeq3x29_MASK 0xffff
#define csr_AcsmCmdRepCnt29_RANGE  7:0
#define csr_AcsmCmdRepCnt29_BITS   7:0
#define csr_AcsmCmdRepCnt29_MSB  7
#define csr_AcsmCmdRepCnt29_LSB  0
#define csr_AcsmCmdRepCnt29_MASK 0xff
#define csr_AcsmAdrAdv29_RANGE  9:8
#define csr_AcsmAdrAdv29_BITS   1:0
#define csr_AcsmAdrAdv29_MSB  9
#define csr_AcsmAdrAdv29_LSB  8
#define csr_AcsmAdrAdv29_MASK 0x300
#define csr_AcsmBnkAdv29_RANGE  11:10
#define csr_AcsmBnkAdv29_BITS   1:0
#define csr_AcsmBnkAdv29_MSB  11
#define csr_AcsmBnkAdv29_LSB  10
#define csr_AcsmBnkAdv29_MASK 0xc00
#define csr_AcsmAdrSelLoad29_RANGE  13:12
#define csr_AcsmAdrSelLoad29_BITS   1:0
#define csr_AcsmAdrSelLoad29_MSB  13
#define csr_AcsmAdrSelLoad29_LSB  12
#define csr_AcsmAdrSelLoad29_MASK 0x3000
#define csr_AcsmBnkSelLoad29_RANGE  14:14
#define csr_AcsmBnkSelLoad29_BITS   0:0
#define csr_AcsmBnkSelLoad29_MSB  14
#define csr_AcsmBnkSelLoad29_LSB  14
#define csr_AcsmBnkSelLoad29_MASK 0x4000
#define csr_AcsmLongBubble29_RANGE  15:15
#define csr_AcsmLongBubble29_BITS   0:0
#define csr_AcsmLongBubble29_MSB  15
#define csr_AcsmLongBubble29_LSB  15
#define csr_AcsmLongBubble29_MASK 0x8000
#define csr_DllLockParam_RANGE  12:0
#define csr_DllLockParam_BITS   12:0
#define csr_DllLockParam_MSB  12
#define csr_DllLockParam_LSB  0
#define csr_DllLockParam_MASK 0x1fff
#define csr_DisDllSeedSel_RANGE  0:0
#define csr_DisDllSeedSel_BITS   0:0
#define csr_DisDllSeedSel_MSB  0
#define csr_DisDllSeedSel_LSB  0
#define csr_DisDllSeedSel_MASK 0x1
#define csr_DisDllGainIVSeed_RANGE  1:1
#define csr_DisDllGainIVSeed_BITS   0:0
#define csr_DisDllGainIVSeed_MSB  1
#define csr_DisDllGainIVSeed_LSB  1
#define csr_DisDllGainIVSeed_MASK 0x2
#define csr_DllLockParamSpare_RANGE  3:2
#define csr_DllLockParamSpare_BITS   1:0
#define csr_DllLockParamSpare_MSB  3
#define csr_DllLockParamSpare_LSB  2
#define csr_DllLockParamSpare_MASK 0xc
#define csr_LcdlSeed0_RANGE  12:4
#define csr_LcdlSeed0_BITS   8:0
#define csr_LcdlSeed0_MSB  12
#define csr_LcdlSeed0_LSB  4
#define csr_LcdlSeed0_MASK 0x1ff0
#define csr_HwtControlVal0_RANGE  12:0
#define csr_HwtControlVal0_BITS   12:0
#define csr_HwtControlVal0_MSB  12
#define csr_HwtControlVal0_LSB  0
#define csr_HwtControlVal0_MASK 0x1fff
#define csr_HwtCs0Val0_RANGE  0:0
#define csr_HwtCs0Val0_BITS   0:0
#define csr_HwtCs0Val0_MSB  0
#define csr_HwtCs0Val0_LSB  0
#define csr_HwtCs0Val0_MASK 0x1
#define csr_HwtCs1Val0_RANGE  1:1
#define csr_HwtCs1Val0_BITS   0:0
#define csr_HwtCs1Val0_MSB  1
#define csr_HwtCs1Val0_LSB  1
#define csr_HwtCs1Val0_MASK 0x2
#define csr_HwtCs2Val0_RANGE  2:2
#define csr_HwtCs2Val0_BITS   0:0
#define csr_HwtCs2Val0_MSB  2
#define csr_HwtCs2Val0_LSB  2
#define csr_HwtCs2Val0_MASK 0x4
#define csr_HwtCs3Val0_RANGE  3:3
#define csr_HwtCs3Val0_BITS   0:0
#define csr_HwtCs3Val0_MSB  3
#define csr_HwtCs3Val0_LSB  3
#define csr_HwtCs3Val0_MASK 0x8
#define csr_HwtCke0Val0_RANGE  4:4
#define csr_HwtCke0Val0_BITS   0:0
#define csr_HwtCke0Val0_MSB  4
#define csr_HwtCke0Val0_LSB  4
#define csr_HwtCke0Val0_MASK 0x10
#define csr_HwtCke1Val0_RANGE  5:5
#define csr_HwtCke1Val0_BITS   0:0
#define csr_HwtCke1Val0_MSB  5
#define csr_HwtCke1Val0_LSB  5
#define csr_HwtCke1Val0_MASK 0x20
#define csr_HwtCke2Val0_RANGE  6:6
#define csr_HwtCke2Val0_BITS   0:0
#define csr_HwtCke2Val0_MSB  6
#define csr_HwtCke2Val0_LSB  6
#define csr_HwtCke2Val0_MASK 0x40
#define csr_HwtCke3Val0_RANGE  7:7
#define csr_HwtCke3Val0_BITS   0:0
#define csr_HwtCke3Val0_MSB  7
#define csr_HwtCke3Val0_LSB  7
#define csr_HwtCke3Val0_MASK 0x80
#define csr_HwtOdt0Val0_RANGE  8:8
#define csr_HwtOdt0Val0_BITS   0:0
#define csr_HwtOdt0Val0_MSB  8
#define csr_HwtOdt0Val0_LSB  8
#define csr_HwtOdt0Val0_MASK 0x100
#define csr_HwtOdt1Val0_RANGE  9:9
#define csr_HwtOdt1Val0_BITS   0:0
#define csr_HwtOdt1Val0_MSB  9
#define csr_HwtOdt1Val0_LSB  9
#define csr_HwtOdt1Val0_MASK 0x200
#define csr_HwtOdt2Val0_RANGE  10:10
#define csr_HwtOdt2Val0_BITS   0:0
#define csr_HwtOdt2Val0_MSB  10
#define csr_HwtOdt2Val0_LSB  10
#define csr_HwtOdt2Val0_MASK 0x400
#define csr_HwtOdt3Val0_RANGE  11:11
#define csr_HwtOdt3Val0_BITS   0:0
#define csr_HwtOdt3Val0_MSB  11
#define csr_HwtOdt3Val0_LSB  11
#define csr_HwtOdt3Val0_MASK 0x800
#define csr_HwtParityVal0_RANGE  12:12
#define csr_HwtParityVal0_BITS   0:0
#define csr_HwtParityVal0_MSB  12
#define csr_HwtParityVal0_LSB  12
#define csr_HwtParityVal0_MASK 0x1000
#define csr_SequenceReg0b28s1_RANGE  15:0
#define csr_SequenceReg0b28s1_BITS   15:0
#define csr_SequenceReg0b28s1_MSB  15
#define csr_SequenceReg0b28s1_LSB  0
#define csr_SequenceReg0b28s1_MASK 0xffff
#define csr_SequenceReg0b113s2_RANGE  8:0
#define csr_SequenceReg0b113s2_BITS   8:0
#define csr_SequenceReg0b113s2_MSB  8
#define csr_SequenceReg0b113s2_LSB  0
#define csr_SequenceReg0b113s2_MASK 0x1ff
#define csr_AcsmSeq3x30_RANGE  15:0
#define csr_AcsmSeq3x30_BITS   15:0
#define csr_AcsmSeq3x30_MSB  15
#define csr_AcsmSeq3x30_LSB  0
#define csr_AcsmSeq3x30_MASK 0xffff
#define csr_AcsmCmdRepCnt30_RANGE  7:0
#define csr_AcsmCmdRepCnt30_BITS   7:0
#define csr_AcsmCmdRepCnt30_MSB  7
#define csr_AcsmCmdRepCnt30_LSB  0
#define csr_AcsmCmdRepCnt30_MASK 0xff
#define csr_AcsmAdrAdv30_RANGE  9:8
#define csr_AcsmAdrAdv30_BITS   1:0
#define csr_AcsmAdrAdv30_MSB  9
#define csr_AcsmAdrAdv30_LSB  8
#define csr_AcsmAdrAdv30_MASK 0x300
#define csr_AcsmBnkAdv30_RANGE  11:10
#define csr_AcsmBnkAdv30_BITS   1:0
#define csr_AcsmBnkAdv30_MSB  11
#define csr_AcsmBnkAdv30_LSB  10
#define csr_AcsmBnkAdv30_MASK 0xc00
#define csr_AcsmAdrSelLoad30_RANGE  13:12
#define csr_AcsmAdrSelLoad30_BITS   1:0
#define csr_AcsmAdrSelLoad30_MSB  13
#define csr_AcsmAdrSelLoad30_LSB  12
#define csr_AcsmAdrSelLoad30_MASK 0x3000
#define csr_AcsmBnkSelLoad30_RANGE  14:14
#define csr_AcsmBnkSelLoad30_BITS   0:0
#define csr_AcsmBnkSelLoad30_MSB  14
#define csr_AcsmBnkSelLoad30_LSB  14
#define csr_AcsmBnkSelLoad30_MASK 0x4000
#define csr_AcsmLongBubble30_RANGE  15:15
#define csr_AcsmLongBubble30_BITS   0:0
#define csr_AcsmLongBubble30_MSB  15
#define csr_AcsmLongBubble30_LSB  15
#define csr_AcsmLongBubble30_MASK 0x8000
#define csr_HwtControlVal1_RANGE  12:0
#define csr_HwtControlVal1_BITS   12:0
#define csr_HwtControlVal1_MSB  12
#define csr_HwtControlVal1_LSB  0
#define csr_HwtControlVal1_MASK 0x1fff
#define csr_HwtCs0Val1_RANGE  0:0
#define csr_HwtCs0Val1_BITS   0:0
#define csr_HwtCs0Val1_MSB  0
#define csr_HwtCs0Val1_LSB  0
#define csr_HwtCs0Val1_MASK 0x1
#define csr_HwtCs1Val1_RANGE  1:1
#define csr_HwtCs1Val1_BITS   0:0
#define csr_HwtCs1Val1_MSB  1
#define csr_HwtCs1Val1_LSB  1
#define csr_HwtCs1Val1_MASK 0x2
#define csr_HwtCs2Val1_RANGE  2:2
#define csr_HwtCs2Val1_BITS   0:0
#define csr_HwtCs2Val1_MSB  2
#define csr_HwtCs2Val1_LSB  2
#define csr_HwtCs2Val1_MASK 0x4
#define csr_HwtCs3Val1_RANGE  3:3
#define csr_HwtCs3Val1_BITS   0:0
#define csr_HwtCs3Val1_MSB  3
#define csr_HwtCs3Val1_LSB  3
#define csr_HwtCs3Val1_MASK 0x8
#define csr_HwtCke0Val1_RANGE  4:4
#define csr_HwtCke0Val1_BITS   0:0
#define csr_HwtCke0Val1_MSB  4
#define csr_HwtCke0Val1_LSB  4
#define csr_HwtCke0Val1_MASK 0x10
#define csr_HwtCke1Val1_RANGE  5:5
#define csr_HwtCke1Val1_BITS   0:0
#define csr_HwtCke1Val1_MSB  5
#define csr_HwtCke1Val1_LSB  5
#define csr_HwtCke1Val1_MASK 0x20
#define csr_HwtCke2Val1_RANGE  6:6
#define csr_HwtCke2Val1_BITS   0:0
#define csr_HwtCke2Val1_MSB  6
#define csr_HwtCke2Val1_LSB  6
#define csr_HwtCke2Val1_MASK 0x40
#define csr_HwtCke3Val1_RANGE  7:7
#define csr_HwtCke3Val1_BITS   0:0
#define csr_HwtCke3Val1_MSB  7
#define csr_HwtCke3Val1_LSB  7
#define csr_HwtCke3Val1_MASK 0x80
#define csr_HwtOdt0Val1_RANGE  8:8
#define csr_HwtOdt0Val1_BITS   0:0
#define csr_HwtOdt0Val1_MSB  8
#define csr_HwtOdt0Val1_LSB  8
#define csr_HwtOdt0Val1_MASK 0x100
#define csr_HwtOdt1Val1_RANGE  9:9
#define csr_HwtOdt1Val1_BITS   0:0
#define csr_HwtOdt1Val1_MSB  9
#define csr_HwtOdt1Val1_LSB  9
#define csr_HwtOdt1Val1_MASK 0x200
#define csr_HwtOdt2Val1_RANGE  10:10
#define csr_HwtOdt2Val1_BITS   0:0
#define csr_HwtOdt2Val1_MSB  10
#define csr_HwtOdt2Val1_LSB  10
#define csr_HwtOdt2Val1_MASK 0x400
#define csr_HwtOdt3Val1_RANGE  11:11
#define csr_HwtOdt3Val1_BITS   0:0
#define csr_HwtOdt3Val1_MSB  11
#define csr_HwtOdt3Val1_LSB  11
#define csr_HwtOdt3Val1_MASK 0x800
#define csr_HwtParityVal1_RANGE  12:12
#define csr_HwtParityVal1_BITS   0:0
#define csr_HwtParityVal1_MSB  12
#define csr_HwtParityVal1_LSB  12
#define csr_HwtParityVal1_MASK 0x1000
#define csr_SequenceReg0b28s2_RANGE  8:0
#define csr_SequenceReg0b28s2_BITS   8:0
#define csr_SequenceReg0b28s2_MSB  8
#define csr_SequenceReg0b28s2_LSB  0
#define csr_SequenceReg0b28s2_MASK 0x1ff
#define csr_SequenceReg0b114s0_RANGE  15:0
#define csr_SequenceReg0b114s0_BITS   15:0
#define csr_SequenceReg0b114s0_MSB  15
#define csr_SequenceReg0b114s0_LSB  0
#define csr_SequenceReg0b114s0_MASK 0xffff
#define csr_AcsmSeq3x31_RANGE  15:0
#define csr_AcsmSeq3x31_BITS   15:0
#define csr_AcsmSeq3x31_MSB  15
#define csr_AcsmSeq3x31_LSB  0
#define csr_AcsmSeq3x31_MASK 0xffff
#define csr_AcsmCmdRepCnt31_RANGE  7:0
#define csr_AcsmCmdRepCnt31_BITS   7:0
#define csr_AcsmCmdRepCnt31_MSB  7
#define csr_AcsmCmdRepCnt31_LSB  0
#define csr_AcsmCmdRepCnt31_MASK 0xff
#define csr_AcsmAdrAdv31_RANGE  9:8
#define csr_AcsmAdrAdv31_BITS   1:0
#define csr_AcsmAdrAdv31_MSB  9
#define csr_AcsmAdrAdv31_LSB  8
#define csr_AcsmAdrAdv31_MASK 0x300
#define csr_AcsmBnkAdv31_RANGE  11:10
#define csr_AcsmBnkAdv31_BITS   1:0
#define csr_AcsmBnkAdv31_MSB  11
#define csr_AcsmBnkAdv31_LSB  10
#define csr_AcsmBnkAdv31_MASK 0xc00
#define csr_AcsmAdrSelLoad31_RANGE  13:12
#define csr_AcsmAdrSelLoad31_BITS   1:0
#define csr_AcsmAdrSelLoad31_MSB  13
#define csr_AcsmAdrSelLoad31_LSB  12
#define csr_AcsmAdrSelLoad31_MASK 0x3000
#define csr_AcsmBnkSelLoad31_RANGE  14:14
#define csr_AcsmBnkSelLoad31_BITS   0:0
#define csr_AcsmBnkSelLoad31_MSB  14
#define csr_AcsmBnkSelLoad31_LSB  14
#define csr_AcsmBnkSelLoad31_MASK 0x4000
#define csr_AcsmLongBubble31_RANGE  15:15
#define csr_AcsmLongBubble31_BITS   0:0
#define csr_AcsmLongBubble31_MSB  15
#define csr_AcsmLongBubble31_LSB  15
#define csr_AcsmLongBubble31_MASK 0x8000
#define csr_RxEnDlyTg0_RANGE  10:0
#define csr_RxEnDlyTg0_BITS   10:0
#define csr_RxEnDlyTg0_MSB  10
#define csr_RxEnDlyTg0_LSB  0
#define csr_RxEnDlyTg0_MASK 0x7ff
#define csr_ATxDly_RANGE  6:0
#define csr_ATxDly_BITS   6:0
#define csr_ATxDly_MSB  6
#define csr_ATxDly_LSB  0
#define csr_ATxDly_MASK 0x7f
#define csr_SequenceReg0b29s0_RANGE  15:0
#define csr_SequenceReg0b29s0_BITS   15:0
#define csr_SequenceReg0b29s0_MSB  15
#define csr_SequenceReg0b29s0_LSB  0
#define csr_SequenceReg0b29s0_MASK 0xffff
#define csr_SequenceReg0b114s1_RANGE  15:0
#define csr_SequenceReg0b114s1_BITS   15:0
#define csr_SequenceReg0b114s1_MSB  15
#define csr_SequenceReg0b114s1_LSB  0
#define csr_SequenceReg0b114s1_MASK 0xffff
#define csr_AcsmPlayback0x0_RANGE  11:0
#define csr_AcsmPlayback0x0_BITS   11:0
#define csr_AcsmPlayback0x0_MSB  11
#define csr_AcsmPlayback0x0_LSB  0
#define csr_AcsmPlayback0x0_MASK 0xfff
#define csr_UcclkHclkEnables_RANGE  1:0
#define csr_UcclkHclkEnables_BITS   1:0
#define csr_UcclkHclkEnables_MSB  1
#define csr_UcclkHclkEnables_LSB  0
#define csr_UcclkHclkEnables_MASK 0x3
#define csr_UcclkEn_RANGE  0:0
#define csr_UcclkEn_BITS   0:0
#define csr_UcclkEn_MSB  0
#define csr_UcclkEn_LSB  0
#define csr_UcclkEn_MASK 0x1
#define csr_HclkEn_RANGE  1:1
#define csr_HclkEn_BITS   0:0
#define csr_HclkEn_MSB  1
#define csr_HclkEn_LSB  1
#define csr_HclkEn_MASK 0x2
#define csr_RxEnDlyTg1_RANGE  10:0
#define csr_RxEnDlyTg1_BITS   10:0
#define csr_RxEnDlyTg1_MSB  10
#define csr_RxEnDlyTg1_LSB  0
#define csr_RxEnDlyTg1_MASK 0x7ff
#define csr_SequenceReg0b29s1_RANGE  15:0
#define csr_SequenceReg0b29s1_BITS   15:0
#define csr_SequenceReg0b29s1_MSB  15
#define csr_SequenceReg0b29s1_LSB  0
#define csr_SequenceReg0b29s1_MASK 0xffff
#define csr_SequenceReg0b114s2_RANGE  8:0
#define csr_SequenceReg0b114s2_BITS   8:0
#define csr_SequenceReg0b114s2_MSB  8
#define csr_SequenceReg0b114s2_LSB  0
#define csr_SequenceReg0b114s2_MASK 0x1ff
#define csr_CurPstate0b_RANGE  3:0
#define csr_CurPstate0b_BITS   3:0
#define csr_CurPstate0b_MSB  3
#define csr_CurPstate0b_LSB  0
#define csr_CurPstate0b_MASK 0xf
#define csr_AcsmGlblStart_RANGE  0:0
#define csr_AcsmGlblStart_BITS   0:0
#define csr_AcsmGlblStart_MSB  0
#define csr_AcsmGlblStart_LSB  0
#define csr_AcsmGlblStart_MASK 0x1
#define csr_AcsmPlayback1x0_RANGE  11:0
#define csr_AcsmPlayback1x0_BITS   11:0
#define csr_AcsmPlayback1x0_MSB  11
#define csr_AcsmPlayback1x0_LSB  0
#define csr_AcsmPlayback1x0_MASK 0xfff
#define csr_RxEnDlyTg2_RANGE  10:0
#define csr_RxEnDlyTg2_BITS   10:0
#define csr_RxEnDlyTg2_MSB  10
#define csr_RxEnDlyTg2_LSB  0
#define csr_RxEnDlyTg2_MASK 0x7ff
#define csr_SequenceReg0b29s2_RANGE  8:0
#define csr_SequenceReg0b29s2_BITS   8:0
#define csr_SequenceReg0b29s2_MSB  8
#define csr_SequenceReg0b29s2_LSB  0
#define csr_SequenceReg0b29s2_MASK 0x1ff
#define csr_SequenceReg0b115s0_RANGE  15:0
#define csr_SequenceReg0b115s0_BITS   15:0
#define csr_SequenceReg0b115s0_MSB  15
#define csr_SequenceReg0b115s0_LSB  0
#define csr_SequenceReg0b115s0_MASK 0xffff
#define csr_AcsmGlblSglStpCtrl_RANGE  1:0
#define csr_AcsmGlblSglStpCtrl_BITS   1:0
#define csr_AcsmGlblSglStpCtrl_MSB  1
#define csr_AcsmGlblSglStpCtrl_LSB  0
#define csr_AcsmGlblSglStpCtrl_MASK 0x3
#define csr_AcsmSglStpMode_RANGE  0:0
#define csr_AcsmSglStpMode_BITS   0:0
#define csr_AcsmSglStpMode_MSB  0
#define csr_AcsmSglStpMode_LSB  0
#define csr_AcsmSglStpMode_MASK 0x1
#define csr_AcsmSglStp_RANGE  1:1
#define csr_AcsmSglStp_BITS   0:0
#define csr_AcsmSglStp_MSB  1
#define csr_AcsmSglStp_LSB  1
#define csr_AcsmSglStp_MASK 0x2
#define csr_AcsmPlayback0x1_RANGE  11:0
#define csr_AcsmPlayback0x1_BITS   11:0
#define csr_AcsmPlayback0x1_MSB  11
#define csr_AcsmPlayback0x1_LSB  0
#define csr_AcsmPlayback0x1_MASK 0xfff
#define csr_RxEnDlyTg3_RANGE  10:0
#define csr_RxEnDlyTg3_BITS   10:0
#define csr_RxEnDlyTg3_MSB  10
#define csr_RxEnDlyTg3_LSB  0
#define csr_RxEnDlyTg3_MASK 0x7ff
#define csr_SequenceReg0b30s0_RANGE  15:0
#define csr_SequenceReg0b30s0_BITS   15:0
#define csr_SequenceReg0b30s0_MSB  15
#define csr_SequenceReg0b30s0_LSB  0
#define csr_SequenceReg0b30s0_MASK 0xffff
#define csr_SequenceReg0b115s1_RANGE  15:0
#define csr_SequenceReg0b115s1_BITS   15:0
#define csr_SequenceReg0b115s1_MSB  15
#define csr_SequenceReg0b115s1_LSB  0
#define csr_SequenceReg0b115s1_MASK 0xffff
#define csr_AcsmPlayback1x1_RANGE  11:0
#define csr_AcsmPlayback1x1_BITS   11:0
#define csr_AcsmPlayback1x1_MSB  11
#define csr_AcsmPlayback1x1_LSB  0
#define csr_AcsmPlayback1x1_MASK 0xfff
#define csr_SequenceReg0b30s1_RANGE  15:0
#define csr_SequenceReg0b30s1_BITS   15:0
#define csr_SequenceReg0b30s1_MSB  15
#define csr_SequenceReg0b30s1_LSB  0
#define csr_SequenceReg0b30s1_MASK 0xffff
#define csr_SequenceReg0b115s2_RANGE  8:0
#define csr_SequenceReg0b115s2_BITS   8:0
#define csr_SequenceReg0b115s2_MSB  8
#define csr_SequenceReg0b115s2_LSB  0
#define csr_SequenceReg0b115s2_MASK 0x1ff
#define csr_AcsmPlayback0x2_RANGE  11:0
#define csr_AcsmPlayback0x2_BITS   11:0
#define csr_AcsmPlayback0x2_MSB  11
#define csr_AcsmPlayback0x2_LSB  0
#define csr_AcsmPlayback0x2_MASK 0xfff
#define csr_LcdlCalPhase_RANGE  8:0
#define csr_LcdlCalPhase_BITS   8:0
#define csr_LcdlCalPhase_MSB  8
#define csr_LcdlCalPhase_LSB  0
#define csr_LcdlCalPhase_MASK 0x1ff
#define csr_SequenceReg0b30s2_RANGE  8:0
#define csr_SequenceReg0b30s2_BITS   8:0
#define csr_SequenceReg0b30s2_MSB  8
#define csr_SequenceReg0b30s2_LSB  0
#define csr_SequenceReg0b30s2_MASK 0x1ff
#define csr_SequenceReg0b116s0_RANGE  15:0
#define csr_SequenceReg0b116s0_BITS   15:0
#define csr_SequenceReg0b116s0_MSB  15
#define csr_SequenceReg0b116s0_LSB  0
#define csr_SequenceReg0b116s0_MASK 0xffff
#define csr_AcsmPlayback1x2_RANGE  11:0
#define csr_AcsmPlayback1x2_BITS   11:0
#define csr_AcsmPlayback1x2_MSB  11
#define csr_AcsmPlayback1x2_LSB  0
#define csr_AcsmPlayback1x2_MASK 0xfff
#define csr_LcdlCalCtrl_RANGE  6:0
#define csr_LcdlCalCtrl_BITS   6:0
#define csr_LcdlCalCtrl_MSB  6
#define csr_LcdlCalCtrl_LSB  0
#define csr_LcdlCalCtrl_MASK 0x7f
#define csr_LcdlCalMode_RANGE  0:0
#define csr_LcdlCalMode_BITS   0:0
#define csr_LcdlCalMode_MSB  0
#define csr_LcdlCalMode_LSB  0
#define csr_LcdlCalMode_MASK 0x1
#define csr_LcdlCalSlowClkSel_RANGE  1:1
#define csr_LcdlCalSlowClkSel_BITS   0:0
#define csr_LcdlCalSlowClkSel_MSB  1
#define csr_LcdlCalSlowClkSel_LSB  1
#define csr_LcdlCalSlowClkSel_MASK 0x2
#define csr_LcdlCalEn_RANGE  2:2
#define csr_LcdlCalEn_BITS   0:0
#define csr_LcdlCalEn_MSB  2
#define csr_LcdlCalEn_LSB  2
#define csr_LcdlCalEn_MASK 0x4
#define csr_LcdlCalPhaseUpdate_RANGE  3:3
#define csr_LcdlCalPhaseUpdate_BITS   0:0
#define csr_LcdlCalPhaseUpdate_MSB  3
#define csr_LcdlCalPhaseUpdate_LSB  3
#define csr_LcdlCalPhaseUpdate_MASK 0x8
#define csr_LcdlCalClkEn_RANGE  4:4
#define csr_LcdlCalClkEn_BITS   0:0
#define csr_LcdlCalClkEn_MSB  4
#define csr_LcdlCalClkEn_LSB  4
#define csr_LcdlCalClkEn_MASK 0x10
#define csr_LcdlCalSampEn_RANGE  5:5
#define csr_LcdlCalSampEn_BITS   0:0
#define csr_LcdlCalSampEn_MSB  5
#define csr_LcdlCalSampEn_LSB  5
#define csr_LcdlCalSampEn_MASK 0x20
#define csr_LcdlCalSlowClkEn_RANGE  6:6
#define csr_LcdlCalSlowClkEn_BITS   0:0
#define csr_LcdlCalSlowClkEn_MSB  6
#define csr_LcdlCalSlowClkEn_LSB  6
#define csr_LcdlCalSlowClkEn_MASK 0x40
#define csr_SequenceReg0b31s0_RANGE  15:0
#define csr_SequenceReg0b31s0_BITS   15:0
#define csr_SequenceReg0b31s0_MSB  15
#define csr_SequenceReg0b31s0_LSB  0
#define csr_SequenceReg0b31s0_MASK 0xffff
#define csr_SequenceReg0b116s1_RANGE  15:0
#define csr_SequenceReg0b116s1_BITS   15:0
#define csr_SequenceReg0b116s1_MSB  15
#define csr_SequenceReg0b116s1_LSB  0
#define csr_SequenceReg0b116s1_MASK 0xffff
#define csr_AcsmPlayback0x3_RANGE  11:0
#define csr_AcsmPlayback0x3_BITS   11:0
#define csr_AcsmPlayback0x3_MSB  11
#define csr_AcsmPlayback0x3_LSB  0
#define csr_AcsmPlayback0x3_MASK 0xfff
#define csr_SequenceReg0b31s1_RANGE  15:0
#define csr_SequenceReg0b31s1_BITS   15:0
#define csr_SequenceReg0b31s1_MSB  15
#define csr_SequenceReg0b31s1_LSB  0
#define csr_SequenceReg0b31s1_MASK 0xffff
#define csr_SequenceReg0b116s2_RANGE  8:0
#define csr_SequenceReg0b116s2_BITS   8:0
#define csr_SequenceReg0b116s2_MSB  8
#define csr_SequenceReg0b116s2_LSB  0
#define csr_SequenceReg0b116s2_MASK 0x1ff
#define csr_AcsmPlayback1x3_RANGE  11:0
#define csr_AcsmPlayback1x3_BITS   11:0
#define csr_AcsmPlayback1x3_MSB  11
#define csr_AcsmPlayback1x3_LSB  0
#define csr_AcsmPlayback1x3_MASK 0xfff
#define csr_SequenceReg0b31s2_RANGE  8:0
#define csr_SequenceReg0b31s2_BITS   8:0
#define csr_SequenceReg0b31s2_MSB  8
#define csr_SequenceReg0b31s2_LSB  0
#define csr_SequenceReg0b31s2_MASK 0x1ff
#define csr_SequenceReg0b117s0_RANGE  15:0
#define csr_SequenceReg0b117s0_BITS   15:0
#define csr_SequenceReg0b117s0_MSB  15
#define csr_SequenceReg0b117s0_LSB  0
#define csr_SequenceReg0b117s0_MASK 0xffff
#define csr_AcsmPlayback0x4_RANGE  11:0
#define csr_AcsmPlayback0x4_BITS   11:0
#define csr_AcsmPlayback0x4_MSB  11
#define csr_AcsmPlayback0x4_LSB  0
#define csr_AcsmPlayback0x4_MASK 0xfff
#define csr_CalRate_RANGE  6:0
#define csr_CalRate_BITS   6:0
#define csr_CalRate_MSB  6
#define csr_CalRate_LSB  0
#define csr_CalRate_MASK 0x7f
#define csr_CalInterval_RANGE  3:0
#define csr_CalInterval_BITS   3:0
#define csr_CalInterval_MSB  3
#define csr_CalInterval_LSB  0
#define csr_CalInterval_MASK 0xf
#define csr_CalRun_RANGE  4:4
#define csr_CalRun_BITS   0:0
#define csr_CalRun_MSB  4
#define csr_CalRun_LSB  4
#define csr_CalRun_MASK 0x10
#define csr_CalOnce_RANGE  5:5
#define csr_CalOnce_BITS   0:0
#define csr_CalOnce_MSB  5
#define csr_CalOnce_LSB  5
#define csr_CalOnce_MASK 0x20
#define csr_DisableBackgroundZQUpdates_RANGE  6:6
#define csr_DisableBackgroundZQUpdates_BITS   0:0
#define csr_DisableBackgroundZQUpdates_MSB  6
#define csr_DisableBackgroundZQUpdates_LSB  6
#define csr_DisableBackgroundZQUpdates_MASK 0x40
#define csr_SequenceReg0b32s0_RANGE  15:0
#define csr_SequenceReg0b32s0_BITS   15:0
#define csr_SequenceReg0b32s0_MSB  15
#define csr_SequenceReg0b32s0_LSB  0
#define csr_SequenceReg0b32s0_MASK 0xffff
#define csr_SequenceReg0b117s1_RANGE  15:0
#define csr_SequenceReg0b117s1_BITS   15:0
#define csr_SequenceReg0b117s1_MSB  15
#define csr_SequenceReg0b117s1_LSB  0
#define csr_SequenceReg0b117s1_MASK 0xffff
#define csr_AcsmPlayback1x4_RANGE  11:0
#define csr_AcsmPlayback1x4_BITS   11:0
#define csr_AcsmPlayback1x4_MSB  11
#define csr_AcsmPlayback1x4_LSB  0
#define csr_AcsmPlayback1x4_MASK 0xfff
#define csr_CalZap_RANGE  0:0
#define csr_CalZap_BITS   0:0
#define csr_CalZap_MSB  0
#define csr_CalZap_LSB  0
#define csr_CalZap_MASK 0x1
#define csr_SequenceReg0b32s1_RANGE  15:0
#define csr_SequenceReg0b32s1_BITS   15:0
#define csr_SequenceReg0b32s1_MSB  15
#define csr_SequenceReg0b32s1_LSB  0
#define csr_SequenceReg0b32s1_MASK 0xffff
#define csr_SequenceReg0b117s2_RANGE  8:0
#define csr_SequenceReg0b117s2_BITS   8:0
#define csr_SequenceReg0b117s2_MSB  8
#define csr_SequenceReg0b117s2_LSB  0
#define csr_SequenceReg0b117s2_MASK 0x1ff
#define csr_AcsmPlayback0x5_RANGE  11:0
#define csr_AcsmPlayback0x5_BITS   11:0
#define csr_AcsmPlayback0x5_MSB  11
#define csr_AcsmPlayback0x5_LSB  0
#define csr_AcsmPlayback0x5_MASK 0xfff
#define csr_SequenceReg0b32s2_RANGE  8:0
#define csr_SequenceReg0b32s2_BITS   8:0
#define csr_SequenceReg0b32s2_MSB  8
#define csr_SequenceReg0b32s2_LSB  0
#define csr_SequenceReg0b32s2_MASK 0x1ff
#define csr_SequenceReg0b118s0_RANGE  15:0
#define csr_SequenceReg0b118s0_BITS   15:0
#define csr_SequenceReg0b118s0_MSB  15
#define csr_SequenceReg0b118s0_LSB  0
#define csr_SequenceReg0b118s0_MASK 0xffff
#define csr_AcsmPlayback1x5_RANGE  11:0
#define csr_AcsmPlayback1x5_BITS   11:0
#define csr_AcsmPlayback1x5_MSB  11
#define csr_AcsmPlayback1x5_LSB  0
#define csr_AcsmPlayback1x5_MASK 0xfff
#define csr_PState_RANGE  3:0
#define csr_PState_BITS   3:0
#define csr_PState_MSB  3
#define csr_PState_LSB  0
#define csr_PState_MASK 0xf
#define csr_RxClkDlyTg0_RANGE  5:0
#define csr_RxClkDlyTg0_BITS   5:0
#define csr_RxClkDlyTg0_MSB  5
#define csr_RxClkDlyTg0_LSB  0
#define csr_RxClkDlyTg0_MASK 0x3f
#define csr_SequenceReg0b33s0_RANGE  15:0
#define csr_SequenceReg0b33s0_BITS   15:0
#define csr_SequenceReg0b33s0_MSB  15
#define csr_SequenceReg0b33s0_LSB  0
#define csr_SequenceReg0b33s0_MASK 0xffff
#define csr_SequenceReg0b118s1_RANGE  15:0
#define csr_SequenceReg0b118s1_BITS   15:0
#define csr_SequenceReg0b118s1_MSB  15
#define csr_SequenceReg0b118s1_LSB  0
#define csr_SequenceReg0b118s1_MASK 0xffff
#define csr_AcsmPlayback0x6_RANGE  11:0
#define csr_AcsmPlayback0x6_BITS   11:0
#define csr_AcsmPlayback0x6_MSB  11
#define csr_AcsmPlayback0x6_LSB  0
#define csr_AcsmPlayback0x6_MASK 0xfff
#define csr_CalPreDriverOverride_RANGE  7:0
#define csr_CalPreDriverOverride_BITS   7:0
#define csr_CalPreDriverOverride_MSB  7
#define csr_CalPreDriverOverride_LSB  0
#define csr_CalPreDriverOverride_MASK 0xff
#define csr_TxPreOvN_RANGE  3:0
#define csr_TxPreOvN_BITS   3:0
#define csr_TxPreOvN_MSB  3
#define csr_TxPreOvN_LSB  0
#define csr_TxPreOvN_MASK 0xf
#define csr_TxPreOvP_RANGE  7:4
#define csr_TxPreOvP_BITS   3:0
#define csr_TxPreOvP_MSB  7
#define csr_TxPreOvP_LSB  4
#define csr_TxPreOvP_MASK 0xf0
#define csr_RxClkDlyTg1_RANGE  5:0
#define csr_RxClkDlyTg1_BITS   5:0
#define csr_RxClkDlyTg1_MSB  5
#define csr_RxClkDlyTg1_LSB  0
#define csr_RxClkDlyTg1_MASK 0x3f
#define csr_SequenceReg0b33s1_RANGE  15:0
#define csr_SequenceReg0b33s1_BITS   15:0
#define csr_SequenceReg0b33s1_MSB  15
#define csr_SequenceReg0b33s1_LSB  0
#define csr_SequenceReg0b33s1_MASK 0xffff
#define csr_SequenceReg0b118s2_RANGE  8:0
#define csr_SequenceReg0b118s2_BITS   8:0
#define csr_SequenceReg0b118s2_MSB  8
#define csr_SequenceReg0b118s2_LSB  0
#define csr_SequenceReg0b118s2_MASK 0x1ff
#define csr_AcsmPlayback1x6_RANGE  11:0
#define csr_AcsmPlayback1x6_BITS   11:0
#define csr_AcsmPlayback1x6_MSB  11
#define csr_AcsmPlayback1x6_LSB  0
#define csr_AcsmPlayback1x6_MASK 0xfff
#define csr_PllOutGateControl_RANGE  1:0
#define csr_PllOutGateControl_BITS   1:0
#define csr_PllOutGateControl_MSB  1
#define csr_PllOutGateControl_LSB  0
#define csr_PllOutGateControl_MASK 0x3
#define csr_PclkGateEn_RANGE  0:0
#define csr_PclkGateEn_BITS   0:0
#define csr_PclkGateEn_MSB  0
#define csr_PclkGateEn_LSB  0
#define csr_PclkGateEn_MASK 0x1
#define csr_Reserved2x1_RANGE  1:1
#define csr_Reserved2x1_BITS   0:0
#define csr_Reserved2x1_MSB  1
#define csr_Reserved2x1_LSB  1
#define csr_Reserved2x1_MASK 0x2
#define csr_RxClkDlyTg2_RANGE  5:0
#define csr_RxClkDlyTg2_BITS   5:0
#define csr_RxClkDlyTg2_MSB  5
#define csr_RxClkDlyTg2_LSB  0
#define csr_RxClkDlyTg2_MASK 0x3f
#define csr_SequenceReg0b33s2_RANGE  8:0
#define csr_SequenceReg0b33s2_BITS   8:0
#define csr_SequenceReg0b33s2_MSB  8
#define csr_SequenceReg0b33s2_LSB  0
#define csr_SequenceReg0b33s2_MASK 0x1ff
#define csr_SequenceReg0b119s0_RANGE  15:0
#define csr_SequenceReg0b119s0_BITS   15:0
#define csr_SequenceReg0b119s0_MSB  15
#define csr_SequenceReg0b119s0_LSB  0
#define csr_SequenceReg0b119s0_MASK 0xffff
#define csr_AcsmPlayback0x7_RANGE  11:0
#define csr_AcsmPlayback0x7_BITS   11:0
#define csr_AcsmPlayback0x7_MSB  11
#define csr_AcsmPlayback0x7_LSB  0
#define csr_AcsmPlayback0x7_MASK 0xfff
#define csr_RxClkDlyTg3_RANGE  5:0
#define csr_RxClkDlyTg3_BITS   5:0
#define csr_RxClkDlyTg3_MSB  5
#define csr_RxClkDlyTg3_LSB  0
#define csr_RxClkDlyTg3_MASK 0x3f
#define csr_SequenceReg0b34s0_RANGE  15:0
#define csr_SequenceReg0b34s0_BITS   15:0
#define csr_SequenceReg0b34s0_MSB  15
#define csr_SequenceReg0b34s0_LSB  0
#define csr_SequenceReg0b34s0_MASK 0xffff
#define csr_SequenceReg0b119s1_RANGE  15:0
#define csr_SequenceReg0b119s1_BITS   15:0
#define csr_SequenceReg0b119s1_MSB  15
#define csr_SequenceReg0b119s1_LSB  0
#define csr_SequenceReg0b119s1_MASK 0xffff
#define csr_AcsmPlayback1x7_RANGE  11:0
#define csr_AcsmPlayback1x7_BITS   11:0
#define csr_AcsmPlayback1x7_MSB  11
#define csr_AcsmPlayback1x7_LSB  0
#define csr_AcsmPlayback1x7_MASK 0xfff
#define csr_UcMemResetControl_RANGE  0:0
#define csr_UcMemResetControl_BITS   0:0
#define csr_UcMemResetControl_MSB  0
#define csr_UcMemResetControl_LSB  0
#define csr_UcMemResetControl_MASK 0x1
#define csr_UcDctSane_RANGE  0:0
#define csr_UcDctSane_BITS   0:0
#define csr_UcDctSane_MSB  0
#define csr_UcDctSane_LSB  0
#define csr_UcDctSane_MASK 0x1
#define csr_RxClkcDlyTg0_RANGE  5:0
#define csr_RxClkcDlyTg0_BITS   5:0
#define csr_RxClkcDlyTg0_MSB  5
#define csr_RxClkcDlyTg0_LSB  0
#define csr_RxClkcDlyTg0_MASK 0x3f
#define csr_SequenceReg0b34s1_RANGE  15:0
#define csr_SequenceReg0b34s1_BITS   15:0
#define csr_SequenceReg0b34s1_MSB  15
#define csr_SequenceReg0b34s1_LSB  0
#define csr_SequenceReg0b34s1_MASK 0xffff
#define csr_SequenceReg0b119s2_RANGE  8:0
#define csr_SequenceReg0b119s2_BITS   8:0
#define csr_SequenceReg0b119s2_MSB  8
#define csr_SequenceReg0b119s2_LSB  0
#define csr_SequenceReg0b119s2_MASK 0x1ff
#define csr_AcsmPStateOvrEn_RANGE  0:0
#define csr_AcsmPStateOvrEn_BITS   0:0
#define csr_AcsmPStateOvrEn_MSB  0
#define csr_AcsmPStateOvrEn_LSB  0
#define csr_AcsmPStateOvrEn_MASK 0x1
#define csr_PorControl_RANGE  0:0
#define csr_PorControl_BITS   0:0
#define csr_PorControl_MSB  0
#define csr_PorControl_LSB  0
#define csr_PorControl_MASK 0x1
#define csr_PllDllLockDone_RANGE  0:0
#define csr_PllDllLockDone_BITS   0:0
#define csr_PllDllLockDone_MSB  0
#define csr_PllDllLockDone_LSB  0
#define csr_PllDllLockDone_MASK 0x1
#define csr_RxClkcDlyTg1_RANGE  5:0
#define csr_RxClkcDlyTg1_BITS   5:0
#define csr_RxClkcDlyTg1_MSB  5
#define csr_RxClkcDlyTg1_LSB  0
#define csr_RxClkcDlyTg1_MASK 0x3f
#define csr_SequenceReg0b34s2_RANGE  8:0
#define csr_SequenceReg0b34s2_BITS   8:0
#define csr_SequenceReg0b34s2_MSB  8
#define csr_SequenceReg0b34s2_LSB  0
#define csr_SequenceReg0b34s2_MASK 0x1ff
#define csr_SequenceReg0b120s0_RANGE  15:0
#define csr_SequenceReg0b120s0_BITS   15:0
#define csr_SequenceReg0b120s0_MSB  15
#define csr_SequenceReg0b120s0_LSB  0
#define csr_SequenceReg0b120s0_MASK 0xffff
#define csr_AcsmPStateOvrVal_RANGE  3:0
#define csr_AcsmPStateOvrVal_BITS   3:0
#define csr_AcsmPStateOvrVal_MSB  3
#define csr_AcsmPStateOvrVal_LSB  0
#define csr_AcsmPStateOvrVal_MASK 0xf
#define csr_RxClkcDlyTg2_RANGE  5:0
#define csr_RxClkcDlyTg2_BITS   5:0
#define csr_RxClkcDlyTg2_MSB  5
#define csr_RxClkcDlyTg2_LSB  0
#define csr_RxClkcDlyTg2_MASK 0x3f
#define csr_SequenceReg0b35s0_RANGE  15:0
#define csr_SequenceReg0b35s0_BITS   15:0
#define csr_SequenceReg0b35s0_MSB  15
#define csr_SequenceReg0b35s0_LSB  0
#define csr_SequenceReg0b35s0_MASK 0xffff
#define csr_SequenceReg0b120s1_RANGE  15:0
#define csr_SequenceReg0b120s1_BITS   15:0
#define csr_SequenceReg0b120s1_MSB  15
#define csr_SequenceReg0b120s1_LSB  0
#define csr_SequenceReg0b120s1_MASK 0xffff
#define csr_RxClkcDlyTg3_RANGE  5:0
#define csr_RxClkcDlyTg3_BITS   5:0
#define csr_RxClkcDlyTg3_MSB  5
#define csr_RxClkcDlyTg3_LSB  0
#define csr_RxClkcDlyTg3_MASK 0x3f
#define csr_SequenceReg0b35s1_RANGE  15:0
#define csr_SequenceReg0b35s1_BITS   15:0
#define csr_SequenceReg0b35s1_MSB  15
#define csr_SequenceReg0b35s1_LSB  0
#define csr_SequenceReg0b35s1_MASK 0xffff
#define csr_SequenceReg0b120s2_RANGE  8:0
#define csr_SequenceReg0b120s2_BITS   8:0
#define csr_SequenceReg0b120s2_MSB  8
#define csr_SequenceReg0b120s2_LSB  0
#define csr_SequenceReg0b120s2_MASK 0x1ff
#define csr_SequenceReg0b35s2_RANGE  8:0
#define csr_SequenceReg0b35s2_BITS   8:0
#define csr_SequenceReg0b35s2_MSB  8
#define csr_SequenceReg0b35s2_LSB  0
#define csr_SequenceReg0b35s2_MASK 0x1ff
#define csr_SequenceReg0b121s0_RANGE  15:0
#define csr_SequenceReg0b121s0_BITS   15:0
#define csr_SequenceReg0b121s0_MSB  15
#define csr_SequenceReg0b121s0_LSB  0
#define csr_SequenceReg0b121s0_MASK 0xffff
#define csr_SequenceReg0b36s0_RANGE  15:0
#define csr_SequenceReg0b36s0_BITS   15:0
#define csr_SequenceReg0b36s0_MSB  15
#define csr_SequenceReg0b36s0_LSB  0
#define csr_SequenceReg0b36s0_MASK 0xffff
#define csr_SequenceReg0b121s1_RANGE  15:0
#define csr_SequenceReg0b121s1_BITS   15:0
#define csr_SequenceReg0b121s1_MSB  15
#define csr_SequenceReg0b121s1_LSB  0
#define csr_SequenceReg0b121s1_MASK 0xffff
#define csr_ClrWakeupSticky_RANGE  3:0
#define csr_ClrWakeupSticky_BITS   3:0
#define csr_ClrWakeupSticky_MSB  3
#define csr_ClrWakeupSticky_LSB  0
#define csr_ClrWakeupSticky_MASK 0xf
#define csr_SequenceReg0b36s1_RANGE  15:0
#define csr_SequenceReg0b36s1_BITS   15:0
#define csr_SequenceReg0b36s1_MSB  15
#define csr_SequenceReg0b36s1_LSB  0
#define csr_SequenceReg0b36s1_MASK 0xffff
#define csr_SequenceReg0b121s2_RANGE  8:0
#define csr_SequenceReg0b121s2_BITS   8:0
#define csr_SequenceReg0b121s2_MSB  8
#define csr_SequenceReg0b121s2_LSB  0
#define csr_SequenceReg0b121s2_MASK 0x1ff
#define csr_WakeupMask_RANGE  3:0
#define csr_WakeupMask_BITS   3:0
#define csr_WakeupMask_MSB  3
#define csr_WakeupMask_LSB  0
#define csr_WakeupMask_MASK 0xf
#define csr_SequenceReg0b36s2_RANGE  8:0
#define csr_SequenceReg0b36s2_BITS   8:0
#define csr_SequenceReg0b36s2_MSB  8
#define csr_SequenceReg0b36s2_LSB  0
#define csr_SequenceReg0b36s2_MASK 0x1ff
#define csr_CalBusy_RANGE  0:0
#define csr_CalBusy_BITS   0:0
#define csr_CalBusy_MSB  0
#define csr_CalBusy_LSB  0
#define csr_CalBusy_MASK 0x1
#define csr_SequenceReg0b37s0_RANGE  15:0
#define csr_SequenceReg0b37s0_BITS   15:0
#define csr_SequenceReg0b37s0_MSB  15
#define csr_SequenceReg0b37s0_LSB  0
#define csr_SequenceReg0b37s0_MASK 0xffff
#define csr_CalMisc2_RANGE  15:0
#define csr_CalMisc2_BITS   15:0
#define csr_CalMisc2_MSB  15
#define csr_CalMisc2_LSB  0
#define csr_CalMisc2_MASK 0xffff
#define csr_CalNumVotes_RANGE  2:0
#define csr_CalNumVotes_BITS   2:0
#define csr_CalNumVotes_MSB  2
#define csr_CalNumVotes_LSB  0
#define csr_CalNumVotes_MASK 0x7
#define csr_Reserved10x3_RANGE  10:3
#define csr_Reserved10x3_BITS   7:0
#define csr_Reserved10x3_MSB  10
#define csr_Reserved10x3_LSB  3
#define csr_Reserved10x3_MASK 0x7f8
#define csr_Reserved11_RANGE  11:11
#define csr_Reserved11_BITS   0:0
#define csr_Reserved11_MSB  11
#define csr_Reserved11_LSB  11
#define csr_Reserved11_MASK 0x800
#define csr_CalCmptrResTrim_RANGE  12:12
#define csr_CalCmptrResTrim_BITS   0:0
#define csr_CalCmptrResTrim_MSB  12
#define csr_CalCmptrResTrim_LSB  12
#define csr_CalCmptrResTrim_MASK 0x1000
#define csr_CalCancelRoundErrDis_RANGE  13:13
#define csr_CalCancelRoundErrDis_BITS   0:0
#define csr_CalCancelRoundErrDis_MSB  13
#define csr_CalCancelRoundErrDis_LSB  13
#define csr_CalCancelRoundErrDis_MASK 0x2000
#define csr_CalSlowCmpana_RANGE  14:14
#define csr_CalSlowCmpana_BITS   0:0
#define csr_CalSlowCmpana_MSB  14
#define csr_CalSlowCmpana_LSB  14
#define csr_CalSlowCmpana_MASK 0x4000
#define csr_Reserved15_RANGE  15:15
#define csr_Reserved15_BITS   0:0
#define csr_Reserved15_MSB  15
#define csr_Reserved15_LSB  15
#define csr_Reserved15_MASK 0x8000
#define csr_SequenceReg0b37s1_RANGE  15:0
#define csr_SequenceReg0b37s1_BITS   15:0
#define csr_SequenceReg0b37s1_MSB  15
#define csr_SequenceReg0b37s1_LSB  0
#define csr_SequenceReg0b37s1_MASK 0xffff
#define csr_MicroReset_RANGE  3:0
#define csr_MicroReset_BITS   3:0
#define csr_MicroReset_MSB  3
#define csr_MicroReset_LSB  0
#define csr_MicroReset_MASK 0xf
#define csr_StallToMicro_RANGE  0:0
#define csr_StallToMicro_BITS   0:0
#define csr_StallToMicro_MSB  0
#define csr_StallToMicro_LSB  0
#define csr_StallToMicro_MASK 0x1
#define csr_TestWakeup_RANGE  1:1
#define csr_TestWakeup_BITS   0:0
#define csr_TestWakeup_MSB  1
#define csr_TestWakeup_LSB  1
#define csr_TestWakeup_MASK 0x2
#define csr_RSVDMicro_RANGE  2:2
#define csr_RSVDMicro_BITS   0:0
#define csr_RSVDMicro_MSB  2
#define csr_RSVDMicro_LSB  2
#define csr_RSVDMicro_MASK 0x4
#define csr_ResetToMicro_RANGE  3:3
#define csr_ResetToMicro_BITS   0:0
#define csr_ResetToMicro_MSB  3
#define csr_ResetToMicro_LSB  3
#define csr_ResetToMicro_MASK 0x8
#define csr_SequenceReg0b37s2_RANGE  8:0
#define csr_SequenceReg0b37s2_BITS   8:0
#define csr_SequenceReg0b37s2_MSB  8
#define csr_SequenceReg0b37s2_LSB  0
#define csr_SequenceReg0b37s2_MASK 0x1ff
#define csr_CalMisc_RANGE  2:0
#define csr_CalMisc_BITS   2:0
#define csr_CalMisc_MSB  2
#define csr_CalMisc_LSB  0
#define csr_CalMisc_MASK 0x7
#define csr_CalCmpr5Dis_RANGE  0:0
#define csr_CalCmpr5Dis_BITS   0:0
#define csr_CalCmpr5Dis_MSB  0
#define csr_CalCmpr5Dis_LSB  0
#define csr_CalCmpr5Dis_MASK 0x1
#define csr_CalNIntDis_RANGE  1:1
#define csr_CalNIntDis_BITS   0:0
#define csr_CalNIntDis_MSB  1
#define csr_CalNIntDis_LSB  1
#define csr_CalNIntDis_MASK 0x2
#define csr_CalPExtDis_RANGE  2:2
#define csr_CalPExtDis_BITS   0:0
#define csr_CalPExtDis_MSB  2
#define csr_CalPExtDis_LSB  2
#define csr_CalPExtDis_MASK 0x4
#define csr_SequenceReg0b38s0_RANGE  15:0
#define csr_SequenceReg0b38s0_BITS   15:0
#define csr_SequenceReg0b38s0_MSB  15
#define csr_SequenceReg0b38s0_LSB  0
#define csr_SequenceReg0b38s0_MASK 0xffff
#define csr_CalVRefs_RANGE  1:0
#define csr_CalVRefs_BITS   1:0
#define csr_CalVRefs_MSB  1
#define csr_CalVRefs_LSB  0
#define csr_CalVRefs_MASK 0x3
#define csr_SequenceReg0b38s1_RANGE  15:0
#define csr_SequenceReg0b38s1_BITS   15:0
#define csr_SequenceReg0b38s1_MSB  15
#define csr_SequenceReg0b38s1_LSB  0
#define csr_SequenceReg0b38s1_MASK 0xffff
#define csr_CalCmpr5_RANGE  7:0
#define csr_CalCmpr5_BITS   7:0
#define csr_CalCmpr5_MSB  7
#define csr_CalCmpr5_LSB  0
#define csr_CalCmpr5_MASK 0xff
#define csr_SequenceReg0b38s2_RANGE  8:0
#define csr_SequenceReg0b38s2_BITS   8:0
#define csr_SequenceReg0b38s2_MSB  8
#define csr_SequenceReg0b38s2_LSB  0
#define csr_SequenceReg0b38s2_MASK 0x1ff
#define csr_CalNInt_RANGE  4:0
#define csr_CalNInt_BITS   4:0
#define csr_CalNInt_MSB  4
#define csr_CalNInt_LSB  0
#define csr_CalNInt_MASK 0x1f
#define csr_CalNIntThB_RANGE  4:0
#define csr_CalNIntThB_BITS   4:0
#define csr_CalNIntThB_MSB  4
#define csr_CalNIntThB_LSB  0
#define csr_CalNIntThB_MASK 0x1f
#define csr_SequenceReg0b39s0_RANGE  15:0
#define csr_SequenceReg0b39s0_BITS   15:0
#define csr_SequenceReg0b39s0_MSB  15
#define csr_SequenceReg0b39s0_LSB  0
#define csr_SequenceReg0b39s0_MASK 0xffff
#define csr_CalPExt_RANGE  4:0
#define csr_CalPExt_BITS   4:0
#define csr_CalPExt_MSB  4
#define csr_CalPExt_LSB  0
#define csr_CalPExt_MASK 0x1f
#define csr_CalPExtThB_RANGE  4:0
#define csr_CalPExtThB_BITS   4:0
#define csr_CalPExtThB_MSB  4
#define csr_CalPExtThB_LSB  0
#define csr_CalPExtThB_MASK 0x1f
#define csr_SequenceReg0b39s1_RANGE  15:0
#define csr_SequenceReg0b39s1_BITS   15:0
#define csr_SequenceReg0b39s1_MSB  15
#define csr_SequenceReg0b39s1_LSB  0
#define csr_SequenceReg0b39s1_MASK 0xffff
#define csr_SequenceReg0b39s2_RANGE  8:0
#define csr_SequenceReg0b39s2_BITS   8:0
#define csr_SequenceReg0b39s2_MSB  8
#define csr_SequenceReg0b39s2_LSB  0
#define csr_SequenceReg0b39s2_MASK 0x1ff
#define csr_Dq0LnSel_RANGE  2:0
#define csr_Dq0LnSel_BITS   2:0
#define csr_Dq0LnSel_MSB  2
#define csr_Dq0LnSel_LSB  0
#define csr_Dq0LnSel_MASK 0x7
#define csr_SequenceReg0b40s0_RANGE  15:0
#define csr_SequenceReg0b40s0_BITS   15:0
#define csr_SequenceReg0b40s0_MSB  15
#define csr_SequenceReg0b40s0_LSB  0
#define csr_SequenceReg0b40s0_MASK 0xffff
#define csr_Dq1LnSel_RANGE  2:0
#define csr_Dq1LnSel_BITS   2:0
#define csr_Dq1LnSel_MSB  2
#define csr_Dq1LnSel_LSB  0
#define csr_Dq1LnSel_MASK 0x7
#define csr_SequenceReg0b40s1_RANGE  15:0
#define csr_SequenceReg0b40s1_BITS   15:0
#define csr_SequenceReg0b40s1_MSB  15
#define csr_SequenceReg0b40s1_LSB  0
#define csr_SequenceReg0b40s1_MASK 0xffff
#define csr_Dq2LnSel_RANGE  2:0
#define csr_Dq2LnSel_BITS   2:0
#define csr_Dq2LnSel_MSB  2
#define csr_Dq2LnSel_LSB  0
#define csr_Dq2LnSel_MASK 0x7
#define csr_SequenceReg0b40s2_RANGE  8:0
#define csr_SequenceReg0b40s2_BITS   8:0
#define csr_SequenceReg0b40s2_MSB  8
#define csr_SequenceReg0b40s2_LSB  0
#define csr_SequenceReg0b40s2_MASK 0x1ff
#define csr_Dq3LnSel_RANGE  2:0
#define csr_Dq3LnSel_BITS   2:0
#define csr_Dq3LnSel_MSB  2
#define csr_Dq3LnSel_LSB  0
#define csr_Dq3LnSel_MASK 0x7
#define csr_SequenceReg0b41s0_RANGE  15:0
#define csr_SequenceReg0b41s0_BITS   15:0
#define csr_SequenceReg0b41s0_MSB  15
#define csr_SequenceReg0b41s0_LSB  0
#define csr_SequenceReg0b41s0_MASK 0xffff
#define csr_Dq4LnSel_RANGE  2:0
#define csr_Dq4LnSel_BITS   2:0
#define csr_Dq4LnSel_MSB  2
#define csr_Dq4LnSel_LSB  0
#define csr_Dq4LnSel_MASK 0x7
#define csr_SequenceReg0b41s1_RANGE  15:0
#define csr_SequenceReg0b41s1_BITS   15:0
#define csr_SequenceReg0b41s1_MSB  15
#define csr_SequenceReg0b41s1_LSB  0
#define csr_SequenceReg0b41s1_MASK 0xffff
#define csr_Dq5LnSel_RANGE  2:0
#define csr_Dq5LnSel_BITS   2:0
#define csr_Dq5LnSel_MSB  2
#define csr_Dq5LnSel_LSB  0
#define csr_Dq5LnSel_MASK 0x7
#define csr_SequenceReg0b41s2_RANGE  8:0
#define csr_SequenceReg0b41s2_BITS   8:0
#define csr_SequenceReg0b41s2_MSB  8
#define csr_SequenceReg0b41s2_LSB  0
#define csr_SequenceReg0b41s2_MASK 0x1ff
#define csr_Dq6LnSel_RANGE  2:0
#define csr_Dq6LnSel_BITS   2:0
#define csr_Dq6LnSel_MSB  2
#define csr_Dq6LnSel_LSB  0
#define csr_Dq6LnSel_MASK 0x7
#define csr_SequenceReg0b42s0_RANGE  15:0
#define csr_SequenceReg0b42s0_BITS   15:0
#define csr_SequenceReg0b42s0_MSB  15
#define csr_SequenceReg0b42s0_LSB  0
#define csr_SequenceReg0b42s0_MASK 0xffff
#define csr_Dq7LnSel_RANGE  2:0
#define csr_Dq7LnSel_BITS   2:0
#define csr_Dq7LnSel_MSB  2
#define csr_Dq7LnSel_LSB  0
#define csr_Dq7LnSel_MASK 0x7
#define csr_SequenceReg0b42s1_RANGE  15:0
#define csr_SequenceReg0b42s1_BITS   15:0
#define csr_SequenceReg0b42s1_MSB  15
#define csr_SequenceReg0b42s1_LSB  0
#define csr_SequenceReg0b42s1_MASK 0xffff
#define csr_CalCmpInvert_RANGE  4:0
#define csr_CalCmpInvert_BITS   4:0
#define csr_CalCmpInvert_MSB  4
#define csr_CalCmpInvert_LSB  0
#define csr_CalCmpInvert_MASK 0x1f
#define csr_CmpInvertCalDac50_RANGE  0:0
#define csr_CmpInvertCalDac50_BITS   0:0
#define csr_CmpInvertCalDac50_MSB  0
#define csr_CmpInvertCalDac50_LSB  0
#define csr_CmpInvertCalDac50_MASK 0x1
#define csr_CmpInvertCalDrvPd50_RANGE  1:1
#define csr_CmpInvertCalDrvPd50_BITS   0:0
#define csr_CmpInvertCalDrvPd50_MSB  1
#define csr_CmpInvertCalDrvPd50_LSB  1
#define csr_CmpInvertCalDrvPd50_MASK 0x2
#define csr_CmpInvertCalDrvPu50_RANGE  2:2
#define csr_CmpInvertCalDrvPu50_BITS   0:0
#define csr_CmpInvertCalDrvPu50_MSB  2
#define csr_CmpInvertCalDrvPu50_LSB  2
#define csr_CmpInvertCalDrvPu50_MASK 0x4
#define csr_CmpInvertCalOdtPd_RANGE  3:3
#define csr_CmpInvertCalOdtPd_BITS   0:0
#define csr_CmpInvertCalOdtPd_MSB  3
#define csr_CmpInvertCalOdtPd_LSB  3
#define csr_CmpInvertCalOdtPd_MASK 0x8
#define csr_CmpInvertCalOdtPu_RANGE  4:4
#define csr_CmpInvertCalOdtPu_BITS   0:0
#define csr_CmpInvertCalOdtPu_MSB  4
#define csr_CmpInvertCalOdtPu_LSB  4
#define csr_CmpInvertCalOdtPu_MASK 0x10
#define csr_SequenceReg0b42s2_RANGE  8:0
#define csr_SequenceReg0b42s2_BITS   8:0
#define csr_SequenceReg0b42s2_MSB  8
#define csr_SequenceReg0b42s2_LSB  0
#define csr_SequenceReg0b42s2_MASK 0x1ff
#define csr_SequenceReg0b43s0_RANGE  15:0
#define csr_SequenceReg0b43s0_BITS   15:0
#define csr_SequenceReg0b43s0_MSB  15
#define csr_SequenceReg0b43s0_LSB  0
#define csr_SequenceReg0b43s0_MASK 0xffff
#define csr_PptCtlStatic_RANGE  11:0
#define csr_PptCtlStatic_BITS   11:0
#define csr_PptCtlStatic_MSB  11
#define csr_PptCtlStatic_LSB  0
#define csr_PptCtlStatic_MASK 0xfff
#define csr_PptEnDqs2DqTg0_RANGE  0:0
#define csr_PptEnDqs2DqTg0_BITS   0:0
#define csr_PptEnDqs2DqTg0_MSB  0
#define csr_PptEnDqs2DqTg0_LSB  0
#define csr_PptEnDqs2DqTg0_MASK 0x1
#define csr_PptEnDqs2DqTg1_RANGE  1:1
#define csr_PptEnDqs2DqTg1_BITS   0:0
#define csr_PptEnDqs2DqTg1_MSB  1
#define csr_PptEnDqs2DqTg1_LSB  1
#define csr_PptEnDqs2DqTg1_MASK 0x2
#define csr_DOCByteSelTg0_RANGE  2:2
#define csr_DOCByteSelTg0_BITS   0:0
#define csr_DOCByteSelTg0_MSB  2
#define csr_DOCByteSelTg0_LSB  2
#define csr_DOCByteSelTg0_MASK 0x4
#define csr_DOCByteSelTg1_RANGE  3:3
#define csr_DOCByteSelTg1_BITS   0:0
#define csr_DOCByteSelTg1_MSB  3
#define csr_DOCByteSelTg1_LSB  3
#define csr_DOCByteSelTg1_MASK 0x8
#define csr_PptInfoSel_RANGE  7:4
#define csr_PptInfoSel_BITS   3:0
#define csr_PptInfoSel_MSB  7
#define csr_PptInfoSel_LSB  4
#define csr_PptInfoSel_MASK 0xf0
#define csr_PptEnRxEnDlyTg0_RANGE  8:8
#define csr_PptEnRxEnDlyTg0_BITS   0:0
#define csr_PptEnRxEnDlyTg0_MSB  8
#define csr_PptEnRxEnDlyTg0_LSB  8
#define csr_PptEnRxEnDlyTg0_MASK 0x100
#define csr_PptEnRxEnDlyTg1_RANGE  9:9
#define csr_PptEnRxEnDlyTg1_BITS   0:0
#define csr_PptEnRxEnDlyTg1_MSB  9
#define csr_PptEnRxEnDlyTg1_LSB  9
#define csr_PptEnRxEnDlyTg1_MASK 0x200
#define csr_PptEnRxEnBackOff_RANGE  11:10
#define csr_PptEnRxEnBackOff_BITS   1:0
#define csr_PptEnRxEnBackOff_MSB  11
#define csr_PptEnRxEnBackOff_LSB  10
#define csr_PptEnRxEnBackOff_MASK 0xc00
#define csr_SequenceReg0b43s1_RANGE  15:0
#define csr_SequenceReg0b43s1_BITS   15:0
#define csr_SequenceReg0b43s1_MSB  15
#define csr_SequenceReg0b43s1_LSB  0
#define csr_SequenceReg0b43s1_MASK 0xffff
#define csr_PptCtlDyn_RANGE  1:0
#define csr_PptCtlDyn_BITS   1:0
#define csr_PptCtlDyn_MSB  1
#define csr_PptCtlDyn_LSB  0
#define csr_PptCtlDyn_MASK 0x3
#define csr_PptDqs2DqActive_RANGE  0:0
#define csr_PptDqs2DqActive_BITS   0:0
#define csr_PptDqs2DqActive_MSB  0
#define csr_PptDqs2DqActive_LSB  0
#define csr_PptDqs2DqActive_MASK 0x1
#define csr_PptEnRxEnUseDqsSampVal_RANGE  1:1
#define csr_PptEnRxEnUseDqsSampVal_BITS   0:0
#define csr_PptEnRxEnUseDqsSampVal_MSB  1
#define csr_PptEnRxEnUseDqsSampVal_LSB  1
#define csr_PptEnRxEnUseDqsSampVal_MASK 0x2
#define csr_SequenceReg0b43s2_RANGE  8:0
#define csr_SequenceReg0b43s2_BITS   8:0
#define csr_SequenceReg0b43s2_MSB  8
#define csr_SequenceReg0b43s2_LSB  0
#define csr_SequenceReg0b43s2_MASK 0x1ff
#define csr_PptInfo_RANGE  15:0
#define csr_PptInfo_BITS   15:0
#define csr_PptInfo_MSB  15
#define csr_PptInfo_LSB  0
#define csr_PptInfo_MASK 0xffff
#define csr_SequenceReg0b44s0_RANGE  15:0
#define csr_SequenceReg0b44s0_BITS   15:0
#define csr_SequenceReg0b44s0_MSB  15
#define csr_SequenceReg0b44s0_LSB  0
#define csr_SequenceReg0b44s0_MASK 0xffff
#define csr_PptRxEnEvnt_RANGE  1:0
#define csr_PptRxEnEvnt_BITS   1:0
#define csr_PptRxEnEvnt_MSB  1
#define csr_PptRxEnEvnt_LSB  0
#define csr_PptRxEnEvnt_MASK 0x3
#define csr_PptRxEnInit_RANGE  0:0
#define csr_PptRxEnInit_BITS   0:0
#define csr_PptRxEnInit_MSB  0
#define csr_PptRxEnInit_LSB  0
#define csr_PptRxEnInit_MASK 0x1
#define csr_PptRxEnMHUI_RANGE  1:1
#define csr_PptRxEnMHUI_BITS   0:0
#define csr_PptRxEnMHUI_MSB  1
#define csr_PptRxEnMHUI_LSB  1
#define csr_PptRxEnMHUI_MASK 0x2
#define csr_SequenceReg0b44s1_RANGE  15:0
#define csr_SequenceReg0b44s1_BITS   15:0
#define csr_SequenceReg0b44s1_MSB  15
#define csr_SequenceReg0b44s1_LSB  0
#define csr_SequenceReg0b44s1_MASK 0xffff
#define csr_CalCmpanaCntrl_RANGE  9:0
#define csr_CalCmpanaCntrl_BITS   9:0
#define csr_CalCmpanaCntrl_MSB  9
#define csr_CalCmpanaCntrl_LSB  0
#define csr_CalCmpanaCntrl_MASK 0x3ff
#define csr_CmprGainCurrAdj_RANGE  7:0
#define csr_CmprGainCurrAdj_BITS   7:0
#define csr_CmprGainCurrAdj_MSB  7
#define csr_CmprGainCurrAdj_LSB  0
#define csr_CmprGainCurrAdj_MASK 0xff
#define csr_CmprGainResAdj_RANGE  8:8
#define csr_CmprGainResAdj_BITS   0:0
#define csr_CmprGainResAdj_MSB  8
#define csr_CmprGainResAdj_LSB  8
#define csr_CmprGainResAdj_MASK 0x100
#define csr_CmprBiasBypassEn_RANGE  9:9
#define csr_CmprBiasBypassEn_BITS   0:0
#define csr_CmprBiasBypassEn_MSB  9
#define csr_CmprBiasBypassEn_LSB  9
#define csr_CmprBiasBypassEn_MASK 0x200
#define csr_PptDqsCntInvTrnTg0_RANGE  15:0
#define csr_PptDqsCntInvTrnTg0_BITS   15:0
#define csr_PptDqsCntInvTrnTg0_MSB  15
#define csr_PptDqsCntInvTrnTg0_LSB  0
#define csr_PptDqsCntInvTrnTg0_MASK 0xffff
#define csr_SequenceReg0b44s2_RANGE  8:0
#define csr_SequenceReg0b44s2_BITS   8:0
#define csr_SequenceReg0b44s2_MSB  8
#define csr_SequenceReg0b44s2_LSB  0
#define csr_SequenceReg0b44s2_MASK 0x1ff
#define csr_PptDqsCntInvTrnTg1_RANGE  15:0
#define csr_PptDqsCntInvTrnTg1_BITS   15:0
#define csr_PptDqsCntInvTrnTg1_MSB  15
#define csr_PptDqsCntInvTrnTg1_LSB  0
#define csr_PptDqsCntInvTrnTg1_MASK 0xffff
#define csr_SequenceReg0b45s0_RANGE  15:0
#define csr_SequenceReg0b45s0_BITS   15:0
#define csr_SequenceReg0b45s0_MSB  15
#define csr_SequenceReg0b45s0_LSB  0
#define csr_SequenceReg0b45s0_MASK 0xffff
#define csr_DfiRdDataCsDestMap_RANGE  7:0
#define csr_DfiRdDataCsDestMap_BITS   7:0
#define csr_DfiRdDataCsDestMap_MSB  7
#define csr_DfiRdDataCsDestMap_LSB  0
#define csr_DfiRdDataCsDestMap_MASK 0xff
#define csr_DfiRdDestm0_RANGE  1:0
#define csr_DfiRdDestm0_BITS   1:0
#define csr_DfiRdDestm0_MSB  1
#define csr_DfiRdDestm0_LSB  0
#define csr_DfiRdDestm0_MASK 0x3
#define csr_DfiRdDestm1_RANGE  3:2
#define csr_DfiRdDestm1_BITS   1:0
#define csr_DfiRdDestm1_MSB  3
#define csr_DfiRdDestm1_LSB  2
#define csr_DfiRdDestm1_MASK 0xc
#define csr_DfiRdDestm2_RANGE  5:4
#define csr_DfiRdDestm2_BITS   1:0
#define csr_DfiRdDestm2_MSB  5
#define csr_DfiRdDestm2_LSB  4
#define csr_DfiRdDestm2_MASK 0x30
#define csr_DfiRdDestm3_RANGE  7:6
#define csr_DfiRdDestm3_BITS   1:0
#define csr_DfiRdDestm3_MSB  7
#define csr_DfiRdDestm3_LSB  6
#define csr_DfiRdDestm3_MASK 0xc0
#define csr_DtsmBlankingCtrl_RANGE  9:0
#define csr_DtsmBlankingCtrl_BITS   9:0
#define csr_DtsmBlankingCtrl_MSB  9
#define csr_DtsmBlankingCtrl_LSB  0
#define csr_DtsmBlankingCtrl_MASK 0x3ff
#define csr_DtsmBlank_RANGE  9:0
#define csr_DtsmBlank_BITS   9:0
#define csr_DtsmBlank_MSB  9
#define csr_DtsmBlank_LSB  0
#define csr_DtsmBlank_MASK 0x3ff
#define csr_SequenceReg0b45s1_RANGE  15:0
#define csr_SequenceReg0b45s1_BITS   15:0
#define csr_SequenceReg0b45s1_MSB  15
#define csr_SequenceReg0b45s1_LSB  0
#define csr_SequenceReg0b45s1_MASK 0xffff
#define csr_Tsm0_RANGE  13:0
#define csr_Tsm0_BITS   13:0
#define csr_Tsm0_MSB  13
#define csr_Tsm0_LSB  0
#define csr_Tsm0_MASK 0x3fff
#define csr_DtsmEnb_RANGE  0:0
#define csr_DtsmEnb_BITS   0:0
#define csr_DtsmEnb_MSB  0
#define csr_DtsmEnb_LSB  0
#define csr_DtsmEnb_MASK 0x1
#define csr_DtsmDir_RANGE  1:1
#define csr_DtsmDir_BITS   0:0
#define csr_DtsmDir_MSB  1
#define csr_DtsmDir_LSB  1
#define csr_DtsmDir_MASK 0x2
#define csr_DtsmIgnFrst_RANGE  2:2
#define csr_DtsmIgnFrst_BITS   0:0
#define csr_DtsmIgnFrst_MSB  2
#define csr_DtsmIgnFrst_LSB  2
#define csr_DtsmIgnFrst_MASK 0x4
#define csr_DtsmOddPhase_RANGE  3:3
#define csr_DtsmOddPhase_BITS   0:0
#define csr_DtsmOddPhase_MSB  3
#define csr_DtsmOddPhase_LSB  3
#define csr_DtsmOddPhase_MASK 0x8
#define csr_DtsmFltPre_RANGE  4:4
#define csr_DtsmFltPre_BITS   0:0
#define csr_DtsmFltPre_MSB  4
#define csr_DtsmFltPre_LSB  4
#define csr_DtsmFltPre_MASK 0x10
#define csr_DtsmFltCur_RANGE  5:5
#define csr_DtsmFltCur_BITS   0:0
#define csr_DtsmFltCur_MSB  5
#define csr_DtsmFltCur_LSB  5
#define csr_DtsmFltCur_MASK 0x20
#define csr_DtsmFltNxt_RANGE  6:6
#define csr_DtsmFltNxt_BITS   0:0
#define csr_DtsmFltNxt_MSB  6
#define csr_DtsmFltNxt_LSB  6
#define csr_DtsmFltNxt_MASK 0x40
#define csr_DtsmFltVal_RANGE  9:7
#define csr_DtsmFltVal_BITS   2:0
#define csr_DtsmFltVal_MSB  9
#define csr_DtsmFltVal_LSB  7
#define csr_DtsmFltVal_MASK 0x380
#define csr_DtsmMskBit_RANGE  13:10
#define csr_DtsmMskBit_BITS   3:0
#define csr_DtsmMskBit_MSB  13
#define csr_DtsmMskBit_LSB  10
#define csr_DtsmMskBit_MASK 0x3c00
#define csr_SequenceReg0b45s2_RANGE  8:0
#define csr_SequenceReg0b45s2_BITS   8:0
#define csr_SequenceReg0b45s2_MSB  8
#define csr_SequenceReg0b45s2_LSB  0
#define csr_SequenceReg0b45s2_MASK 0x1ff
#define csr_VrefInGlobal_RANGE  14:0
#define csr_VrefInGlobal_BITS   14:0
#define csr_VrefInGlobal_MSB  14
#define csr_VrefInGlobal_LSB  0
#define csr_VrefInGlobal_MASK 0x7fff
#define csr_GlobalVrefInSel_RANGE  2:0
#define csr_GlobalVrefInSel_BITS   2:0
#define csr_GlobalVrefInSel_MSB  2
#define csr_GlobalVrefInSel_LSB  0
#define csr_GlobalVrefInSel_MASK 0x7
#define csr_GlobalVrefInDAC_RANGE  9:3
#define csr_GlobalVrefInDAC_BITS   6:0
#define csr_GlobalVrefInDAC_MSB  9
#define csr_GlobalVrefInDAC_LSB  3
#define csr_GlobalVrefInDAC_MASK 0x3f8
#define csr_GlobalVrefInTrim_RANGE  13:10
#define csr_GlobalVrefInTrim_BITS   3:0
#define csr_GlobalVrefInTrim_MSB  13
#define csr_GlobalVrefInTrim_LSB  10
#define csr_GlobalVrefInTrim_MASK 0x3c00
#define csr_GlobalVrefInMode_RANGE  14:14
#define csr_GlobalVrefInMode_BITS   0:0
#define csr_GlobalVrefInMode_MSB  14
#define csr_GlobalVrefInMode_LSB  14
#define csr_GlobalVrefInMode_MASK 0x4000
#define csr_Tsm1_RANGE  15:0
#define csr_Tsm1_BITS   15:0
#define csr_Tsm1_MSB  15
#define csr_Tsm1_LSB  0
#define csr_Tsm1_MASK 0xffff
#define csr_DtsmErrCnt_RANGE  15:0
#define csr_DtsmErrCnt_BITS   15:0
#define csr_DtsmErrCnt_MSB  15
#define csr_DtsmErrCnt_LSB  0
#define csr_DtsmErrCnt_MASK 0xffff
#define csr_SequenceReg0b46s0_RANGE  15:0
#define csr_SequenceReg0b46s0_BITS   15:0
#define csr_SequenceReg0b46s0_MSB  15
#define csr_SequenceReg0b46s0_LSB  0
#define csr_SequenceReg0b46s0_MASK 0xffff
#define csr_Tsm2_RANGE  0:0
#define csr_Tsm2_BITS   0:0
#define csr_Tsm2_MSB  0
#define csr_Tsm2_LSB  0
#define csr_Tsm2_MASK 0x1
#define csr_DtsmDisErrChk_RANGE  0:0
#define csr_DtsmDisErrChk_BITS   0:0
#define csr_DtsmDisErrChk_MSB  0
#define csr_DtsmDisErrChk_LSB  0
#define csr_DtsmDisErrChk_MASK 0x1
#define csr_SequenceReg0b46s1_RANGE  15:0
#define csr_SequenceReg0b46s1_BITS   15:0
#define csr_SequenceReg0b46s1_MSB  15
#define csr_SequenceReg0b46s1_LSB  0
#define csr_SequenceReg0b46s1_MASK 0xffff
#define csr_DfiWrDataCsDestMap_RANGE  7:0
#define csr_DfiWrDataCsDestMap_BITS   7:0
#define csr_DfiWrDataCsDestMap_MSB  7
#define csr_DfiWrDataCsDestMap_LSB  0
#define csr_DfiWrDataCsDestMap_MASK 0xff
#define csr_DfiWrDestm0_RANGE  1:0
#define csr_DfiWrDestm0_BITS   1:0
#define csr_DfiWrDestm0_MSB  1
#define csr_DfiWrDestm0_LSB  0
#define csr_DfiWrDestm0_MASK 0x3
#define csr_DfiWrDestm1_RANGE  3:2
#define csr_DfiWrDestm1_BITS   1:0
#define csr_DfiWrDestm1_MSB  3
#define csr_DfiWrDestm1_LSB  2
#define csr_DfiWrDestm1_MASK 0xc
#define csr_DfiWrDestm2_RANGE  5:4
#define csr_DfiWrDestm2_BITS   1:0
#define csr_DfiWrDestm2_MSB  5
#define csr_DfiWrDestm2_LSB  4
#define csr_DfiWrDestm2_MASK 0x30
#define csr_DfiWrDestm3_RANGE  7:6
#define csr_DfiWrDestm3_BITS   1:0
#define csr_DfiWrDestm3_MSB  7
#define csr_DfiWrDestm3_LSB  6
#define csr_DfiWrDestm3_MASK 0xc0
#define csr_Tsm3_RANGE  9:0
#define csr_Tsm3_BITS   9:0
#define csr_Tsm3_MSB  9
#define csr_Tsm3_LSB  0
#define csr_Tsm3_MASK 0x3ff
#define csr_DtsmClrErrCntMsk_RANGE  8:0
#define csr_DtsmClrErrCntMsk_BITS   8:0
#define csr_DtsmClrErrCntMsk_MSB  8
#define csr_DtsmClrErrCntMsk_LSB  0
#define csr_DtsmClrErrCntMsk_MASK 0x1ff
#define csr_DtsmClrErrCnt_RANGE  9:9
#define csr_DtsmClrErrCnt_BITS   0:0
#define csr_DtsmClrErrCnt_MSB  9
#define csr_DtsmClrErrCnt_LSB  9
#define csr_DtsmClrErrCnt_MASK 0x200
#define csr_SequenceReg0b46s2_RANGE  8:0
#define csr_SequenceReg0b46s2_BITS   8:0
#define csr_SequenceReg0b46s2_MSB  8
#define csr_SequenceReg0b46s2_LSB  0
#define csr_SequenceReg0b46s2_MASK 0x1ff
#define csr_MasUpdGoodCtr_RANGE  15:0
#define csr_MasUpdGoodCtr_BITS   15:0
#define csr_MasUpdGoodCtr_MSB  15
#define csr_MasUpdGoodCtr_LSB  0
#define csr_MasUpdGoodCtr_MASK 0xffff
#define csr_TxChkDataSelects_RANGE  1:0
#define csr_TxChkDataSelects_BITS   1:0
#define csr_TxChkDataSelects_MSB  1
#define csr_TxChkDataSelects_LSB  0
#define csr_TxChkDataSelects_MASK 0x3
#define csr_SelChktoTx_RANGE  0:0
#define csr_SelChktoTx_BITS   0:0
#define csr_SelChktoTx_MSB  0
#define csr_SelChktoTx_LSB  0
#define csr_SelChktoTx_MASK 0x1
#define csr_SelTxtoChk_RANGE  1:1
#define csr_SelTxtoChk_BITS   0:0
#define csr_SelTxtoChk_MSB  1
#define csr_SelTxtoChk_LSB  1
#define csr_SelTxtoChk_MASK 0x2
#define csr_SequenceReg0b47s0_RANGE  15:0
#define csr_SequenceReg0b47s0_BITS   15:0
#define csr_SequenceReg0b47s0_MSB  15
#define csr_SequenceReg0b47s0_LSB  0
#define csr_SequenceReg0b47s0_MASK 0xffff
#define csr_PhyUpd0GoodCtr_RANGE  15:0
#define csr_PhyUpd0GoodCtr_BITS   15:0
#define csr_PhyUpd0GoodCtr_MSB  15
#define csr_PhyUpd0GoodCtr_LSB  0
#define csr_PhyUpd0GoodCtr_MASK 0xffff
#define csr_DtsmUpThldXingInd_RANGE  8:0
#define csr_DtsmUpThldXingInd_BITS   8:0
#define csr_DtsmUpThldXingInd_MSB  8
#define csr_DtsmUpThldXingInd_LSB  0
#define csr_DtsmUpThldXingInd_MASK 0x1ff
#define csr_SequenceReg0b47s1_RANGE  15:0
#define csr_SequenceReg0b47s1_BITS   15:0
#define csr_SequenceReg0b47s1_MSB  15
#define csr_SequenceReg0b47s1_LSB  0
#define csr_SequenceReg0b47s1_MASK 0xffff
#define csr_PhyUpd1GoodCtr_RANGE  15:0
#define csr_PhyUpd1GoodCtr_BITS   15:0
#define csr_PhyUpd1GoodCtr_MSB  15
#define csr_PhyUpd1GoodCtr_LSB  0
#define csr_PhyUpd1GoodCtr_MASK 0xffff
#define csr_DtsmLoThldXingInd_RANGE  8:0
#define csr_DtsmLoThldXingInd_BITS   8:0
#define csr_DtsmLoThldXingInd_MSB  8
#define csr_DtsmLoThldXingInd_LSB  0
#define csr_DtsmLoThldXingInd_MASK 0x1ff
#define csr_SequenceReg0b47s2_RANGE  8:0
#define csr_SequenceReg0b47s2_BITS   8:0
#define csr_SequenceReg0b47s2_MSB  8
#define csr_SequenceReg0b47s2_LSB  0
#define csr_SequenceReg0b47s2_MASK 0x1ff
#define csr_CtlUpd0GoodCtr_RANGE  15:0
#define csr_CtlUpd0GoodCtr_BITS   15:0
#define csr_CtlUpd0GoodCtr_MSB  15
#define csr_CtlUpd0GoodCtr_LSB  0
#define csr_CtlUpd0GoodCtr_MASK 0xffff
#define csr_DbyteAllDtsmCtrl0_RANGE  8:0
#define csr_DbyteAllDtsmCtrl0_BITS   8:0
#define csr_DbyteAllDtsmCtrl0_MSB  8
#define csr_DbyteAllDtsmCtrl0_LSB  0
#define csr_DbyteAllDtsmCtrl0_MASK 0x1ff
#define csr_DtsmInhibDtsm_RANGE  8:0
#define csr_DtsmInhibDtsm_BITS   8:0
#define csr_DtsmInhibDtsm_MSB  8
#define csr_DtsmInhibDtsm_LSB  0
#define csr_DtsmInhibDtsm_MASK 0x1ff
#define csr_SequenceReg0b48s0_RANGE  15:0
#define csr_SequenceReg0b48s0_BITS   15:0
#define csr_SequenceReg0b48s0_MSB  15
#define csr_SequenceReg0b48s0_LSB  0
#define csr_SequenceReg0b48s0_MASK 0xffff
#define csr_CtlUpd1GoodCtr_RANGE  15:0
#define csr_CtlUpd1GoodCtr_BITS   15:0
#define csr_CtlUpd1GoodCtr_MSB  15
#define csr_CtlUpd1GoodCtr_LSB  0
#define csr_CtlUpd1GoodCtr_MASK 0xffff
#define csr_DbyteAllDtsmCtrl1_RANGE  8:0
#define csr_DbyteAllDtsmCtrl1_BITS   8:0
#define csr_DbyteAllDtsmCtrl1_MSB  8
#define csr_DbyteAllDtsmCtrl1_LSB  0
#define csr_DbyteAllDtsmCtrl1_MASK 0x1ff
#define csr_DtsmGateInc_RANGE  8:0
#define csr_DtsmGateInc_BITS   8:0
#define csr_DtsmGateInc_MSB  8
#define csr_DtsmGateInc_LSB  0
#define csr_DtsmGateInc_MASK 0x1ff
#define csr_SequenceReg0b48s1_RANGE  15:0
#define csr_SequenceReg0b48s1_BITS   15:0
#define csr_SequenceReg0b48s1_MSB  15
#define csr_SequenceReg0b48s1_LSB  0
#define csr_SequenceReg0b48s1_MASK 0xffff
#define csr_MasUpdFailCtr_RANGE  15:0
#define csr_MasUpdFailCtr_BITS   15:0
#define csr_MasUpdFailCtr_MSB  15
#define csr_MasUpdFailCtr_LSB  0
#define csr_MasUpdFailCtr_MASK 0xffff
#define csr_DbyteAllDtsmCtrl2_RANGE  8:0
#define csr_DbyteAllDtsmCtrl2_BITS   8:0
#define csr_DbyteAllDtsmCtrl2_MSB  8
#define csr_DbyteAllDtsmCtrl2_LSB  0
#define csr_DbyteAllDtsmCtrl2_MASK 0x1ff
#define csr_DtsmGateDec_RANGE  8:0
#define csr_DtsmGateDec_BITS   8:0
#define csr_DtsmGateDec_MSB  8
#define csr_DtsmGateDec_LSB  0
#define csr_DtsmGateDec_MASK 0x1ff
#define csr_SequenceReg0b48s2_RANGE  8:0
#define csr_SequenceReg0b48s2_BITS   8:0
#define csr_SequenceReg0b48s2_MSB  8
#define csr_SequenceReg0b48s2_LSB  0
#define csr_SequenceReg0b48s2_MASK 0x1ff
#define csr_PhyUpd0FailCtr_RANGE  15:0
#define csr_PhyUpd0FailCtr_BITS   15:0
#define csr_PhyUpd0FailCtr_MSB  15
#define csr_PhyUpd0FailCtr_LSB  0
#define csr_PhyUpd0FailCtr_MASK 0xffff
#define csr_SequenceReg0b49s0_RANGE  15:0
#define csr_SequenceReg0b49s0_BITS   15:0
#define csr_SequenceReg0b49s0_MSB  15
#define csr_SequenceReg0b49s0_LSB  0
#define csr_SequenceReg0b49s0_MASK 0xffff
#define csr_PhyUpd1FailCtr_RANGE  15:0
#define csr_PhyUpd1FailCtr_BITS   15:0
#define csr_PhyUpd1FailCtr_MSB  15
#define csr_PhyUpd1FailCtr_LSB  0
#define csr_PhyUpd1FailCtr_MASK 0xffff
#define csr_SequenceReg0b49s1_RANGE  15:0
#define csr_SequenceReg0b49s1_BITS   15:0
#define csr_SequenceReg0b49s1_MSB  15
#define csr_SequenceReg0b49s1_LSB  0
#define csr_SequenceReg0b49s1_MASK 0xffff
#define csr_PhyPerfCtrEnable_RANGE  7:0
#define csr_PhyPerfCtrEnable_BITS   7:0
#define csr_PhyPerfCtrEnable_MSB  7
#define csr_PhyPerfCtrEnable_LSB  0
#define csr_PhyPerfCtrEnable_MASK 0xff
#define csr_MasUpdGoodCtl_RANGE  0:0
#define csr_MasUpdGoodCtl_BITS   0:0
#define csr_MasUpdGoodCtl_MSB  0
#define csr_MasUpdGoodCtl_LSB  0
#define csr_MasUpdGoodCtl_MASK 0x1
#define csr_PhyUpd0GoodCtl_RANGE  1:1
#define csr_PhyUpd0GoodCtl_BITS   0:0
#define csr_PhyUpd0GoodCtl_MSB  1
#define csr_PhyUpd0GoodCtl_LSB  1
#define csr_PhyUpd0GoodCtl_MASK 0x2
#define csr_PhyUpd1GoodCtl_RANGE  2:2
#define csr_PhyUpd1GoodCtl_BITS   0:0
#define csr_PhyUpd1GoodCtl_MSB  2
#define csr_PhyUpd1GoodCtl_LSB  2
#define csr_PhyUpd1GoodCtl_MASK 0x4
#define csr_CtlUpd0GoodCtl_RANGE  3:3
#define csr_CtlUpd0GoodCtl_BITS   0:0
#define csr_CtlUpd0GoodCtl_MSB  3
#define csr_CtlUpd0GoodCtl_LSB  3
#define csr_CtlUpd0GoodCtl_MASK 0x8
#define csr_CtlUpd1GoodCtl_RANGE  4:4
#define csr_CtlUpd1GoodCtl_BITS   0:0
#define csr_CtlUpd1GoodCtl_MSB  4
#define csr_CtlUpd1GoodCtl_LSB  4
#define csr_CtlUpd1GoodCtl_MASK 0x10
#define csr_MasUpdFailCtl_RANGE  5:5
#define csr_MasUpdFailCtl_BITS   0:0
#define csr_MasUpdFailCtl_MSB  5
#define csr_MasUpdFailCtl_LSB  5
#define csr_MasUpdFailCtl_MASK 0x20
#define csr_PhyUpd0FailCtl_RANGE  6:6
#define csr_PhyUpd0FailCtl_BITS   0:0
#define csr_PhyUpd0FailCtl_MSB  6
#define csr_PhyUpd0FailCtl_LSB  6
#define csr_PhyUpd0FailCtl_MASK 0x40
#define csr_PhyUpd1FailCtl_RANGE  7:7
#define csr_PhyUpd1FailCtl_BITS   0:0
#define csr_PhyUpd1FailCtl_MSB  7
#define csr_PhyUpd1FailCtl_LSB  7
#define csr_PhyUpd1FailCtl_MASK 0x80
#define csr_SequenceReg0b49s2_RANGE  8:0
#define csr_SequenceReg0b49s2_BITS   8:0
#define csr_SequenceReg0b49s2_MSB  8
#define csr_SequenceReg0b49s2_LSB  0
#define csr_SequenceReg0b49s2_MASK 0x1ff
#define csr_DfiWrRdDataCsConfig_RANGE  1:0
#define csr_DfiWrRdDataCsConfig_BITS   1:0
#define csr_DfiWrRdDataCsConfig_MSB  1
#define csr_DfiWrRdDataCsConfig_LSB  0
#define csr_DfiWrRdDataCsConfig_MASK 0x3
#define csr_DfiWrDataCsPolarity_RANGE  0:0
#define csr_DfiWrDataCsPolarity_BITS   0:0
#define csr_DfiWrDataCsPolarity_MSB  0
#define csr_DfiWrDataCsPolarity_LSB  0
#define csr_DfiWrDataCsPolarity_MASK 0x1
#define csr_DfiRdDataCsPolarity_RANGE  1:1
#define csr_DfiRdDataCsPolarity_BITS   0:0
#define csr_DfiRdDataCsPolarity_MSB  1
#define csr_DfiRdDataCsPolarity_LSB  1
#define csr_DfiRdDataCsPolarity_MASK 0x2
#define csr_SequenceReg0b50s0_RANGE  15:0
#define csr_SequenceReg0b50s0_BITS   15:0
#define csr_SequenceReg0b50s0_MSB  15
#define csr_SequenceReg0b50s0_LSB  0
#define csr_SequenceReg0b50s0_MASK 0xffff
#define csr_TxDqDlyTg0_RANGE  8:0
#define csr_TxDqDlyTg0_BITS   8:0
#define csr_TxDqDlyTg0_MSB  8
#define csr_TxDqDlyTg0_LSB  0
#define csr_TxDqDlyTg0_MASK 0x1ff
#define csr_SequenceReg0b50s1_RANGE  15:0
#define csr_SequenceReg0b50s1_BITS   15:0
#define csr_SequenceReg0b50s1_MSB  15
#define csr_SequenceReg0b50s1_LSB  0
#define csr_SequenceReg0b50s1_MASK 0xffff
#define csr_AcsmCtrl23_RANGE  12:0
#define csr_AcsmCtrl23_BITS   12:0
#define csr_AcsmCtrl23_MSB  12
#define csr_AcsmCtrl23_LSB  0
#define csr_AcsmCtrl23_MASK 0x1fff
#define csr_AcsmCsMask_RANGE  7:0
#define csr_AcsmCsMask_BITS   7:0
#define csr_AcsmCsMask_MSB  7
#define csr_AcsmCsMask_LSB  0
#define csr_AcsmCsMask_MASK 0xff
#define csr_AcsmCsMode_RANGE  8:8
#define csr_AcsmCsMode_BITS   0:0
#define csr_AcsmCsMode_MSB  8
#define csr_AcsmCsMode_LSB  8
#define csr_AcsmCsMode_MASK 0x100
#define csr_AcsmParMask_RANGE  12:9
#define csr_AcsmParMask_BITS   3:0
#define csr_AcsmParMask_MSB  12
#define csr_AcsmParMask_LSB  9
#define csr_AcsmParMask_MASK 0x1e00
#define csr_TxDqDlyTg1_RANGE  8:0
#define csr_TxDqDlyTg1_BITS   8:0
#define csr_TxDqDlyTg1_MSB  8
#define csr_TxDqDlyTg1_LSB  0
#define csr_TxDqDlyTg1_MASK 0x1ff
#define csr_SequenceReg0b50s2_RANGE  8:0
#define csr_SequenceReg0b50s2_BITS   8:0
#define csr_SequenceReg0b50s2_MSB  8
#define csr_SequenceReg0b50s2_LSB  0
#define csr_SequenceReg0b50s2_MASK 0x1ff
#define csr_TxDqDlyTg2_RANGE  8:0
#define csr_TxDqDlyTg2_BITS   8:0
#define csr_TxDqDlyTg2_MSB  8
#define csr_TxDqDlyTg2_LSB  0
#define csr_TxDqDlyTg2_MASK 0x1ff
#define csr_SequenceReg0b51s0_RANGE  15:0
#define csr_SequenceReg0b51s0_BITS   15:0
#define csr_SequenceReg0b51s0_MSB  15
#define csr_SequenceReg0b51s0_LSB  0
#define csr_SequenceReg0b51s0_MASK 0xffff
#define csr_AcsmCkeVal_RANGE  3:0
#define csr_AcsmCkeVal_BITS   3:0
#define csr_AcsmCkeVal_MSB  3
#define csr_AcsmCkeVal_LSB  0
#define csr_AcsmCkeVal_MASK 0xf
#define csr_TxDqDlyTg3_RANGE  8:0
#define csr_TxDqDlyTg3_BITS   8:0
#define csr_TxDqDlyTg3_MSB  8
#define csr_TxDqDlyTg3_LSB  0
#define csr_TxDqDlyTg3_MASK 0x1ff
#define csr_SequenceReg0b51s1_RANGE  15:0
#define csr_SequenceReg0b51s1_BITS   15:0
#define csr_SequenceReg0b51s1_MSB  15
#define csr_SequenceReg0b51s1_LSB  0
#define csr_SequenceReg0b51s1_MASK 0xffff
#define csr_PllPwrDn_RANGE  0:0
#define csr_PllPwrDn_BITS   0:0
#define csr_PllPwrDn_MSB  0
#define csr_PllPwrDn_LSB  0
#define csr_PllPwrDn_MASK 0x1
#define csr_SequenceReg0b51s2_RANGE  8:0
#define csr_SequenceReg0b51s2_BITS   8:0
#define csr_SequenceReg0b51s2_MSB  8
#define csr_SequenceReg0b51s2_LSB  0
#define csr_SequenceReg0b51s2_MASK 0x1ff
#define csr_PllReset_RANGE  0:0
#define csr_PllReset_BITS   0:0
#define csr_PllReset_MSB  0
#define csr_PllReset_LSB  0
#define csr_PllReset_MASK 0x1
#define csr_SequenceReg0b52s0_RANGE  15:0
#define csr_SequenceReg0b52s0_BITS   15:0
#define csr_SequenceReg0b52s0_MSB  15
#define csr_SequenceReg0b52s0_LSB  0
#define csr_SequenceReg0b52s0_MASK 0xffff
#define csr_PllCtrl2_RANGE  4:0
#define csr_PllCtrl2_BITS   4:0
#define csr_PllCtrl2_MSB  4
#define csr_PllCtrl2_LSB  0
#define csr_PllCtrl2_MASK 0x1f
#define csr_PllFreqSel_RANGE  4:0
#define csr_PllFreqSel_BITS   4:0
#define csr_PllFreqSel_MSB  4
#define csr_PllFreqSel_LSB  0
#define csr_PllFreqSel_MASK 0x1f
#define csr_SequenceReg0b52s1_RANGE  15:0
#define csr_SequenceReg0b52s1_BITS   15:0
#define csr_SequenceReg0b52s1_MSB  15
#define csr_SequenceReg0b52s1_LSB  0
#define csr_SequenceReg0b52s1_MASK 0xffff
#define csr_PllCtrl0_RANGE  15:0
#define csr_PllCtrl0_BITS   15:0
#define csr_PllCtrl0_MSB  15
#define csr_PllCtrl0_LSB  0
#define csr_PllCtrl0_MASK 0xffff
#define csr_PllStandby_RANGE  0:0
#define csr_PllStandby_BITS   0:0
#define csr_PllStandby_MSB  0
#define csr_PllStandby_LSB  0
#define csr_PllStandby_MASK 0x1
#define csr_PllBypSel_RANGE  1:1
#define csr_PllBypSel_BITS   0:0
#define csr_PllBypSel_MSB  1
#define csr_PllBypSel_LSB  1
#define csr_PllBypSel_MASK 0x2
#define csr_PllX2Mode_RANGE  2:2
#define csr_PllX2Mode_BITS   0:0
#define csr_PllX2Mode_MSB  2
#define csr_PllX2Mode_LSB  2
#define csr_PllX2Mode_MASK 0x4
#define csr_PllOutBypEn_RANGE  3:3
#define csr_PllOutBypEn_BITS   0:0
#define csr_PllOutBypEn_MSB  3
#define csr_PllOutBypEn_LSB  3
#define csr_PllOutBypEn_MASK 0x8
#define csr_PllPreset_RANGE  4:4
#define csr_PllPreset_BITS   0:0
#define csr_PllPreset_MSB  4
#define csr_PllPreset_LSB  4
#define csr_PllPreset_MASK 0x10
#define csr_PllBypassMode_RANGE  5:5
#define csr_PllBypassMode_BITS   0:0
#define csr_PllBypassMode_MSB  5
#define csr_PllBypassMode_LSB  5
#define csr_PllBypassMode_MASK 0x20
#define csr_PllSelDfiFreqRatio_RANGE  6:6
#define csr_PllSelDfiFreqRatio_BITS   0:0
#define csr_PllSelDfiFreqRatio_MSB  6
#define csr_PllSelDfiFreqRatio_LSB  6
#define csr_PllSelDfiFreqRatio_MASK 0x40
#define csr_PllSyncBusFlush_RANGE  7:7
#define csr_PllSyncBusFlush_BITS   0:0
#define csr_PllSyncBusFlush_MSB  7
#define csr_PllSyncBusFlush_LSB  7
#define csr_PllSyncBusFlush_MASK 0x80
#define csr_PllSyncBusByp_RANGE  8:8
#define csr_PllSyncBusByp_BITS   0:0
#define csr_PllSyncBusByp_MSB  8
#define csr_PllSyncBusByp_LSB  8
#define csr_PllSyncBusByp_MASK 0x100
#define csr_PllReserved10x9_RANGE  10:9
#define csr_PllReserved10x9_BITS   1:0
#define csr_PllReserved10x9_MSB  10
#define csr_PllReserved10x9_LSB  9
#define csr_PllReserved10x9_MASK 0x600
#define csr_PllGearShift_RANGE  11:11
#define csr_PllGearShift_BITS   0:0
#define csr_PllGearShift_MSB  11
#define csr_PllGearShift_LSB  11
#define csr_PllGearShift_MASK 0x800
#define csr_PllLockCntSel_RANGE  12:12
#define csr_PllLockCntSel_BITS   0:0
#define csr_PllLockCntSel_MSB  12
#define csr_PllLockCntSel_LSB  12
#define csr_PllLockCntSel_MASK 0x1000
#define csr_PllLockPhSel_RANGE  14:13
#define csr_PllLockPhSel_BITS   1:0
#define csr_PllLockPhSel_MSB  14
#define csr_PllLockPhSel_LSB  13
#define csr_PllLockPhSel_MASK 0x6000
#define csr_PllSpareCtrl0_RANGE  15:15
#define csr_PllSpareCtrl0_BITS   0:0
#define csr_PllSpareCtrl0_MSB  15
#define csr_PllSpareCtrl0_LSB  15
#define csr_PllSpareCtrl0_MASK 0x8000
#define csr_SequenceReg0b52s2_RANGE  8:0
#define csr_SequenceReg0b52s2_BITS   8:0
#define csr_SequenceReg0b52s2_MSB  8
#define csr_SequenceReg0b52s2_LSB  0
#define csr_SequenceReg0b52s2_MASK 0x1ff
#define csr_PllCtrl1_RANGE  8:0
#define csr_PllCtrl1_BITS   8:0
#define csr_PllCtrl1_MSB  8
#define csr_PllCtrl1_LSB  0
#define csr_PllCtrl1_MASK 0x1ff
#define csr_PllCpIntCtrl_RANGE  4:0
#define csr_PllCpIntCtrl_BITS   4:0
#define csr_PllCpIntCtrl_MSB  4
#define csr_PllCpIntCtrl_LSB  0
#define csr_PllCpIntCtrl_MASK 0x1f
#define csr_PllCpPropCtrl_RANGE  8:5
#define csr_PllCpPropCtrl_BITS   3:0
#define csr_PllCpPropCtrl_MSB  8
#define csr_PllCpPropCtrl_LSB  5
#define csr_PllCpPropCtrl_MASK 0x1e0
#define csr_SequenceReg0b53s0_RANGE  15:0
#define csr_SequenceReg0b53s0_BITS   15:0
#define csr_SequenceReg0b53s0_MSB  15
#define csr_SequenceReg0b53s0_LSB  0
#define csr_SequenceReg0b53s0_MASK 0xffff
#define csr_LowSpeedClockDivider_RANGE  5:0
#define csr_LowSpeedClockDivider_BITS   5:0
#define csr_LowSpeedClockDivider_MSB  5
#define csr_LowSpeedClockDivider_LSB  0
#define csr_LowSpeedClockDivider_MASK 0x3f
#define csr_PllTst_RANGE  8:0
#define csr_PllTst_BITS   8:0
#define csr_PllTst_MSB  8
#define csr_PllTst_LSB  0
#define csr_PllTst_MASK 0x1ff
#define csr_PllAnaTstEn_RANGE  0:0
#define csr_PllAnaTstEn_BITS   0:0
#define csr_PllAnaTstEn_MSB  0
#define csr_PllAnaTstEn_LSB  0
#define csr_PllAnaTstEn_MASK 0x1
#define csr_PllAnaTstSel_RANGE  4:1
#define csr_PllAnaTstSel_BITS   3:0
#define csr_PllAnaTstSel_MSB  4
#define csr_PllAnaTstSel_LSB  1
#define csr_PllAnaTstSel_MASK 0x1e
#define csr_PllDigTstSel_RANGE  8:5
#define csr_PllDigTstSel_BITS   3:0
#define csr_PllDigTstSel_MSB  8
#define csr_PllDigTstSel_LSB  5
#define csr_PllDigTstSel_MASK 0x1e0
#define csr_SequenceReg0b53s1_RANGE  15:0
#define csr_SequenceReg0b53s1_BITS   15:0
#define csr_SequenceReg0b53s1_MSB  15
#define csr_SequenceReg0b53s1_LSB  0
#define csr_SequenceReg0b53s1_MASK 0xffff
#define csr_PllLockStatus_RANGE  0:0
#define csr_PllLockStatus_BITS   0:0
#define csr_PllLockStatus_MSB  0
#define csr_PllLockStatus_LSB  0
#define csr_PllLockStatus_MASK 0x1
#define csr_SequenceReg0b53s2_RANGE  8:0
#define csr_SequenceReg0b53s2_BITS   8:0
#define csr_SequenceReg0b53s2_MSB  8
#define csr_SequenceReg0b53s2_LSB  0
#define csr_SequenceReg0b53s2_MASK 0x1ff
#define csr_PllTestMode_RANGE  15:0
#define csr_PllTestMode_BITS   15:0
#define csr_PllTestMode_MSB  15
#define csr_PllTestMode_LSB  0
#define csr_PllTestMode_MASK 0xffff
#define csr_SequenceReg0b54s0_RANGE  15:0
#define csr_SequenceReg0b54s0_BITS   15:0
#define csr_SequenceReg0b54s0_MSB  15
#define csr_SequenceReg0b54s0_LSB  0
#define csr_SequenceReg0b54s0_MASK 0xffff
#define csr_PllCtrl3_RANGE  15:0
#define csr_PllCtrl3_BITS   15:0
#define csr_PllCtrl3_MSB  15
#define csr_PllCtrl3_LSB  0
#define csr_PllCtrl3_MASK 0xffff
#define csr_PllSpare_RANGE  3:0
#define csr_PllSpare_BITS   3:0
#define csr_PllSpare_MSB  3
#define csr_PllSpare_LSB  0
#define csr_PllSpare_MASK 0xf
#define csr_PllMaxRange_RANGE  8:4
#define csr_PllMaxRange_BITS   4:0
#define csr_PllMaxRange_MSB  8
#define csr_PllMaxRange_LSB  4
#define csr_PllMaxRange_MASK 0x1f0
#define csr_PllDacValIn_RANGE  13:9
#define csr_PllDacValIn_BITS   4:0
#define csr_PllDacValIn_MSB  13
#define csr_PllDacValIn_LSB  9
#define csr_PllDacValIn_MASK 0x3e00
#define csr_PllForceCal_RANGE  14:14
#define csr_PllForceCal_BITS   0:0
#define csr_PllForceCal_MSB  14
#define csr_PllForceCal_LSB  14
#define csr_PllForceCal_MASK 0x4000
#define csr_PllEnCal_RANGE  15:15
#define csr_PllEnCal_BITS   0:0
#define csr_PllEnCal_MSB  15
#define csr_PllEnCal_LSB  15
#define csr_PllEnCal_MASK 0x8000
#define csr_SequenceReg0b54s1_RANGE  15:0
#define csr_SequenceReg0b54s1_BITS   15:0
#define csr_SequenceReg0b54s1_MSB  15
#define csr_SequenceReg0b54s1_LSB  0
#define csr_SequenceReg0b54s1_MASK 0xffff
#define csr_PllCtrl4_RANGE  8:0
#define csr_PllCtrl4_BITS   8:0
#define csr_PllCtrl4_MSB  8
#define csr_PllCtrl4_LSB  0
#define csr_PllCtrl4_MASK 0x1ff
#define csr_PllCpIntGsCtrl_RANGE  4:0
#define csr_PllCpIntGsCtrl_BITS   4:0
#define csr_PllCpIntGsCtrl_MSB  4
#define csr_PllCpIntGsCtrl_LSB  0
#define csr_PllCpIntGsCtrl_MASK 0x1f
#define csr_PllCpPropGsCtrl_RANGE  8:5
#define csr_PllCpPropGsCtrl_BITS   3:0
#define csr_PllCpPropGsCtrl_MSB  8
#define csr_PllCpPropGsCtrl_LSB  5
#define csr_PllCpPropGsCtrl_MASK 0x1e0
#define csr_SequenceReg0b54s2_RANGE  8:0
#define csr_SequenceReg0b54s2_BITS   8:0
#define csr_SequenceReg0b54s2_MSB  8
#define csr_SequenceReg0b54s2_LSB  0
#define csr_SequenceReg0b54s2_MASK 0x1ff
#define csr_PllEndofCal_RANGE  0:0
#define csr_PllEndofCal_BITS   0:0
#define csr_PllEndofCal_MSB  0
#define csr_PllEndofCal_LSB  0
#define csr_PllEndofCal_MASK 0x1
#define csr_SequenceReg0b55s0_RANGE  15:0
#define csr_SequenceReg0b55s0_BITS   15:0
#define csr_SequenceReg0b55s0_MSB  15
#define csr_SequenceReg0b55s0_LSB  0
#define csr_SequenceReg0b55s0_MASK 0xffff
#define csr_PllStandbyEff_RANGE  0:0
#define csr_PllStandbyEff_BITS   0:0
#define csr_PllStandbyEff_MSB  0
#define csr_PllStandbyEff_LSB  0
#define csr_PllStandbyEff_MASK 0x1
#define csr_SequenceReg0b55s1_RANGE  15:0
#define csr_SequenceReg0b55s1_BITS   15:0
#define csr_SequenceReg0b55s1_MSB  15
#define csr_SequenceReg0b55s1_LSB  0
#define csr_SequenceReg0b55s1_MASK 0xffff
#define csr_PllDacValOut_RANGE  4:0
#define csr_PllDacValOut_BITS   4:0
#define csr_PllDacValOut_MSB  4
#define csr_PllDacValOut_LSB  0
#define csr_PllDacValOut_MASK 0x1f
#define csr_TxDqsDlyTg0_RANGE  9:0
#define csr_TxDqsDlyTg0_BITS   9:0
#define csr_TxDqsDlyTg0_MSB  9
#define csr_TxDqsDlyTg0_LSB  0
#define csr_TxDqsDlyTg0_MASK 0x3ff
#define csr_SequenceReg0b55s2_RANGE  8:0
#define csr_SequenceReg0b55s2_BITS   8:0
#define csr_SequenceReg0b55s2_MSB  8
#define csr_SequenceReg0b55s2_LSB  0
#define csr_SequenceReg0b55s2_MASK 0x1ff
#define csr_DlyTestSeq_RANGE  5:0
#define csr_DlyTestSeq_BITS   5:0
#define csr_DlyTestSeq_MSB  5
#define csr_DlyTestSeq_LSB  0
#define csr_DlyTestSeq_MASK 0x3f
#define csr_DlyTestEn_RANGE  0:0
#define csr_DlyTestEn_BITS   0:0
#define csr_DlyTestEn_MSB  0
#define csr_DlyTestEn_LSB  0
#define csr_DlyTestEn_MASK 0x1
#define csr_DlyTestCntInit_RANGE  1:1
#define csr_DlyTestCntInit_BITS   0:0
#define csr_DlyTestCntInit_MSB  1
#define csr_DlyTestCntInit_LSB  1
#define csr_DlyTestCntInit_MASK 0x2
#define csr_DlyTestEnOverride1_RANGE  2:2
#define csr_DlyTestEnOverride1_BITS   0:0
#define csr_DlyTestEnOverride1_MSB  2
#define csr_DlyTestEnOverride1_LSB  2
#define csr_DlyTestEnOverride1_MASK 0x4
#define csr_DlyTestEnOverride2_RANGE  3:3
#define csr_DlyTestEnOverride2_BITS   0:0
#define csr_DlyTestEnOverride2_MSB  3
#define csr_DlyTestEnOverride2_LSB  3
#define csr_DlyTestEnOverride2_MASK 0x8
#define csr_SyncDlyMultiplier_RANGE  5:4
#define csr_SyncDlyMultiplier_BITS   1:0
#define csr_SyncDlyMultiplier_MSB  5
#define csr_SyncDlyMultiplier_LSB  4
#define csr_SyncDlyMultiplier_MASK 0x30
#define csr_AcsmCsMapCtrl0_RANGE  14:0
#define csr_AcsmCsMapCtrl0_BITS   14:0
#define csr_AcsmCsMapCtrl0_MSB  14
#define csr_AcsmCsMapCtrl0_LSB  0
#define csr_AcsmCsMapCtrl0_MASK 0x7fff
#define csr_AcsmCsMap0_RANGE  7:0
#define csr_AcsmCsMap0_BITS   7:0
#define csr_AcsmCsMap0_MSB  7
#define csr_AcsmCsMap0_LSB  0
#define csr_AcsmCsMap0_MASK 0xff
#define csr_AcsmDestMap0_RANGE  11:8
#define csr_AcsmDestMap0_BITS   3:0
#define csr_AcsmDestMap0_MSB  11
#define csr_AcsmDestMap0_LSB  8
#define csr_AcsmDestMap0_MASK 0xf00
#define csr_AcsmOdtMap0_RANGE  14:12
#define csr_AcsmOdtMap0_BITS   2:0
#define csr_AcsmOdtMap0_MSB  14
#define csr_AcsmOdtMap0_LSB  12
#define csr_AcsmOdtMap0_MASK 0x7000
#define csr_TxDqsDlyTg1_RANGE  9:0
#define csr_TxDqsDlyTg1_BITS   9:0
#define csr_TxDqsDlyTg1_MSB  9
#define csr_TxDqsDlyTg1_LSB  0
#define csr_TxDqsDlyTg1_MASK 0x3ff
#define csr_SequenceReg0b56s0_RANGE  15:0
#define csr_SequenceReg0b56s0_BITS   15:0
#define csr_SequenceReg0b56s0_MSB  15
#define csr_SequenceReg0b56s0_LSB  0
#define csr_SequenceReg0b56s0_MASK 0xffff
#define csr_DlyTestRingSelDb_RANGE  4:0
#define csr_DlyTestRingSelDb_BITS   4:0
#define csr_DlyTestRingSelDb_MSB  4
#define csr_DlyTestRingSelDb_LSB  0
#define csr_DlyTestRingSelDb_MASK 0x1f
#define csr_DlyTestCuTDb_RANGE  4:0
#define csr_DlyTestCuTDb_BITS   4:0
#define csr_DlyTestCuTDb_MSB  4
#define csr_DlyTestCuTDb_LSB  0
#define csr_DlyTestCuTDb_MASK 0x1f
#define csr_AcsmCsMapCtrl1_RANGE  14:0
#define csr_AcsmCsMapCtrl1_BITS   14:0
#define csr_AcsmCsMapCtrl1_MSB  14
#define csr_AcsmCsMapCtrl1_LSB  0
#define csr_AcsmCsMapCtrl1_MASK 0x7fff
#define csr_AcsmCsMap1_RANGE  7:0
#define csr_AcsmCsMap1_BITS   7:0
#define csr_AcsmCsMap1_MSB  7
#define csr_AcsmCsMap1_LSB  0
#define csr_AcsmCsMap1_MASK 0xff
#define csr_AcsmDestMap1_RANGE  11:8
#define csr_AcsmDestMap1_BITS   3:0
#define csr_AcsmDestMap1_MSB  11
#define csr_AcsmDestMap1_LSB  8
#define csr_AcsmDestMap1_MASK 0xf00
#define csr_AcsmOdtMap1_RANGE  14:12
#define csr_AcsmOdtMap1_BITS   2:0
#define csr_AcsmOdtMap1_MSB  14
#define csr_AcsmOdtMap1_LSB  12
#define csr_AcsmOdtMap1_MASK 0x7000
#define csr_TxDqsDlyTg2_RANGE  9:0
#define csr_TxDqsDlyTg2_BITS   9:0
#define csr_TxDqsDlyTg2_MSB  9
#define csr_TxDqsDlyTg2_LSB  0
#define csr_TxDqsDlyTg2_MASK 0x3ff
#define csr_SequenceReg0b56s1_RANGE  15:0
#define csr_SequenceReg0b56s1_BITS   15:0
#define csr_SequenceReg0b56s1_MSB  15
#define csr_SequenceReg0b56s1_LSB  0
#define csr_SequenceReg0b56s1_MASK 0xffff
#define csr_DlyTestRingSelAc_RANGE  4:0
#define csr_DlyTestRingSelAc_BITS   4:0
#define csr_DlyTestRingSelAc_MSB  4
#define csr_DlyTestRingSelAc_LSB  0
#define csr_DlyTestRingSelAc_MASK 0x1f
#define csr_DlyTestCuTAc_RANGE  4:0
#define csr_DlyTestCuTAc_BITS   4:0
#define csr_DlyTestCuTAc_MSB  4
#define csr_DlyTestCuTAc_LSB  0
#define csr_DlyTestCuTAc_MASK 0x1f
#define csr_AcsmCsMapCtrl2_RANGE  14:0
#define csr_AcsmCsMapCtrl2_BITS   14:0
#define csr_AcsmCsMapCtrl2_MSB  14
#define csr_AcsmCsMapCtrl2_LSB  0
#define csr_AcsmCsMapCtrl2_MASK 0x7fff
#define csr_AcsmCsMap2_RANGE  7:0
#define csr_AcsmCsMap2_BITS   7:0
#define csr_AcsmCsMap2_MSB  7
#define csr_AcsmCsMap2_LSB  0
#define csr_AcsmCsMap2_MASK 0xff
#define csr_AcsmDestMap2_RANGE  11:8
#define csr_AcsmDestMap2_BITS   3:0
#define csr_AcsmDestMap2_MSB  11
#define csr_AcsmDestMap2_LSB  8
#define csr_AcsmDestMap2_MASK 0xf00
#define csr_AcsmOdtMap2_RANGE  14:12
#define csr_AcsmOdtMap2_BITS   2:0
#define csr_AcsmOdtMap2_MSB  14
#define csr_AcsmOdtMap2_LSB  12
#define csr_AcsmOdtMap2_MASK 0x7000
#define csr_TxDqsDlyTg3_RANGE  9:0
#define csr_TxDqsDlyTg3_BITS   9:0
#define csr_TxDqsDlyTg3_MSB  9
#define csr_TxDqsDlyTg3_LSB  0
#define csr_TxDqsDlyTg3_MASK 0x3ff
#define csr_SequenceReg0b56s2_RANGE  8:0
#define csr_SequenceReg0b56s2_BITS   8:0
#define csr_SequenceReg0b56s2_MSB  8
#define csr_SequenceReg0b56s2_LSB  0
#define csr_SequenceReg0b56s2_MASK 0x1ff
#define csr_DlyTestCntDfiClkIV_RANGE  15:0
#define csr_DlyTestCntDfiClkIV_BITS   15:0
#define csr_DlyTestCntDfiClkIV_MSB  15
#define csr_DlyTestCntDfiClkIV_LSB  0
#define csr_DlyTestCntDfiClkIV_MASK 0xffff
#define csr_AcsmCsMapCtrl3_RANGE  14:0
#define csr_AcsmCsMapCtrl3_BITS   14:0
#define csr_AcsmCsMapCtrl3_MSB  14
#define csr_AcsmCsMapCtrl3_LSB  0
#define csr_AcsmCsMapCtrl3_MASK 0x7fff
#define csr_AcsmCsMap3_RANGE  7:0
#define csr_AcsmCsMap3_BITS   7:0
#define csr_AcsmCsMap3_MSB  7
#define csr_AcsmCsMap3_LSB  0
#define csr_AcsmCsMap3_MASK 0xff
#define csr_AcsmDestMap3_RANGE  11:8
#define csr_AcsmDestMap3_BITS   3:0
#define csr_AcsmDestMap3_MSB  11
#define csr_AcsmDestMap3_LSB  8
#define csr_AcsmDestMap3_MASK 0xf00
#define csr_AcsmOdtMap3_RANGE  14:12
#define csr_AcsmOdtMap3_BITS   2:0
#define csr_AcsmOdtMap3_MSB  14
#define csr_AcsmOdtMap3_LSB  12
#define csr_AcsmOdtMap3_MASK 0x7000
#define csr_SequenceReg0b57s0_RANGE  15:0
#define csr_SequenceReg0b57s0_BITS   15:0
#define csr_SequenceReg0b57s0_MSB  15
#define csr_SequenceReg0b57s0_LSB  0
#define csr_SequenceReg0b57s0_MASK 0xffff
#define csr_DlyTestCntDfiClk_RANGE  15:0
#define csr_DlyTestCntDfiClk_BITS   15:0
#define csr_DlyTestCntDfiClk_MSB  15
#define csr_DlyTestCntDfiClk_LSB  0
#define csr_DlyTestCntDfiClk_MASK 0xffff
#define csr_AcsmCsMapCtrl4_RANGE  14:0
#define csr_AcsmCsMapCtrl4_BITS   14:0
#define csr_AcsmCsMapCtrl4_MSB  14
#define csr_AcsmCsMapCtrl4_LSB  0
#define csr_AcsmCsMapCtrl4_MASK 0x7fff
#define csr_AcsmCsMap4_RANGE  7:0
#define csr_AcsmCsMap4_BITS   7:0
#define csr_AcsmCsMap4_MSB  7
#define csr_AcsmCsMap4_LSB  0
#define csr_AcsmCsMap4_MASK 0xff
#define csr_AcsmDestMap4_RANGE  11:8
#define csr_AcsmDestMap4_BITS   3:0
#define csr_AcsmDestMap4_MSB  11
#define csr_AcsmDestMap4_LSB  8
#define csr_AcsmDestMap4_MASK 0xf00
#define csr_AcsmOdtMap4_RANGE  14:12
#define csr_AcsmOdtMap4_BITS   2:0
#define csr_AcsmOdtMap4_MSB  14
#define csr_AcsmOdtMap4_LSB  12
#define csr_AcsmOdtMap4_MASK 0x7000
#define csr_SequenceReg0b57s1_RANGE  15:0
#define csr_SequenceReg0b57s1_BITS   15:0
#define csr_SequenceReg0b57s1_MSB  15
#define csr_SequenceReg0b57s1_LSB  0
#define csr_SequenceReg0b57s1_MASK 0xffff
#define csr_DlyTestCntRingOscDb0_RANGE  15:0
#define csr_DlyTestCntRingOscDb0_BITS   15:0
#define csr_DlyTestCntRingOscDb0_MSB  15
#define csr_DlyTestCntRingOscDb0_LSB  0
#define csr_DlyTestCntRingOscDb0_MASK 0xffff
#define csr_AcsmCsMapCtrl5_RANGE  14:0
#define csr_AcsmCsMapCtrl5_BITS   14:0
#define csr_AcsmCsMapCtrl5_MSB  14
#define csr_AcsmCsMapCtrl5_LSB  0
#define csr_AcsmCsMapCtrl5_MASK 0x7fff
#define csr_AcsmCsMap5_RANGE  7:0
#define csr_AcsmCsMap5_BITS   7:0
#define csr_AcsmCsMap5_MSB  7
#define csr_AcsmCsMap5_LSB  0
#define csr_AcsmCsMap5_MASK 0xff
#define csr_AcsmDestMap5_RANGE  11:8
#define csr_AcsmDestMap5_BITS   3:0
#define csr_AcsmDestMap5_MSB  11
#define csr_AcsmDestMap5_LSB  8
#define csr_AcsmDestMap5_MASK 0xf00
#define csr_AcsmOdtMap5_RANGE  14:12
#define csr_AcsmOdtMap5_BITS   2:0
#define csr_AcsmOdtMap5_MSB  14
#define csr_AcsmOdtMap5_LSB  12
#define csr_AcsmOdtMap5_MASK 0x7000
#define csr_SequenceReg0b57s2_RANGE  8:0
#define csr_SequenceReg0b57s2_BITS   8:0
#define csr_SequenceReg0b57s2_MSB  8
#define csr_SequenceReg0b57s2_LSB  0
#define csr_SequenceReg0b57s2_MASK 0x1ff
#define csr_DlyTestCntRingOscDb1_RANGE  15:0
#define csr_DlyTestCntRingOscDb1_BITS   15:0
#define csr_DlyTestCntRingOscDb1_MSB  15
#define csr_DlyTestCntRingOscDb1_LSB  0
#define csr_DlyTestCntRingOscDb1_MASK 0xffff
#define csr_AcsmCsMapCtrl6_RANGE  14:0
#define csr_AcsmCsMapCtrl6_BITS   14:0
#define csr_AcsmCsMapCtrl6_MSB  14
#define csr_AcsmCsMapCtrl6_LSB  0
#define csr_AcsmCsMapCtrl6_MASK 0x7fff
#define csr_AcsmCsMap6_RANGE  7:0
#define csr_AcsmCsMap6_BITS   7:0
#define csr_AcsmCsMap6_MSB  7
#define csr_AcsmCsMap6_LSB  0
#define csr_AcsmCsMap6_MASK 0xff
#define csr_AcsmDestMap6_RANGE  11:8
#define csr_AcsmDestMap6_BITS   3:0
#define csr_AcsmDestMap6_MSB  11
#define csr_AcsmDestMap6_LSB  8
#define csr_AcsmDestMap6_MASK 0xf00
#define csr_AcsmOdtMap6_RANGE  14:12
#define csr_AcsmOdtMap6_BITS   2:0
#define csr_AcsmOdtMap6_MSB  14
#define csr_AcsmOdtMap6_LSB  12
#define csr_AcsmOdtMap6_MASK 0x7000
#define csr_SequenceReg0b58s0_RANGE  15:0
#define csr_SequenceReg0b58s0_BITS   15:0
#define csr_SequenceReg0b58s0_MSB  15
#define csr_SequenceReg0b58s0_LSB  0
#define csr_SequenceReg0b58s0_MASK 0xffff
#define csr_DlyTestCntRingOscDb2_RANGE  15:0
#define csr_DlyTestCntRingOscDb2_BITS   15:0
#define csr_DlyTestCntRingOscDb2_MSB  15
#define csr_DlyTestCntRingOscDb2_LSB  0
#define csr_DlyTestCntRingOscDb2_MASK 0xffff
#define csr_AcsmCsMapCtrl7_RANGE  14:0
#define csr_AcsmCsMapCtrl7_BITS   14:0
#define csr_AcsmCsMapCtrl7_MSB  14
#define csr_AcsmCsMapCtrl7_LSB  0
#define csr_AcsmCsMapCtrl7_MASK 0x7fff
#define csr_AcsmCsMap7_RANGE  7:0
#define csr_AcsmCsMap7_BITS   7:0
#define csr_AcsmCsMap7_MSB  7
#define csr_AcsmCsMap7_LSB  0
#define csr_AcsmCsMap7_MASK 0xff
#define csr_AcsmDestMap7_RANGE  11:8
#define csr_AcsmDestMap7_BITS   3:0
#define csr_AcsmDestMap7_MSB  11
#define csr_AcsmDestMap7_LSB  8
#define csr_AcsmDestMap7_MASK 0xf00
#define csr_AcsmOdtMap7_RANGE  14:12
#define csr_AcsmOdtMap7_BITS   2:0
#define csr_AcsmOdtMap7_MSB  14
#define csr_AcsmOdtMap7_LSB  12
#define csr_AcsmOdtMap7_MASK 0x7000
#define csr_SequenceReg0b58s1_RANGE  15:0
#define csr_SequenceReg0b58s1_BITS   15:0
#define csr_SequenceReg0b58s1_MSB  15
#define csr_SequenceReg0b58s1_LSB  0
#define csr_SequenceReg0b58s1_MASK 0xffff
#define csr_DlyTestCntRingOscDb3_RANGE  15:0
#define csr_DlyTestCntRingOscDb3_BITS   15:0
#define csr_DlyTestCntRingOscDb3_MSB  15
#define csr_DlyTestCntRingOscDb3_LSB  0
#define csr_DlyTestCntRingOscDb3_MASK 0xffff
#define csr_AcsmCsMapCtrl8_RANGE  14:0
#define csr_AcsmCsMapCtrl8_BITS   14:0
#define csr_AcsmCsMapCtrl8_MSB  14
#define csr_AcsmCsMapCtrl8_LSB  0
#define csr_AcsmCsMapCtrl8_MASK 0x7fff
#define csr_AcsmCsMap8_RANGE  7:0
#define csr_AcsmCsMap8_BITS   7:0
#define csr_AcsmCsMap8_MSB  7
#define csr_AcsmCsMap8_LSB  0
#define csr_AcsmCsMap8_MASK 0xff
#define csr_AcsmDestMap8_RANGE  11:8
#define csr_AcsmDestMap8_BITS   3:0
#define csr_AcsmDestMap8_MSB  11
#define csr_AcsmDestMap8_LSB  8
#define csr_AcsmDestMap8_MASK 0xf00
#define csr_AcsmOdtMap8_RANGE  14:12
#define csr_AcsmOdtMap8_BITS   2:0
#define csr_AcsmOdtMap8_MSB  14
#define csr_AcsmOdtMap8_LSB  12
#define csr_AcsmOdtMap8_MASK 0x7000
#define csr_SequenceReg0b58s2_RANGE  8:0
#define csr_SequenceReg0b58s2_BITS   8:0
#define csr_SequenceReg0b58s2_MSB  8
#define csr_SequenceReg0b58s2_LSB  0
#define csr_SequenceReg0b58s2_MASK 0x1ff
#define csr_DlyTestCntRingOscDb4_RANGE  15:0
#define csr_DlyTestCntRingOscDb4_BITS   15:0
#define csr_DlyTestCntRingOscDb4_MSB  15
#define csr_DlyTestCntRingOscDb4_LSB  0
#define csr_DlyTestCntRingOscDb4_MASK 0xffff
#define csr_AcsmCsMapCtrl9_RANGE  14:0
#define csr_AcsmCsMapCtrl9_BITS   14:0
#define csr_AcsmCsMapCtrl9_MSB  14
#define csr_AcsmCsMapCtrl9_LSB  0
#define csr_AcsmCsMapCtrl9_MASK 0x7fff
#define csr_AcsmCsMap9_RANGE  7:0
#define csr_AcsmCsMap9_BITS   7:0
#define csr_AcsmCsMap9_MSB  7
#define csr_AcsmCsMap9_LSB  0
#define csr_AcsmCsMap9_MASK 0xff
#define csr_AcsmDestMap9_RANGE  11:8
#define csr_AcsmDestMap9_BITS   3:0
#define csr_AcsmDestMap9_MSB  11
#define csr_AcsmDestMap9_LSB  8
#define csr_AcsmDestMap9_MASK 0xf00
#define csr_AcsmOdtMap9_RANGE  14:12
#define csr_AcsmOdtMap9_BITS   2:0
#define csr_AcsmOdtMap9_MSB  14
#define csr_AcsmOdtMap9_LSB  12
#define csr_AcsmOdtMap9_MASK 0x7000
#define csr_SequenceReg0b59s0_RANGE  15:0
#define csr_SequenceReg0b59s0_BITS   15:0
#define csr_SequenceReg0b59s0_MSB  15
#define csr_SequenceReg0b59s0_LSB  0
#define csr_SequenceReg0b59s0_MASK 0xffff
#define csr_DlyTestCntRingOscDb5_RANGE  15:0
#define csr_DlyTestCntRingOscDb5_BITS   15:0
#define csr_DlyTestCntRingOscDb5_MSB  15
#define csr_DlyTestCntRingOscDb5_LSB  0
#define csr_DlyTestCntRingOscDb5_MASK 0xffff
#define csr_AcsmCsMapCtrl10_RANGE  14:0
#define csr_AcsmCsMapCtrl10_BITS   14:0
#define csr_AcsmCsMapCtrl10_MSB  14
#define csr_AcsmCsMapCtrl10_LSB  0
#define csr_AcsmCsMapCtrl10_MASK 0x7fff
#define csr_AcsmCsMap10_RANGE  7:0
#define csr_AcsmCsMap10_BITS   7:0
#define csr_AcsmCsMap10_MSB  7
#define csr_AcsmCsMap10_LSB  0
#define csr_AcsmCsMap10_MASK 0xff
#define csr_AcsmDestMap10_RANGE  11:8
#define csr_AcsmDestMap10_BITS   3:0
#define csr_AcsmDestMap10_MSB  11
#define csr_AcsmDestMap10_LSB  8
#define csr_AcsmDestMap10_MASK 0xf00
#define csr_AcsmOdtMap10_RANGE  14:12
#define csr_AcsmOdtMap10_BITS   2:0
#define csr_AcsmOdtMap10_MSB  14
#define csr_AcsmOdtMap10_LSB  12
#define csr_AcsmOdtMap10_MASK 0x7000
#define csr_SequenceReg0b59s1_RANGE  15:0
#define csr_SequenceReg0b59s1_BITS   15:0
#define csr_SequenceReg0b59s1_MSB  15
#define csr_SequenceReg0b59s1_LSB  0
#define csr_SequenceReg0b59s1_MASK 0xffff
#define csr_DlyTestCntRingOscDb6_RANGE  15:0
#define csr_DlyTestCntRingOscDb6_BITS   15:0
#define csr_DlyTestCntRingOscDb6_MSB  15
#define csr_DlyTestCntRingOscDb6_LSB  0
#define csr_DlyTestCntRingOscDb6_MASK 0xffff
#define csr_AcsmCsMapCtrl11_RANGE  14:0
#define csr_AcsmCsMapCtrl11_BITS   14:0
#define csr_AcsmCsMapCtrl11_MSB  14
#define csr_AcsmCsMapCtrl11_LSB  0
#define csr_AcsmCsMapCtrl11_MASK 0x7fff
#define csr_AcsmCsMap11_RANGE  7:0
#define csr_AcsmCsMap11_BITS   7:0
#define csr_AcsmCsMap11_MSB  7
#define csr_AcsmCsMap11_LSB  0
#define csr_AcsmCsMap11_MASK 0xff
#define csr_AcsmDestMap11_RANGE  11:8
#define csr_AcsmDestMap11_BITS   3:0
#define csr_AcsmDestMap11_MSB  11
#define csr_AcsmDestMap11_LSB  8
#define csr_AcsmDestMap11_MASK 0xf00
#define csr_AcsmOdtMap11_RANGE  14:12
#define csr_AcsmOdtMap11_BITS   2:0
#define csr_AcsmOdtMap11_MSB  14
#define csr_AcsmOdtMap11_LSB  12
#define csr_AcsmOdtMap11_MASK 0x7000
#define csr_SequenceReg0b59s2_RANGE  8:0
#define csr_SequenceReg0b59s2_BITS   8:0
#define csr_SequenceReg0b59s2_MSB  8
#define csr_SequenceReg0b59s2_LSB  0
#define csr_SequenceReg0b59s2_MASK 0x1ff
#define csr_DlyTestCntRingOscDb7_RANGE  15:0
#define csr_DlyTestCntRingOscDb7_BITS   15:0
#define csr_DlyTestCntRingOscDb7_MSB  15
#define csr_DlyTestCntRingOscDb7_LSB  0
#define csr_DlyTestCntRingOscDb7_MASK 0xffff
#define csr_AcsmCsMapCtrl12_RANGE  14:0
#define csr_AcsmCsMapCtrl12_BITS   14:0
#define csr_AcsmCsMapCtrl12_MSB  14
#define csr_AcsmCsMapCtrl12_LSB  0
#define csr_AcsmCsMapCtrl12_MASK 0x7fff
#define csr_AcsmCsMap12_RANGE  7:0
#define csr_AcsmCsMap12_BITS   7:0
#define csr_AcsmCsMap12_MSB  7
#define csr_AcsmCsMap12_LSB  0
#define csr_AcsmCsMap12_MASK 0xff
#define csr_AcsmDestMap12_RANGE  11:8
#define csr_AcsmDestMap12_BITS   3:0
#define csr_AcsmDestMap12_MSB  11
#define csr_AcsmDestMap12_LSB  8
#define csr_AcsmDestMap12_MASK 0xf00
#define csr_AcsmOdtMap12_RANGE  14:12
#define csr_AcsmOdtMap12_BITS   2:0
#define csr_AcsmOdtMap12_MSB  14
#define csr_AcsmOdtMap12_LSB  12
#define csr_AcsmOdtMap12_MASK 0x7000
#define csr_SequenceReg0b60s0_RANGE  15:0
#define csr_SequenceReg0b60s0_BITS   15:0
#define csr_SequenceReg0b60s0_MSB  15
#define csr_SequenceReg0b60s0_LSB  0
#define csr_SequenceReg0b60s0_MASK 0xffff
#define csr_DlyTestCntRingOscDb8_RANGE  15:0
#define csr_DlyTestCntRingOscDb8_BITS   15:0
#define csr_DlyTestCntRingOscDb8_MSB  15
#define csr_DlyTestCntRingOscDb8_LSB  0
#define csr_DlyTestCntRingOscDb8_MASK 0xffff
#define csr_AcsmCsMapCtrl13_RANGE  14:0
#define csr_AcsmCsMapCtrl13_BITS   14:0
#define csr_AcsmCsMapCtrl13_MSB  14
#define csr_AcsmCsMapCtrl13_LSB  0
#define csr_AcsmCsMapCtrl13_MASK 0x7fff
#define csr_AcsmCsMap13_RANGE  7:0
#define csr_AcsmCsMap13_BITS   7:0
#define csr_AcsmCsMap13_MSB  7
#define csr_AcsmCsMap13_LSB  0
#define csr_AcsmCsMap13_MASK 0xff
#define csr_AcsmDestMap13_RANGE  11:8
#define csr_AcsmDestMap13_BITS   3:0
#define csr_AcsmDestMap13_MSB  11
#define csr_AcsmDestMap13_LSB  8
#define csr_AcsmDestMap13_MASK 0xf00
#define csr_AcsmOdtMap13_RANGE  14:12
#define csr_AcsmOdtMap13_BITS   2:0
#define csr_AcsmOdtMap13_MSB  14
#define csr_AcsmOdtMap13_LSB  12
#define csr_AcsmOdtMap13_MASK 0x7000
#define csr_SequenceReg0b60s1_RANGE  15:0
#define csr_SequenceReg0b60s1_BITS   15:0
#define csr_SequenceReg0b60s1_MSB  15
#define csr_SequenceReg0b60s1_LSB  0
#define csr_SequenceReg0b60s1_MASK 0xffff
#define csr_DlyTestCntRingOscDb9_RANGE  15:0
#define csr_DlyTestCntRingOscDb9_BITS   15:0
#define csr_DlyTestCntRingOscDb9_MSB  15
#define csr_DlyTestCntRingOscDb9_LSB  0
#define csr_DlyTestCntRingOscDb9_MASK 0xffff
#define csr_AcsmCsMapCtrl14_RANGE  14:0
#define csr_AcsmCsMapCtrl14_BITS   14:0
#define csr_AcsmCsMapCtrl14_MSB  14
#define csr_AcsmCsMapCtrl14_LSB  0
#define csr_AcsmCsMapCtrl14_MASK 0x7fff
#define csr_AcsmCsMap14_RANGE  7:0
#define csr_AcsmCsMap14_BITS   7:0
#define csr_AcsmCsMap14_MSB  7
#define csr_AcsmCsMap14_LSB  0
#define csr_AcsmCsMap14_MASK 0xff
#define csr_AcsmDestMap14_RANGE  11:8
#define csr_AcsmDestMap14_BITS   3:0
#define csr_AcsmDestMap14_MSB  11
#define csr_AcsmDestMap14_LSB  8
#define csr_AcsmDestMap14_MASK 0xf00
#define csr_AcsmOdtMap14_RANGE  14:12
#define csr_AcsmOdtMap14_BITS   2:0
#define csr_AcsmOdtMap14_MSB  14
#define csr_AcsmOdtMap14_LSB  12
#define csr_AcsmOdtMap14_MASK 0x7000
#define csr_SequenceReg0b60s2_RANGE  8:0
#define csr_SequenceReg0b60s2_BITS   8:0
#define csr_SequenceReg0b60s2_MSB  8
#define csr_SequenceReg0b60s2_LSB  0
#define csr_SequenceReg0b60s2_MASK 0x1ff
#define csr_DlyTestCntRingOscAc_RANGE  15:0
#define csr_DlyTestCntRingOscAc_BITS   15:0
#define csr_DlyTestCntRingOscAc_MSB  15
#define csr_DlyTestCntRingOscAc_LSB  0
#define csr_DlyTestCntRingOscAc_MASK 0xffff
#define csr_AcsmCsMapCtrl15_RANGE  14:0
#define csr_AcsmCsMapCtrl15_BITS   14:0
#define csr_AcsmCsMapCtrl15_MSB  14
#define csr_AcsmCsMapCtrl15_LSB  0
#define csr_AcsmCsMapCtrl15_MASK 0x7fff
#define csr_AcsmCsMap15_RANGE  7:0
#define csr_AcsmCsMap15_BITS   7:0
#define csr_AcsmCsMap15_MSB  7
#define csr_AcsmCsMap15_LSB  0
#define csr_AcsmCsMap15_MASK 0xff
#define csr_AcsmDestMap15_RANGE  11:8
#define csr_AcsmDestMap15_BITS   3:0
#define csr_AcsmDestMap15_MSB  11
#define csr_AcsmDestMap15_LSB  8
#define csr_AcsmDestMap15_MASK 0xf00
#define csr_AcsmOdtMap15_RANGE  14:12
#define csr_AcsmOdtMap15_BITS   2:0
#define csr_AcsmOdtMap15_MSB  14
#define csr_AcsmOdtMap15_LSB  12
#define csr_AcsmOdtMap15_MASK 0x7000
#define csr_SequenceReg0b61s0_RANGE  15:0
#define csr_SequenceReg0b61s0_BITS   15:0
#define csr_SequenceReg0b61s0_MSB  15
#define csr_SequenceReg0b61s0_LSB  0
#define csr_SequenceReg0b61s0_MASK 0xffff
#define csr_MstLcdlDbgCntl_RANGE  11:0
#define csr_MstLcdlDbgCntl_BITS   11:0
#define csr_MstLcdlDbgCntl_MSB  11
#define csr_MstLcdlDbgCntl_LSB  0
#define csr_MstLcdlDbgCntl_MASK 0xfff
#define csr_MstLcdlFineOvrVal_RANGE  8:0
#define csr_MstLcdlFineOvrVal_BITS   8:0
#define csr_MstLcdlFineOvrVal_MSB  8
#define csr_MstLcdlFineOvrVal_LSB  0
#define csr_MstLcdlFineOvrVal_MASK 0x1ff
#define csr_MstLcdlFineOvr_RANGE  9:9
#define csr_MstLcdlFineOvr_BITS   0:0
#define csr_MstLcdlFineOvr_MSB  9
#define csr_MstLcdlFineOvr_LSB  9
#define csr_MstLcdlFineOvr_MASK 0x200
#define csr_MstLcdlFineSnap_RANGE  10:10
#define csr_MstLcdlFineSnap_BITS   0:0
#define csr_MstLcdlFineSnap_MSB  10
#define csr_MstLcdlFineSnap_LSB  10
#define csr_MstLcdlFineSnap_MASK 0x400
#define csr_MstLcdlTstEnable_RANGE  11:11
#define csr_MstLcdlTstEnable_BITS   0:0
#define csr_MstLcdlTstEnable_MSB  11
#define csr_MstLcdlTstEnable_LSB  11
#define csr_MstLcdlTstEnable_MASK 0x800
#define csr_AcsmOdtCtrl0_RANGE  7:0
#define csr_AcsmOdtCtrl0_BITS   7:0
#define csr_AcsmOdtCtrl0_MSB  7
#define csr_AcsmOdtCtrl0_LSB  0
#define csr_AcsmOdtCtrl0_MASK 0xff
#define csr_AcsmOdtWrPatCs0_RANGE  3:0
#define csr_AcsmOdtWrPatCs0_BITS   3:0
#define csr_AcsmOdtWrPatCs0_MSB  3
#define csr_AcsmOdtWrPatCs0_LSB  0
#define csr_AcsmOdtWrPatCs0_MASK 0xf
#define csr_AcsmOdtRdPatCs0_RANGE  7:4
#define csr_AcsmOdtRdPatCs0_BITS   3:0
#define csr_AcsmOdtRdPatCs0_MSB  7
#define csr_AcsmOdtRdPatCs0_LSB  4
#define csr_AcsmOdtRdPatCs0_MASK 0xf0
#define csr_SequenceReg0b61s1_RANGE  15:0
#define csr_SequenceReg0b61s1_BITS   15:0
#define csr_SequenceReg0b61s1_MSB  15
#define csr_SequenceReg0b61s1_LSB  0
#define csr_SequenceReg0b61s1_MASK 0xffff
#define csr_MstLcdl0DbgRes_RANGE  12:0
#define csr_MstLcdl0DbgRes_BITS   12:0
#define csr_MstLcdl0DbgRes_MSB  12
#define csr_MstLcdl0DbgRes_LSB  0
#define csr_MstLcdl0DbgRes_MASK 0x1fff
#define csr_MstLcdl0FineSnapVal_RANGE  8:0
#define csr_MstLcdl0FineSnapVal_BITS   8:0
#define csr_MstLcdl0FineSnapVal_MSB  8
#define csr_MstLcdl0FineSnapVal_LSB  0
#define csr_MstLcdl0FineSnapVal_MASK 0x1ff
#define csr_MstLcdl0PhdSnapVal_RANGE  9:9
#define csr_MstLcdl0PhdSnapVal_BITS   0:0
#define csr_MstLcdl0PhdSnapVal_MSB  9
#define csr_MstLcdl0PhdSnapVal_LSB  9
#define csr_MstLcdl0PhdSnapVal_MASK 0x200
#define csr_MstLcdl0StickyLock_RANGE  10:10
#define csr_MstLcdl0StickyLock_BITS   0:0
#define csr_MstLcdl0StickyLock_MSB  10
#define csr_MstLcdl0StickyLock_LSB  10
#define csr_MstLcdl0StickyLock_MASK 0x400
#define csr_MstLcdl0StickyUnlock_RANGE  11:11
#define csr_MstLcdl0StickyUnlock_BITS   0:0
#define csr_MstLcdl0StickyUnlock_MSB  11
#define csr_MstLcdl0StickyUnlock_LSB  11
#define csr_MstLcdl0StickyUnlock_MASK 0x800
#define csr_MstLcdl0LiveLock_RANGE  12:12
#define csr_MstLcdl0LiveLock_BITS   0:0
#define csr_MstLcdl0LiveLock_MSB  12
#define csr_MstLcdl0LiveLock_LSB  12
#define csr_MstLcdl0LiveLock_MASK 0x1000
#define csr_AcsmOdtCtrl1_RANGE  7:0
#define csr_AcsmOdtCtrl1_BITS   7:0
#define csr_AcsmOdtCtrl1_MSB  7
#define csr_AcsmOdtCtrl1_LSB  0
#define csr_AcsmOdtCtrl1_MASK 0xff
#define csr_AcsmOdtWrPatCs1_RANGE  3:0
#define csr_AcsmOdtWrPatCs1_BITS   3:0
#define csr_AcsmOdtWrPatCs1_MSB  3
#define csr_AcsmOdtWrPatCs1_LSB  0
#define csr_AcsmOdtWrPatCs1_MASK 0xf
#define csr_AcsmOdtRdPatCs1_RANGE  7:4
#define csr_AcsmOdtRdPatCs1_BITS   3:0
#define csr_AcsmOdtRdPatCs1_MSB  7
#define csr_AcsmOdtRdPatCs1_LSB  4
#define csr_AcsmOdtRdPatCs1_MASK 0xf0
#define csr_SequenceReg0b61s2_RANGE  8:0
#define csr_SequenceReg0b61s2_BITS   8:0
#define csr_SequenceReg0b61s2_MSB  8
#define csr_SequenceReg0b61s2_LSB  0
#define csr_SequenceReg0b61s2_MASK 0x1ff
#define csr_MstLcdl1DbgRes_RANGE  12:0
#define csr_MstLcdl1DbgRes_BITS   12:0
#define csr_MstLcdl1DbgRes_MSB  12
#define csr_MstLcdl1DbgRes_LSB  0
#define csr_MstLcdl1DbgRes_MASK 0x1fff
#define csr_MstLcdl1FineSnapVal_RANGE  8:0
#define csr_MstLcdl1FineSnapVal_BITS   8:0
#define csr_MstLcdl1FineSnapVal_MSB  8
#define csr_MstLcdl1FineSnapVal_LSB  0
#define csr_MstLcdl1FineSnapVal_MASK 0x1ff
#define csr_MstLcdl1PhdSnapVal_RANGE  9:9
#define csr_MstLcdl1PhdSnapVal_BITS   0:0
#define csr_MstLcdl1PhdSnapVal_MSB  9
#define csr_MstLcdl1PhdSnapVal_LSB  9
#define csr_MstLcdl1PhdSnapVal_MASK 0x200
#define csr_MstLcdl1StickyLock_RANGE  10:10
#define csr_MstLcdl1StickyLock_BITS   0:0
#define csr_MstLcdl1StickyLock_MSB  10
#define csr_MstLcdl1StickyLock_LSB  10
#define csr_MstLcdl1StickyLock_MASK 0x400
#define csr_MstLcdl1StickyUnlock_RANGE  11:11
#define csr_MstLcdl1StickyUnlock_BITS   0:0
#define csr_MstLcdl1StickyUnlock_MSB  11
#define csr_MstLcdl1StickyUnlock_LSB  11
#define csr_MstLcdl1StickyUnlock_MASK 0x800
#define csr_MstLcdl1LiveLock_RANGE  12:12
#define csr_MstLcdl1LiveLock_BITS   0:0
#define csr_MstLcdl1LiveLock_MSB  12
#define csr_MstLcdl1LiveLock_LSB  12
#define csr_MstLcdl1LiveLock_MASK 0x1000
#define csr_AcsmOdtCtrl2_RANGE  7:0
#define csr_AcsmOdtCtrl2_BITS   7:0
#define csr_AcsmOdtCtrl2_MSB  7
#define csr_AcsmOdtCtrl2_LSB  0
#define csr_AcsmOdtCtrl2_MASK 0xff
#define csr_AcsmOdtWrPatCs2_RANGE  3:0
#define csr_AcsmOdtWrPatCs2_BITS   3:0
#define csr_AcsmOdtWrPatCs2_MSB  3
#define csr_AcsmOdtWrPatCs2_LSB  0
#define csr_AcsmOdtWrPatCs2_MASK 0xf
#define csr_AcsmOdtRdPatCs2_RANGE  7:4
#define csr_AcsmOdtRdPatCs2_BITS   3:0
#define csr_AcsmOdtRdPatCs2_MSB  7
#define csr_AcsmOdtRdPatCs2_LSB  4
#define csr_AcsmOdtRdPatCs2_MASK 0xf0
#define csr_SequenceReg0b62s0_RANGE  15:0
#define csr_SequenceReg0b62s0_BITS   15:0
#define csr_SequenceReg0b62s0_MSB  15
#define csr_SequenceReg0b62s0_LSB  0
#define csr_SequenceReg0b62s0_MASK 0xffff
#define csr_LcdlDbgCntl_RANGE  15:0
#define csr_LcdlDbgCntl_BITS   15:0
#define csr_LcdlDbgCntl_MSB  15
#define csr_LcdlDbgCntl_LSB  0
#define csr_LcdlDbgCntl_MASK 0xffff
#define csr_LcdlFineOvrVal_RANGE  8:0
#define csr_LcdlFineOvrVal_BITS   8:0
#define csr_LcdlFineOvrVal_MSB  8
#define csr_LcdlFineOvrVal_LSB  0
#define csr_LcdlFineOvrVal_MASK 0x1ff
#define csr_LcdlFineOvr_RANGE  9:9
#define csr_LcdlFineOvr_BITS   0:0
#define csr_LcdlFineOvr_MSB  9
#define csr_LcdlFineOvr_LSB  9
#define csr_LcdlFineOvr_MASK 0x200
#define csr_LcdlFineSnap_RANGE  10:10
#define csr_LcdlFineSnap_BITS   0:0
#define csr_LcdlFineSnap_MSB  10
#define csr_LcdlFineSnap_LSB  10
#define csr_LcdlFineSnap_MASK 0x400
#define csr_LcdlTstEnable_RANGE  11:11
#define csr_LcdlTstEnable_BITS   0:0
#define csr_LcdlTstEnable_MSB  11
#define csr_LcdlTstEnable_LSB  11
#define csr_LcdlTstEnable_MASK 0x800
#define csr_LcdlStatusSel_RANGE  15:12
#define csr_LcdlStatusSel_BITS   3:0
#define csr_LcdlStatusSel_MSB  15
#define csr_LcdlStatusSel_LSB  12
#define csr_LcdlStatusSel_MASK 0xf000
#define csr_AcsmOdtCtrl3_RANGE  7:0
#define csr_AcsmOdtCtrl3_BITS   7:0
#define csr_AcsmOdtCtrl3_MSB  7
#define csr_AcsmOdtCtrl3_LSB  0
#define csr_AcsmOdtCtrl3_MASK 0xff
#define csr_AcsmOdtWrPatCs3_RANGE  3:0
#define csr_AcsmOdtWrPatCs3_BITS   3:0
#define csr_AcsmOdtWrPatCs3_MSB  3
#define csr_AcsmOdtWrPatCs3_LSB  0
#define csr_AcsmOdtWrPatCs3_MASK 0xf
#define csr_AcsmOdtRdPatCs3_RANGE  7:4
#define csr_AcsmOdtRdPatCs3_BITS   3:0
#define csr_AcsmOdtRdPatCs3_MSB  7
#define csr_AcsmOdtRdPatCs3_LSB  4
#define csr_AcsmOdtRdPatCs3_MASK 0xf0
#define csr_SequenceReg0b62s1_RANGE  15:0
#define csr_SequenceReg0b62s1_BITS   15:0
#define csr_SequenceReg0b62s1_MSB  15
#define csr_SequenceReg0b62s1_LSB  0
#define csr_SequenceReg0b62s1_MASK 0xffff
#define csr_DxLcdlStatus_RANGE  13:0
#define csr_DxLcdlStatus_BITS   13:0
#define csr_DxLcdlStatus_MSB  13
#define csr_DxLcdlStatus_LSB  0
#define csr_DxLcdlStatus_MASK 0x3fff
#define csr_DxLcdlFineSnapVal_RANGE  9:0
#define csr_DxLcdlFineSnapVal_BITS   9:0
#define csr_DxLcdlFineSnapVal_MSB  9
#define csr_DxLcdlFineSnapVal_LSB  0
#define csr_DxLcdlFineSnapVal_MASK 0x3ff
#define csr_DxLcdlPhdSnapVal_RANGE  10:10
#define csr_DxLcdlPhdSnapVal_BITS   0:0
#define csr_DxLcdlPhdSnapVal_MSB  10
#define csr_DxLcdlPhdSnapVal_LSB  10
#define csr_DxLcdlPhdSnapVal_MASK 0x400
#define csr_DxLcdlStickyLock_RANGE  11:11
#define csr_DxLcdlStickyLock_BITS   0:0
#define csr_DxLcdlStickyLock_MSB  11
#define csr_DxLcdlStickyLock_LSB  11
#define csr_DxLcdlStickyLock_MASK 0x800
#define csr_DxLcdlStickyUnlock_RANGE  12:12
#define csr_DxLcdlStickyUnlock_BITS   0:0
#define csr_DxLcdlStickyUnlock_MSB  12
#define csr_DxLcdlStickyUnlock_LSB  12
#define csr_DxLcdlStickyUnlock_MASK 0x1000
#define csr_DxLcdlLiveLock_RANGE  13:13
#define csr_DxLcdlLiveLock_BITS   0:0
#define csr_DxLcdlLiveLock_MSB  13
#define csr_DxLcdlLiveLock_LSB  13
#define csr_DxLcdlLiveLock_MASK 0x2000
#define csr_AcLcdlStatus_RANGE  13:0
#define csr_AcLcdlStatus_BITS   13:0
#define csr_AcLcdlStatus_MSB  13
#define csr_AcLcdlStatus_LSB  0
#define csr_AcLcdlStatus_MASK 0x3fff
#define csr_AcLcdlFineSnapVal_RANGE  9:0
#define csr_AcLcdlFineSnapVal_BITS   9:0
#define csr_AcLcdlFineSnapVal_MSB  9
#define csr_AcLcdlFineSnapVal_LSB  0
#define csr_AcLcdlFineSnapVal_MASK 0x3ff
#define csr_AcLcdlPhdSnapVal_RANGE  10:10
#define csr_AcLcdlPhdSnapVal_BITS   0:0
#define csr_AcLcdlPhdSnapVal_MSB  10
#define csr_AcLcdlPhdSnapVal_LSB  10
#define csr_AcLcdlPhdSnapVal_MASK 0x400
#define csr_AcLcdlStickyLock_RANGE  11:11
#define csr_AcLcdlStickyLock_BITS   0:0
#define csr_AcLcdlStickyLock_MSB  11
#define csr_AcLcdlStickyLock_LSB  11
#define csr_AcLcdlStickyLock_MASK 0x800
#define csr_AcLcdlStickyUnlock_RANGE  12:12
#define csr_AcLcdlStickyUnlock_BITS   0:0
#define csr_AcLcdlStickyUnlock_MSB  12
#define csr_AcLcdlStickyUnlock_LSB  12
#define csr_AcLcdlStickyUnlock_MASK 0x1000
#define csr_AcLcdlLiveLock_RANGE  13:13
#define csr_AcLcdlLiveLock_BITS   0:0
#define csr_AcLcdlLiveLock_MSB  13
#define csr_AcLcdlLiveLock_LSB  13
#define csr_AcLcdlLiveLock_MASK 0x2000
#define csr_AcsmOdtCtrl4_RANGE  7:0
#define csr_AcsmOdtCtrl4_BITS   7:0
#define csr_AcsmOdtCtrl4_MSB  7
#define csr_AcsmOdtCtrl4_LSB  0
#define csr_AcsmOdtCtrl4_MASK 0xff
#define csr_AcsmOdtWrPatCs4_RANGE  3:0
#define csr_AcsmOdtWrPatCs4_BITS   3:0
#define csr_AcsmOdtWrPatCs4_MSB  3
#define csr_AcsmOdtWrPatCs4_LSB  0
#define csr_AcsmOdtWrPatCs4_MASK 0xf
#define csr_AcsmOdtRdPatCs4_RANGE  7:4
#define csr_AcsmOdtRdPatCs4_BITS   3:0
#define csr_AcsmOdtRdPatCs4_MSB  7
#define csr_AcsmOdtRdPatCs4_LSB  4
#define csr_AcsmOdtRdPatCs4_MASK 0xf0
#define csr_SequenceReg0b62s2_RANGE  8:0
#define csr_SequenceReg0b62s2_BITS   8:0
#define csr_SequenceReg0b62s2_MSB  8
#define csr_SequenceReg0b62s2_LSB  0
#define csr_SequenceReg0b62s2_MASK 0x1ff
#define csr_AcsmOdtCtrl5_RANGE  7:0
#define csr_AcsmOdtCtrl5_BITS   7:0
#define csr_AcsmOdtCtrl5_MSB  7
#define csr_AcsmOdtCtrl5_LSB  0
#define csr_AcsmOdtCtrl5_MASK 0xff
#define csr_AcsmOdtWrPatCs5_RANGE  3:0
#define csr_AcsmOdtWrPatCs5_BITS   3:0
#define csr_AcsmOdtWrPatCs5_MSB  3
#define csr_AcsmOdtWrPatCs5_LSB  0
#define csr_AcsmOdtWrPatCs5_MASK 0xf
#define csr_AcsmOdtRdPatCs5_RANGE  7:4
#define csr_AcsmOdtRdPatCs5_BITS   3:0
#define csr_AcsmOdtRdPatCs5_MSB  7
#define csr_AcsmOdtRdPatCs5_LSB  4
#define csr_AcsmOdtRdPatCs5_MASK 0xf0
#define csr_SequenceReg0b63s0_RANGE  15:0
#define csr_SequenceReg0b63s0_BITS   15:0
#define csr_SequenceReg0b63s0_MSB  15
#define csr_SequenceReg0b63s0_LSB  0
#define csr_SequenceReg0b63s0_MASK 0xffff
#define csr_AcsmOdtCtrl6_RANGE  7:0
#define csr_AcsmOdtCtrl6_BITS   7:0
#define csr_AcsmOdtCtrl6_MSB  7
#define csr_AcsmOdtCtrl6_LSB  0
#define csr_AcsmOdtCtrl6_MASK 0xff
#define csr_AcsmOdtWrPatCs6_RANGE  3:0
#define csr_AcsmOdtWrPatCs6_BITS   3:0
#define csr_AcsmOdtWrPatCs6_MSB  3
#define csr_AcsmOdtWrPatCs6_LSB  0
#define csr_AcsmOdtWrPatCs6_MASK 0xf
#define csr_AcsmOdtRdPatCs6_RANGE  7:4
#define csr_AcsmOdtRdPatCs6_BITS   3:0
#define csr_AcsmOdtRdPatCs6_MSB  7
#define csr_AcsmOdtRdPatCs6_LSB  4
#define csr_AcsmOdtRdPatCs6_MASK 0xf0
#define csr_SequenceReg0b63s1_RANGE  15:0
#define csr_SequenceReg0b63s1_BITS   15:0
#define csr_SequenceReg0b63s1_MSB  15
#define csr_SequenceReg0b63s1_LSB  0
#define csr_SequenceReg0b63s1_MASK 0xffff
#define csr_SequencerOverride_RANGE  10:0
#define csr_SequencerOverride_BITS   10:0
#define csr_SequencerOverride_MSB  10
#define csr_SequencerOverride_LSB  0
#define csr_SequencerOverride_MASK 0x7ff
#define csr_ForceSeq0BDfiFreq_RANGE  4:0
#define csr_ForceSeq0BDfiFreq_BITS   4:0
#define csr_ForceSeq0BDfiFreq_MSB  4
#define csr_ForceSeq0BDfiFreq_LSB  0
#define csr_ForceSeq0BDfiFreq_MASK 0x1f
#define csr_ForceSeq0BStart_RANGE  5:5
#define csr_ForceSeq0BStart_BITS   0:0
#define csr_ForceSeq0BStart_MSB  5
#define csr_ForceSeq0BStart_LSB  5
#define csr_ForceSeq0BStart_MASK 0x20
#define csr_ForceSeq0BStop_RANGE  6:6
#define csr_ForceSeq0BStop_BITS   0:0
#define csr_ForceSeq0BStop_MSB  6
#define csr_ForceSeq0BStop_LSB  6
#define csr_ForceSeq0BStop_MASK 0x40
#define csr_BlockSeq0BRequests_RANGE  7:7
#define csr_BlockSeq0BRequests_BITS   0:0
#define csr_BlockSeq0BRequests_MSB  7
#define csr_BlockSeq0BRequests_LSB  7
#define csr_BlockSeq0BRequests_MASK 0x80
#define csr_BlockSeq0BAck_RANGE  8:8
#define csr_BlockSeq0BAck_BITS   0:0
#define csr_BlockSeq0BAck_MSB  8
#define csr_BlockSeq0BAck_LSB  8
#define csr_BlockSeq0BAck_MASK 0x100
#define csr_DisableTerminateFlag_RANGE  9:9
#define csr_DisableTerminateFlag_BITS   0:0
#define csr_DisableTerminateFlag_MSB  9
#define csr_DisableTerminateFlag_LSB  9
#define csr_DisableTerminateFlag_MASK 0x200
#define csr_SelectDFIFreqToGPRMux_RANGE  10:10
#define csr_SelectDFIFreqToGPRMux_BITS   0:0
#define csr_SelectDFIFreqToGPRMux_MSB  10
#define csr_SelectDFIFreqToGPRMux_LSB  10
#define csr_SelectDFIFreqToGPRMux_MASK 0x400
#define csr_AcsmOdtCtrl7_RANGE  7:0
#define csr_AcsmOdtCtrl7_BITS   7:0
#define csr_AcsmOdtCtrl7_MSB  7
#define csr_AcsmOdtCtrl7_LSB  0
#define csr_AcsmOdtCtrl7_MASK 0xff
#define csr_AcsmOdtWrPatCs7_RANGE  3:0
#define csr_AcsmOdtWrPatCs7_BITS   3:0
#define csr_AcsmOdtWrPatCs7_MSB  3
#define csr_AcsmOdtWrPatCs7_LSB  0
#define csr_AcsmOdtWrPatCs7_MASK 0xf
#define csr_AcsmOdtRdPatCs7_RANGE  7:4
#define csr_AcsmOdtRdPatCs7_BITS   3:0
#define csr_AcsmOdtRdPatCs7_MSB  7
#define csr_AcsmOdtRdPatCs7_LSB  4
#define csr_AcsmOdtRdPatCs7_MASK 0xf0
#define csr_SequenceReg0b63s2_RANGE  8:0
#define csr_SequenceReg0b63s2_BITS   8:0
#define csr_SequenceReg0b63s2_MSB  8
#define csr_SequenceReg0b63s2_LSB  0
#define csr_SequenceReg0b63s2_MASK 0x1ff
#define csr_AcsmOdtCtrl8_RANGE  15:0
#define csr_AcsmOdtCtrl8_BITS   15:0
#define csr_AcsmOdtCtrl8_MSB  15
#define csr_AcsmOdtCtrl8_LSB  0
#define csr_AcsmOdtCtrl8_MASK 0xffff
#define csr_AcsmOdtWrDurCtrl_RANGE  3:0
#define csr_AcsmOdtWrDurCtrl_BITS   3:0
#define csr_AcsmOdtWrDurCtrl_MSB  3
#define csr_AcsmOdtWrDurCtrl_LSB  0
#define csr_AcsmOdtWrDurCtrl_MASK 0xf
#define csr_AcsmOdtRdDurCtrl_RANGE  7:4
#define csr_AcsmOdtRdDurCtrl_BITS   3:0
#define csr_AcsmOdtRdDurCtrl_MSB  7
#define csr_AcsmOdtRdDurCtrl_LSB  4
#define csr_AcsmOdtRdDurCtrl_MASK 0xf0
#define csr_AcsmOdtWrStrtCtrl_RANGE  11:8
#define csr_AcsmOdtWrStrtCtrl_BITS   3:0
#define csr_AcsmOdtWrStrtCtrl_MSB  11
#define csr_AcsmOdtWrStrtCtrl_LSB  8
#define csr_AcsmOdtWrStrtCtrl_MASK 0xf00
#define csr_AcsmOdtRdStrtCtrl_RANGE  15:12
#define csr_AcsmOdtRdStrtCtrl_BITS   3:0
#define csr_AcsmOdtRdStrtCtrl_MSB  15
#define csr_AcsmOdtRdStrtCtrl_LSB  12
#define csr_AcsmOdtRdStrtCtrl_MASK 0xf000
#define csr_SequenceReg0b64s0_RANGE  15:0
#define csr_SequenceReg0b64s0_BITS   15:0
#define csr_SequenceReg0b64s0_MSB  15
#define csr_SequenceReg0b64s0_LSB  0
#define csr_SequenceReg0b64s0_MASK 0xffff
#define csr_AcsmCtrl16_RANGE  15:0
#define csr_AcsmCtrl16_BITS   15:0
#define csr_AcsmCtrl16_MSB  15
#define csr_AcsmCtrl16_LSB  0
#define csr_AcsmCtrl16_MASK 0xffff
#define csr_AcsmDdrAdrUp_RANGE  3:0
#define csr_AcsmDdrAdrUp_BITS   3:0
#define csr_AcsmDdrAdrUp_MSB  3
#define csr_AcsmDdrAdrUp_LSB  0
#define csr_AcsmDdrAdrUp_MASK 0xf
#define csr_AcsmHighAddr_RANGE  4:4
#define csr_AcsmHighAddr_BITS   0:0
#define csr_AcsmHighAddr_MSB  4
#define csr_AcsmHighAddr_LSB  4
#define csr_AcsmHighAddr_MASK 0x10
#define csr_AcsmAdr13PlugHole_RANGE  5:5
#define csr_AcsmAdr13PlugHole_BITS   0:0
#define csr_AcsmAdr13PlugHole_MSB  5
#define csr_AcsmAdr13PlugHole_LSB  5
#define csr_AcsmAdr13PlugHole_MASK 0x20
#define csr_AcsmCtrl16Rsvd_RANGE  6:6
#define csr_AcsmCtrl16Rsvd_BITS   0:0
#define csr_AcsmCtrl16Rsvd_MSB  6
#define csr_AcsmCtrl16Rsvd_LSB  6
#define csr_AcsmCtrl16Rsvd_MASK 0x40
#define csr_AcsmWrtLvlOdtCtrl_RANGE  7:7
#define csr_AcsmWrtLvlOdtCtrl_BITS   0:0
#define csr_AcsmWrtLvlOdtCtrl_MSB  7
#define csr_AcsmWrtLvlOdtCtrl_LSB  7
#define csr_AcsmWrtLvlOdtCtrl_MASK 0x80
#define csr_AcsmWrtLvlOdt_RANGE  11:8
#define csr_AcsmWrtLvlOdt_BITS   3:0
#define csr_AcsmWrtLvlOdt_MSB  11
#define csr_AcsmWrtLvlOdt_LSB  8
#define csr_AcsmWrtLvlOdt_MASK 0xf00
#define csr_Acsm2TGrpInhibit_RANGE  15:12
#define csr_Acsm2TGrpInhibit_BITS   3:0
#define csr_Acsm2TGrpInhibit_MSB  15
#define csr_Acsm2TGrpInhibit_LSB  12
#define csr_Acsm2TGrpInhibit_MASK 0xf000
#define csr_SequenceReg0b64s1_RANGE  15:0
#define csr_SequenceReg0b64s1_BITS   15:0
#define csr_SequenceReg0b64s1_MSB  15
#define csr_SequenceReg0b64s1_LSB  0
#define csr_SequenceReg0b64s1_MASK 0xffff
#define csr_LowSpeedClockStopVal_RANGE  0:0
#define csr_LowSpeedClockStopVal_BITS   0:0
#define csr_LowSpeedClockStopVal_MSB  0
#define csr_LowSpeedClockStopVal_LSB  0
#define csr_LowSpeedClockStopVal_MASK 0x1
#define csr_SequenceReg0b64s2_RANGE  8:0
#define csr_SequenceReg0b64s2_BITS   8:0
#define csr_SequenceReg0b64s2_MSB  8
#define csr_SequenceReg0b64s2_LSB  0
#define csr_SequenceReg0b64s2_MASK 0x1ff
#define csr_AcsmCtrl18_RANGE  1:0
#define csr_AcsmCtrl18_BITS   1:0
#define csr_AcsmCtrl18_MSB  1
#define csr_AcsmCtrl18_LSB  0
#define csr_AcsmCtrl18_MASK 0x3
#define csr_AcsmLocalDone_RANGE  0:0
#define csr_AcsmLocalDone_BITS   0:0
#define csr_AcsmLocalDone_MSB  0
#define csr_AcsmLocalDone_LSB  0
#define csr_AcsmLocalDone_MASK 0x1
#define csr_AcsmStopOnErrAsrtd_RANGE  1:1
#define csr_AcsmStopOnErrAsrtd_BITS   0:0
#define csr_AcsmStopOnErrAsrtd_MSB  1
#define csr_AcsmStopOnErrAsrtd_LSB  1
#define csr_AcsmStopOnErrAsrtd_MASK 0x2
#define csr_SequenceReg0b65s0_RANGE  15:0
#define csr_SequenceReg0b65s0_BITS   15:0
#define csr_SequenceReg0b65s0_MSB  15
#define csr_SequenceReg0b65s0_LSB  0
#define csr_SequenceReg0b65s0_MASK 0xffff
#define csr_AcsmCtrl19_RANGE  2:0
#define csr_AcsmCtrl19_BITS   2:0
#define csr_AcsmCtrl19_MSB  2
#define csr_AcsmCtrl19_LSB  0
#define csr_AcsmCtrl19_MASK 0x7
#define csr_AcsmVisSel_RANGE  2:0
#define csr_AcsmVisSel_BITS   2:0
#define csr_AcsmVisSel_MSB  2
#define csr_AcsmVisSel_LSB  0
#define csr_AcsmVisSel_MASK 0x7
#define csr_SequenceReg0b65s1_RANGE  15:0
#define csr_SequenceReg0b65s1_BITS   15:0
#define csr_SequenceReg0b65s1_MSB  15
#define csr_SequenceReg0b65s1_LSB  0
#define csr_SequenceReg0b65s1_MASK 0xffff
#define csr_AcsmCtrl20_RANGE  15:0
#define csr_AcsmCtrl20_BITS   15:0
#define csr_AcsmCtrl20_MSB  15
#define csr_AcsmCtrl20_LSB  0
#define csr_AcsmCtrl20_MASK 0xffff
#define csr_AcsmVisVal_RANGE  15:0
#define csr_AcsmVisVal_BITS   15:0
#define csr_AcsmVisVal_MSB  15
#define csr_AcsmVisVal_LSB  0
#define csr_AcsmVisVal_MASK 0xffff
#define csr_CUSTPUBREV_RANGE  5:0
#define csr_CUSTPUBREV_BITS   5:0
#define csr_CUSTPUBREV_MSB  5
#define csr_CUSTPUBREV_LSB  0
#define csr_CUSTPUBREV_MASK 0x3f
#define csr_CUSTPHYREV_RANGE  5:0
#define csr_CUSTPHYREV_BITS   5:0
#define csr_CUSTPHYREV_MSB  5
#define csr_CUSTPHYREV_LSB  0
#define csr_CUSTPHYREV_MASK 0x3f
#define csr_SequenceReg0b65s2_RANGE  8:0
#define csr_SequenceReg0b65s2_BITS   8:0
#define csr_SequenceReg0b65s2_MSB  8
#define csr_SequenceReg0b65s2_LSB  0
#define csr_SequenceReg0b65s2_MASK 0x1ff
#define csr_AcsmCtrl21_RANGE  11:0
#define csr_AcsmCtrl21_BITS   11:0
#define csr_AcsmCtrl21_MSB  11
#define csr_AcsmCtrl21_LSB  0
#define csr_AcsmCtrl21_MASK 0xfff
#define csr_AcsmMapDimmCs0_RANGE  2:0
#define csr_AcsmMapDimmCs0_BITS   2:0
#define csr_AcsmMapDimmCs0_MSB  2
#define csr_AcsmMapDimmCs0_LSB  0
#define csr_AcsmMapDimmCs0_MASK 0x7
#define csr_AcsmMapDimmCs1_RANGE  5:3
#define csr_AcsmMapDimmCs1_BITS   2:0
#define csr_AcsmMapDimmCs1_MSB  5
#define csr_AcsmMapDimmCs1_LSB  3
#define csr_AcsmMapDimmCs1_MASK 0x38
#define csr_AcsmMapDimmCs2_RANGE  8:6
#define csr_AcsmMapDimmCs2_BITS   2:0
#define csr_AcsmMapDimmCs2_MSB  8
#define csr_AcsmMapDimmCs2_LSB  6
#define csr_AcsmMapDimmCs2_MASK 0x1c0
#define csr_AcsmMapDimmCs3_RANGE  11:9
#define csr_AcsmMapDimmCs3_BITS   2:0
#define csr_AcsmMapDimmCs3_MSB  11
#define csr_AcsmMapDimmCs3_LSB  9
#define csr_AcsmMapDimmCs3_MASK 0xe00
#define csr_PUBREV_RANGE  15:0
#define csr_PUBREV_BITS   15:0
#define csr_PUBREV_MSB  15
#define csr_PUBREV_LSB  0
#define csr_PUBREV_MASK 0xffff
#define csr_ReservedPubrev_RANGE  3:0
#define csr_ReservedPubrev_BITS   3:0
#define csr_ReservedPubrev_MSB  3
#define csr_ReservedPubrev_LSB  0
#define csr_ReservedPubrev_MASK 0xf
#define csr_PUBMNR_RANGE  7:4
#define csr_PUBMNR_BITS   3:0
#define csr_PUBMNR_MSB  7
#define csr_PUBMNR_LSB  4
#define csr_PUBMNR_MASK 0xf0
#define csr_PUBMDR_RANGE  11:8
#define csr_PUBMDR_BITS   3:0
#define csr_PUBMDR_MSB  11
#define csr_PUBMDR_LSB  8
#define csr_PUBMDR_MASK 0xf00
#define csr_PUBMJR_RANGE  15:12
#define csr_PUBMJR_BITS   3:0
#define csr_PUBMJR_MSB  15
#define csr_PUBMJR_LSB  12
#define csr_PUBMJR_MASK 0xf000
#define csr_PHYREV_RANGE  15:0
#define csr_PHYREV_BITS   15:0
#define csr_PHYREV_MSB  15
#define csr_PHYREV_LSB  0
#define csr_PHYREV_MASK 0xffff
#define csr_PHYMNR_RANGE  3:0
#define csr_PHYMNR_BITS   3:0
#define csr_PHYMNR_MSB  3
#define csr_PHYMNR_LSB  0
#define csr_PHYMNR_MASK 0xf
#define csr_PHYMDR_RANGE  7:4
#define csr_PHYMDR_BITS   3:0
#define csr_PHYMDR_MSB  7
#define csr_PHYMDR_LSB  4
#define csr_PHYMDR_MASK 0xf0
#define csr_PHYMJR_RANGE  15:8
#define csr_PHYMJR_BITS   7:0
#define csr_PHYMJR_MSB  15
#define csr_PHYMJR_LSB  8
#define csr_PHYMJR_MASK 0xff00
#define csr_SequenceReg0b66s0_RANGE  15:0
#define csr_SequenceReg0b66s0_BITS   15:0
#define csr_SequenceReg0b66s0_MSB  15
#define csr_SequenceReg0b66s0_LSB  0
#define csr_SequenceReg0b66s0_MASK 0xffff
#define csr_LP3ExitSeq0BStartVector_RANGE  7:0
#define csr_LP3ExitSeq0BStartVector_BITS   7:0
#define csr_LP3ExitSeq0BStartVector_MSB  7
#define csr_LP3ExitSeq0BStartVector_LSB  0
#define csr_LP3ExitSeq0BStartVector_MASK 0xff
#define csr_LP3ExitSeq0BStartVecPllEnabled_RANGE  3:0
#define csr_LP3ExitSeq0BStartVecPllEnabled_BITS   3:0
#define csr_LP3ExitSeq0BStartVecPllEnabled_MSB  3
#define csr_LP3ExitSeq0BStartVecPllEnabled_LSB  0
#define csr_LP3ExitSeq0BStartVecPllEnabled_MASK 0xf
#define csr_LP3ExitSeq0BStartVecPllBypassed_RANGE  7:4
#define csr_LP3ExitSeq0BStartVecPllBypassed_BITS   3:0
#define csr_LP3ExitSeq0BStartVecPllBypassed_MSB  7
#define csr_LP3ExitSeq0BStartVecPllBypassed_LSB  4
#define csr_LP3ExitSeq0BStartVecPllBypassed_MASK 0xf0
#define csr_AcsmCtrl22_RANGE  11:0
#define csr_AcsmCtrl22_BITS   11:0
#define csr_AcsmCtrl22_MSB  11
#define csr_AcsmCtrl22_LSB  0
#define csr_AcsmCtrl22_MASK 0xfff
#define csr_AcsmMapDimmCs4_RANGE  2:0
#define csr_AcsmMapDimmCs4_BITS   2:0
#define csr_AcsmMapDimmCs4_MSB  2
#define csr_AcsmMapDimmCs4_LSB  0
#define csr_AcsmMapDimmCs4_MASK 0x7
#define csr_AcsmMapDimmCs5_RANGE  5:3
#define csr_AcsmMapDimmCs5_BITS   2:0
#define csr_AcsmMapDimmCs5_MSB  5
#define csr_AcsmMapDimmCs5_LSB  3
#define csr_AcsmMapDimmCs5_MASK 0x38
#define csr_AcsmMapDimmCs6_RANGE  8:6
#define csr_AcsmMapDimmCs6_BITS   2:0
#define csr_AcsmMapDimmCs6_MSB  8
#define csr_AcsmMapDimmCs6_LSB  6
#define csr_AcsmMapDimmCs6_MASK 0x1c0
#define csr_AcsmMapDimmCs7_RANGE  11:9
#define csr_AcsmMapDimmCs7_BITS   2:0
#define csr_AcsmMapDimmCs7_MSB  11
#define csr_AcsmMapDimmCs7_LSB  9
#define csr_AcsmMapDimmCs7_MASK 0xe00
#define csr_SequenceReg0b66s1_RANGE  15:0
#define csr_SequenceReg0b66s1_BITS   15:0
#define csr_SequenceReg0b66s1_MSB  15
#define csr_SequenceReg0b66s1_LSB  0
#define csr_SequenceReg0b66s1_MASK 0xffff
#define csr_DfiFreqXlat0_RANGE  15:0
#define csr_DfiFreqXlat0_BITS   15:0
#define csr_DfiFreqXlat0_MSB  15
#define csr_DfiFreqXlat0_LSB  0
#define csr_DfiFreqXlat0_MASK 0xffff
#define csr_DfiFreqXlatVal0_RANGE  3:0
#define csr_DfiFreqXlatVal0_BITS   3:0
#define csr_DfiFreqXlatVal0_MSB  3
#define csr_DfiFreqXlatVal0_LSB  0
#define csr_DfiFreqXlatVal0_MASK 0xf
#define csr_DfiFreqXlatVal1_RANGE  7:4
#define csr_DfiFreqXlatVal1_BITS   3:0
#define csr_DfiFreqXlatVal1_MSB  7
#define csr_DfiFreqXlatVal1_LSB  4
#define csr_DfiFreqXlatVal1_MASK 0xf0
#define csr_DfiFreqXlatVal2_RANGE  11:8
#define csr_DfiFreqXlatVal2_BITS   3:0
#define csr_DfiFreqXlatVal2_MSB  11
#define csr_DfiFreqXlatVal2_LSB  8
#define csr_DfiFreqXlatVal2_MASK 0xf00
#define csr_DfiFreqXlatVal3_RANGE  15:12
#define csr_DfiFreqXlatVal3_BITS   3:0
#define csr_DfiFreqXlatVal3_MSB  15
#define csr_DfiFreqXlatVal3_LSB  12
#define csr_DfiFreqXlatVal3_MASK 0xf000
#define csr_AcsmCtrl0_RANGE  15:0
#define csr_AcsmCtrl0_BITS   15:0
#define csr_AcsmCtrl0_MSB  15
#define csr_AcsmCtrl0_LSB  0
#define csr_AcsmCtrl0_MASK 0xffff
#define csr_AcsmRsvdCtrl00_RANGE  0:0
#define csr_AcsmRsvdCtrl00_BITS   0:0
#define csr_AcsmRsvdCtrl00_MSB  0
#define csr_AcsmRsvdCtrl00_LSB  0
#define csr_AcsmRsvdCtrl00_MASK 0x1
#define csr_AcsmDynBLMode_RANGE  1:1
#define csr_AcsmDynBLMode_BITS   0:0
#define csr_AcsmDynBLMode_MSB  1
#define csr_AcsmDynBLMode_LSB  1
#define csr_AcsmDynBLMode_MASK 0x2
#define csr_AcsmBurstLen_RANGE  2:2
#define csr_AcsmBurstLen_BITS   0:0
#define csr_AcsmBurstLen_MSB  2
#define csr_AcsmBurstLen_LSB  2
#define csr_AcsmBurstLen_MASK 0x4
#define csr_AcsmInfLoop_RANGE  3:3
#define csr_AcsmInfLoop_BITS   0:0
#define csr_AcsmInfLoop_MSB  3
#define csr_AcsmInfLoop_LSB  3
#define csr_AcsmInfLoop_MASK 0x8
#define csr_AcsmRxvalMode_RANGE  4:4
#define csr_AcsmRxvalMode_BITS   0:0
#define csr_AcsmRxvalMode_MSB  4
#define csr_AcsmRxvalMode_LSB  4
#define csr_AcsmRxvalMode_MASK 0x10
#define csr_AcsmStpOnErrMode_RANGE  5:5
#define csr_AcsmStpOnErrMode_BITS   0:0
#define csr_AcsmStpOnErrMode_MSB  5
#define csr_AcsmStpOnErrMode_LSB  5
#define csr_AcsmStpOnErrMode_MASK 0x20
#define csr_Acsm2TMode_RANGE  6:6
#define csr_Acsm2TMode_BITS   0:0
#define csr_Acsm2TMode_MSB  6
#define csr_Acsm2TMode_LSB  6
#define csr_Acsm2TMode_MASK 0x40
#define csr_AcsmTrainSOEMode_RANGE  7:7
#define csr_AcsmTrainSOEMode_BITS   0:0
#define csr_AcsmTrainSOEMode_MSB  7
#define csr_AcsmTrainSOEMode_LSB  7
#define csr_AcsmTrainSOEMode_MASK 0x80
#define csr_AcsmGateDdrCmd_RANGE  8:8
#define csr_AcsmGateDdrCmd_BITS   0:0
#define csr_AcsmGateDdrCmd_MSB  8
#define csr_AcsmGateDdrCmd_LSB  8
#define csr_AcsmGateDdrCmd_MASK 0x100
#define csr_AcsmGeardownMode_RANGE  9:9
#define csr_AcsmGeardownMode_BITS   0:0
#define csr_AcsmGeardownMode_MSB  9
#define csr_AcsmGeardownMode_LSB  9
#define csr_AcsmGeardownMode_MASK 0x200
#define csr_AcsmGeardownPhase_RANGE  10:10
#define csr_AcsmGeardownPhase_BITS   0:0
#define csr_AcsmGeardownPhase_MSB  10
#define csr_AcsmGeardownPhase_LSB  10
#define csr_AcsmGeardownPhase_MASK 0x400
#define csr_AcsmGeardownSync_RANGE  11:11
#define csr_AcsmGeardownSync_BITS   0:0
#define csr_AcsmGeardownSync_MSB  11
#define csr_AcsmGeardownSync_LSB  11
#define csr_AcsmGeardownSync_MASK 0x800
#define csr_AcsmCaPrbsMode_RANGE  12:12
#define csr_AcsmCaPrbsMode_BITS   0:0
#define csr_AcsmCaPrbsMode_MSB  12
#define csr_AcsmCaPrbsMode_LSB  12
#define csr_AcsmCaPrbsMode_MASK 0x1000
#define csr_AcsmGateRxFifoWrite_RANGE  13:13
#define csr_AcsmGateRxFifoWrite_BITS   0:0
#define csr_AcsmGateRxFifoWrite_MSB  13
#define csr_AcsmGateRxFifoWrite_LSB  13
#define csr_AcsmGateRxFifoWrite_MASK 0x2000
#define csr_AcsmParMode_RANGE  14:14
#define csr_AcsmParMode_BITS   0:0
#define csr_AcsmParMode_MSB  14
#define csr_AcsmParMode_LSB  14
#define csr_AcsmParMode_MASK 0x4000
#define csr_AcsmTdsMode_RANGE  15:15
#define csr_AcsmTdsMode_BITS   0:0
#define csr_AcsmTdsMode_MSB  15
#define csr_AcsmTdsMode_LSB  15
#define csr_AcsmTdsMode_MASK 0x8000
#define csr_SequenceReg0b66s2_RANGE  8:0
#define csr_SequenceReg0b66s2_BITS   8:0
#define csr_SequenceReg0b66s2_MSB  8
#define csr_SequenceReg0b66s2_LSB  0
#define csr_SequenceReg0b66s2_MASK 0x1ff
#define csr_DfiFreqXlat1_RANGE  15:0
#define csr_DfiFreqXlat1_BITS   15:0
#define csr_DfiFreqXlat1_MSB  15
#define csr_DfiFreqXlat1_LSB  0
#define csr_DfiFreqXlat1_MASK 0xffff
#define csr_DfiFreqXlatVal4_RANGE  3:0
#define csr_DfiFreqXlatVal4_BITS   3:0
#define csr_DfiFreqXlatVal4_MSB  3
#define csr_DfiFreqXlatVal4_LSB  0
#define csr_DfiFreqXlatVal4_MASK 0xf
#define csr_DfiFreqXlatVal5_RANGE  7:4
#define csr_DfiFreqXlatVal5_BITS   3:0
#define csr_DfiFreqXlatVal5_MSB  7
#define csr_DfiFreqXlatVal5_LSB  4
#define csr_DfiFreqXlatVal5_MASK 0xf0
#define csr_DfiFreqXlatVal6_RANGE  11:8
#define csr_DfiFreqXlatVal6_BITS   3:0
#define csr_DfiFreqXlatVal6_MSB  11
#define csr_DfiFreqXlatVal6_LSB  8
#define csr_DfiFreqXlatVal6_MASK 0xf00
#define csr_DfiFreqXlatVal7_RANGE  15:12
#define csr_DfiFreqXlatVal7_BITS   3:0
#define csr_DfiFreqXlatVal7_MSB  15
#define csr_DfiFreqXlatVal7_LSB  12
#define csr_DfiFreqXlatVal7_MASK 0xf000
#define csr_AcsmCtrl1_RANGE  15:0
#define csr_AcsmCtrl1_BITS   15:0
#define csr_AcsmCtrl1_MSB  15
#define csr_AcsmCtrl1_LSB  0
#define csr_AcsmCtrl1_MASK 0xffff
#define csr_AcsmRepCnt_RANGE  15:0
#define csr_AcsmRepCnt_BITS   15:0
#define csr_AcsmRepCnt_MSB  15
#define csr_AcsmRepCnt_LSB  0
#define csr_AcsmRepCnt_MASK 0xffff
#define csr_SequenceReg0b67s0_RANGE  15:0
#define csr_SequenceReg0b67s0_BITS   15:0
#define csr_SequenceReg0b67s0_MSB  15
#define csr_SequenceReg0b67s0_LSB  0
#define csr_SequenceReg0b67s0_MASK 0xffff
#define csr_DfiFreqXlat2_RANGE  15:0
#define csr_DfiFreqXlat2_BITS   15:0
#define csr_DfiFreqXlat2_MSB  15
#define csr_DfiFreqXlat2_LSB  0
#define csr_DfiFreqXlat2_MASK 0xffff
#define csr_DfiFreqXlatVal8_RANGE  3:0
#define csr_DfiFreqXlatVal8_BITS   3:0
#define csr_DfiFreqXlatVal8_MSB  3
#define csr_DfiFreqXlatVal8_LSB  0
#define csr_DfiFreqXlatVal8_MASK 0xf
#define csr_DfiFreqXlatVal9_RANGE  7:4
#define csr_DfiFreqXlatVal9_BITS   3:0
#define csr_DfiFreqXlatVal9_MSB  7
#define csr_DfiFreqXlatVal9_LSB  4
#define csr_DfiFreqXlatVal9_MASK 0xf0
#define csr_DfiFreqXlatVal10_RANGE  11:8
#define csr_DfiFreqXlatVal10_BITS   3:0
#define csr_DfiFreqXlatVal10_MSB  11
#define csr_DfiFreqXlatVal10_LSB  8
#define csr_DfiFreqXlatVal10_MASK 0xf00
#define csr_DfiFreqXlatVal11_RANGE  15:12
#define csr_DfiFreqXlatVal11_BITS   3:0
#define csr_DfiFreqXlatVal11_MSB  15
#define csr_DfiFreqXlatVal11_LSB  12
#define csr_DfiFreqXlatVal11_MASK 0xf000
#define csr_AcsmCtrl2_RANGE  4:0
#define csr_AcsmCtrl2_BITS   4:0
#define csr_AcsmCtrl2_MSB  4
#define csr_AcsmCtrl2_LSB  0
#define csr_AcsmCtrl2_MASK 0x1f
#define csr_AcsmStartPtr_RANGE  4:0
#define csr_AcsmStartPtr_BITS   4:0
#define csr_AcsmStartPtr_MSB  4
#define csr_AcsmStartPtr_LSB  0
#define csr_AcsmStartPtr_MASK 0x1f
#define csr_SequenceReg0b67s1_RANGE  15:0
#define csr_SequenceReg0b67s1_BITS   15:0
#define csr_SequenceReg0b67s1_MSB  15
#define csr_SequenceReg0b67s1_LSB  0
#define csr_SequenceReg0b67s1_MASK 0xffff
#define csr_DfiFreqXlat3_RANGE  15:0
#define csr_DfiFreqXlat3_BITS   15:0
#define csr_DfiFreqXlat3_MSB  15
#define csr_DfiFreqXlat3_LSB  0
#define csr_DfiFreqXlat3_MASK 0xffff
#define csr_DfiFreqXlatVal12_RANGE  3:0
#define csr_DfiFreqXlatVal12_BITS   3:0
#define csr_DfiFreqXlatVal12_MSB  3
#define csr_DfiFreqXlatVal12_LSB  0
#define csr_DfiFreqXlatVal12_MASK 0xf
#define csr_DfiFreqXlatVal13_RANGE  7:4
#define csr_DfiFreqXlatVal13_BITS   3:0
#define csr_DfiFreqXlatVal13_MSB  7
#define csr_DfiFreqXlatVal13_LSB  4
#define csr_DfiFreqXlatVal13_MASK 0xf0
#define csr_DfiFreqXlatVal14_RANGE  11:8
#define csr_DfiFreqXlatVal14_BITS   3:0
#define csr_DfiFreqXlatVal14_MSB  11
#define csr_DfiFreqXlatVal14_LSB  8
#define csr_DfiFreqXlatVal14_MASK 0xf00
#define csr_DfiFreqXlatVal15_RANGE  15:12
#define csr_DfiFreqXlatVal15_BITS   3:0
#define csr_DfiFreqXlatVal15_MSB  15
#define csr_DfiFreqXlatVal15_LSB  12
#define csr_DfiFreqXlatVal15_MASK 0xf000
#define csr_AcsmCtrl3_RANGE  4:0
#define csr_AcsmCtrl3_BITS   4:0
#define csr_AcsmCtrl3_MSB  4
#define csr_AcsmCtrl3_LSB  0
#define csr_AcsmCtrl3_MASK 0x1f
#define csr_AcsmLoopPtr_RANGE  4:0
#define csr_AcsmLoopPtr_BITS   4:0
#define csr_AcsmLoopPtr_MSB  4
#define csr_AcsmLoopPtr_LSB  0
#define csr_AcsmLoopPtr_MASK 0x1f
#define csr_SequenceReg0b67s2_RANGE  8:0
#define csr_SequenceReg0b67s2_BITS   8:0
#define csr_SequenceReg0b67s2_MSB  8
#define csr_SequenceReg0b67s2_LSB  0
#define csr_SequenceReg0b67s2_MASK 0x1ff
#define csr_DfiFreqXlat4_RANGE  15:0
#define csr_DfiFreqXlat4_BITS   15:0
#define csr_DfiFreqXlat4_MSB  15
#define csr_DfiFreqXlat4_LSB  0
#define csr_DfiFreqXlat4_MASK 0xffff
#define csr_DfiFreqXlatVal16_RANGE  3:0
#define csr_DfiFreqXlatVal16_BITS   3:0
#define csr_DfiFreqXlatVal16_MSB  3
#define csr_DfiFreqXlatVal16_LSB  0
#define csr_DfiFreqXlatVal16_MASK 0xf
#define csr_DfiFreqXlatVal17_RANGE  7:4
#define csr_DfiFreqXlatVal17_BITS   3:0
#define csr_DfiFreqXlatVal17_MSB  7
#define csr_DfiFreqXlatVal17_LSB  4
#define csr_DfiFreqXlatVal17_MASK 0xf0
#define csr_DfiFreqXlatVal18_RANGE  11:8
#define csr_DfiFreqXlatVal18_BITS   3:0
#define csr_DfiFreqXlatVal18_MSB  11
#define csr_DfiFreqXlatVal18_LSB  8
#define csr_DfiFreqXlatVal18_MASK 0xf00
#define csr_DfiFreqXlatVal19_RANGE  15:12
#define csr_DfiFreqXlatVal19_BITS   3:0
#define csr_DfiFreqXlatVal19_MSB  15
#define csr_DfiFreqXlatVal19_LSB  12
#define csr_DfiFreqXlatVal19_MASK 0xf000
#define csr_AcsmCtrl4_RANGE  4:0
#define csr_AcsmCtrl4_BITS   4:0
#define csr_AcsmCtrl4_MSB  4
#define csr_AcsmCtrl4_LSB  0
#define csr_AcsmCtrl4_MASK 0x1f
#define csr_AcsmEndPtr_RANGE  4:0
#define csr_AcsmEndPtr_BITS   4:0
#define csr_AcsmEndPtr_MSB  4
#define csr_AcsmEndPtr_LSB  0
#define csr_AcsmEndPtr_MASK 0x1f
#define csr_SequenceReg0b68s0_RANGE  15:0
#define csr_SequenceReg0b68s0_BITS   15:0
#define csr_SequenceReg0b68s0_MSB  15
#define csr_SequenceReg0b68s0_LSB  0
#define csr_SequenceReg0b68s0_MASK 0xffff
#define csr_DfiFreqXlat5_RANGE  15:0
#define csr_DfiFreqXlat5_BITS   15:0
#define csr_DfiFreqXlat5_MSB  15
#define csr_DfiFreqXlat5_LSB  0
#define csr_DfiFreqXlat5_MASK 0xffff
#define csr_DfiFreqXlatVal20_RANGE  3:0
#define csr_DfiFreqXlatVal20_BITS   3:0
#define csr_DfiFreqXlatVal20_MSB  3
#define csr_DfiFreqXlatVal20_LSB  0
#define csr_DfiFreqXlatVal20_MASK 0xf
#define csr_DfiFreqXlatVal21_RANGE  7:4
#define csr_DfiFreqXlatVal21_BITS   3:0
#define csr_DfiFreqXlatVal21_MSB  7
#define csr_DfiFreqXlatVal21_LSB  4
#define csr_DfiFreqXlatVal21_MASK 0xf0
#define csr_DfiFreqXlatVal22_RANGE  11:8
#define csr_DfiFreqXlatVal22_BITS   3:0
#define csr_DfiFreqXlatVal22_MSB  11
#define csr_DfiFreqXlatVal22_LSB  8
#define csr_DfiFreqXlatVal22_MASK 0xf00
#define csr_DfiFreqXlatVal23_RANGE  15:12
#define csr_DfiFreqXlatVal23_BITS   3:0
#define csr_DfiFreqXlatVal23_MSB  15
#define csr_DfiFreqXlatVal23_LSB  12
#define csr_DfiFreqXlatVal23_MASK 0xf000
#define csr_AcsmCtrl5_RANGE  13:0
#define csr_AcsmCtrl5_BITS   13:0
#define csr_AcsmCtrl5_MSB  13
#define csr_AcsmCtrl5_LSB  0
#define csr_AcsmCtrl5_MASK 0x3fff
#define csr_AcsmMxRdLat_RANGE  7:0
#define csr_AcsmMxRdLat_BITS   7:0
#define csr_AcsmMxRdLat_MSB  7
#define csr_AcsmMxRdLat_LSB  0
#define csr_AcsmMxRdLat_MASK 0xff
#define csr_AcsmRCasLat_RANGE  13:8
#define csr_AcsmRCasLat_BITS   5:0
#define csr_AcsmRCasLat_MSB  13
#define csr_AcsmRCasLat_LSB  8
#define csr_AcsmRCasLat_MASK 0x3f00
#define csr_SequenceReg0b68s1_RANGE  15:0
#define csr_SequenceReg0b68s1_BITS   15:0
#define csr_SequenceReg0b68s1_MSB  15
#define csr_SequenceReg0b68s1_LSB  0
#define csr_SequenceReg0b68s1_MASK 0xffff
#define csr_DfiFreqXlat6_RANGE  15:0
#define csr_DfiFreqXlat6_BITS   15:0
#define csr_DfiFreqXlat6_MSB  15
#define csr_DfiFreqXlat6_LSB  0
#define csr_DfiFreqXlat6_MASK 0xffff
#define csr_DfiFreqXlatVal24_RANGE  3:0
#define csr_DfiFreqXlatVal24_BITS   3:0
#define csr_DfiFreqXlatVal24_MSB  3
#define csr_DfiFreqXlatVal24_LSB  0
#define csr_DfiFreqXlatVal24_MASK 0xf
#define csr_DfiFreqXlatVal25_RANGE  7:4
#define csr_DfiFreqXlatVal25_BITS   3:0
#define csr_DfiFreqXlatVal25_MSB  7
#define csr_DfiFreqXlatVal25_LSB  4
#define csr_DfiFreqXlatVal25_MASK 0xf0
#define csr_DfiFreqXlatVal26_RANGE  11:8
#define csr_DfiFreqXlatVal26_BITS   3:0
#define csr_DfiFreqXlatVal26_MSB  11
#define csr_DfiFreqXlatVal26_LSB  8
#define csr_DfiFreqXlatVal26_MASK 0xf00
#define csr_DfiFreqXlatVal27_RANGE  15:12
#define csr_DfiFreqXlatVal27_BITS   3:0
#define csr_DfiFreqXlatVal27_MSB  15
#define csr_DfiFreqXlatVal27_LSB  12
#define csr_DfiFreqXlatVal27_MASK 0xf000
#define csr_AcsmCtrl6_RANGE  10:0
#define csr_AcsmCtrl6_BITS   10:0
#define csr_AcsmCtrl6_MSB  10
#define csr_AcsmCtrl6_LSB  0
#define csr_AcsmCtrl6_MASK 0x7ff
#define csr_AcsmWCasLat_RANGE  5:0
#define csr_AcsmWCasLat_BITS   5:0
#define csr_AcsmWCasLat_MSB  5
#define csr_AcsmWCasLat_LSB  0
#define csr_AcsmWCasLat_MASK 0x3f
#define csr_AcsmWrRsvd_RANGE  7:6
#define csr_AcsmWrRsvd_BITS   1:0
#define csr_AcsmWrRsvd_MSB  7
#define csr_AcsmWrRsvd_LSB  6
#define csr_AcsmWrRsvd_MASK 0xc0
#define csr_AcsmWrDatLat_RANGE  10:8
#define csr_AcsmWrDatLat_BITS   2:0
#define csr_AcsmWrDatLat_MSB  10
#define csr_AcsmWrDatLat_LSB  8
#define csr_AcsmWrDatLat_MASK 0x700
#define csr_SequenceReg0b68s2_RANGE  8:0
#define csr_SequenceReg0b68s2_BITS   8:0
#define csr_SequenceReg0b68s2_MSB  8
#define csr_SequenceReg0b68s2_LSB  0
#define csr_SequenceReg0b68s2_MASK 0x1ff
#define csr_DfiFreqXlat7_RANGE  15:0
#define csr_DfiFreqXlat7_BITS   15:0
#define csr_DfiFreqXlat7_MSB  15
#define csr_DfiFreqXlat7_LSB  0
#define csr_DfiFreqXlat7_MASK 0xffff
#define csr_DfiFreqXlatVal28_RANGE  3:0
#define csr_DfiFreqXlatVal28_BITS   3:0
#define csr_DfiFreqXlatVal28_MSB  3
#define csr_DfiFreqXlatVal28_LSB  0
#define csr_DfiFreqXlatVal28_MASK 0xf
#define csr_DfiFreqXlatVal29_RANGE  7:4
#define csr_DfiFreqXlatVal29_BITS   3:0
#define csr_DfiFreqXlatVal29_MSB  7
#define csr_DfiFreqXlatVal29_LSB  4
#define csr_DfiFreqXlatVal29_MASK 0xf0
#define csr_DfiFreqXlatVal30_RANGE  11:8
#define csr_DfiFreqXlatVal30_BITS   3:0
#define csr_DfiFreqXlatVal30_MSB  11
#define csr_DfiFreqXlatVal30_LSB  8
#define csr_DfiFreqXlatVal30_MASK 0xf00
#define csr_DfiFreqXlatVal31_RANGE  15:12
#define csr_DfiFreqXlatVal31_BITS   3:0
#define csr_DfiFreqXlatVal31_MSB  15
#define csr_DfiFreqXlatVal31_LSB  12
#define csr_DfiFreqXlatVal31_MASK 0xf000
#define csr_AcsmCtrl7_RANGE  15:0
#define csr_AcsmCtrl7_BITS   15:0
#define csr_AcsmCtrl7_MSB  15
#define csr_AcsmCtrl7_LSB  0
#define csr_AcsmCtrl7_MASK 0xffff
#define csr_AcsmRasPCfg_RANGE  15:0
#define csr_AcsmRasPCfg_BITS   15:0
#define csr_AcsmRasPCfg_MSB  15
#define csr_AcsmRasPCfg_LSB  0
#define csr_AcsmRasPCfg_MASK 0xffff
#define csr_SequenceReg0b69s0_RANGE  15:0
#define csr_SequenceReg0b69s0_BITS   15:0
#define csr_SequenceReg0b69s0_MSB  15
#define csr_SequenceReg0b69s0_LSB  0
#define csr_SequenceReg0b69s0_MASK 0xffff
#define csr_TxRdPtrInit_RANGE  0:0
#define csr_TxRdPtrInit_BITS   0:0
#define csr_TxRdPtrInit_MSB  0
#define csr_TxRdPtrInit_LSB  0
#define csr_TxRdPtrInit_MASK 0x1
#define csr_AcsmCtrl8_RANGE  15:0
#define csr_AcsmCtrl8_BITS   15:0
#define csr_AcsmCtrl8_MSB  15
#define csr_AcsmCtrl8_LSB  0
#define csr_AcsmCtrl8_MASK 0xffff
#define csr_AcsmRasPSeed_RANGE  15:0
#define csr_AcsmRasPSeed_BITS   15:0
#define csr_AcsmRasPSeed_MSB  15
#define csr_AcsmRasPSeed_LSB  0
#define csr_AcsmRasPSeed_MASK 0xffff
#define csr_SequenceReg0b69s1_RANGE  15:0
#define csr_SequenceReg0b69s1_BITS   15:0
#define csr_SequenceReg0b69s1_MSB  15
#define csr_SequenceReg0b69s1_LSB  0
#define csr_SequenceReg0b69s1_MASK 0xffff
#define csr_DfiInitComplete_RANGE  0:0
#define csr_DfiInitComplete_BITS   0:0
#define csr_DfiInitComplete_MSB  0
#define csr_DfiInitComplete_LSB  0
#define csr_DfiInitComplete_MASK 0x1
#define csr_AcsmCtrl9_RANGE  15:0
#define csr_AcsmCtrl9_BITS   15:0
#define csr_AcsmCtrl9_MSB  15
#define csr_AcsmCtrl9_LSB  0
#define csr_AcsmCtrl9_MASK 0xffff
#define csr_AcsmCasPCfg_RANGE  15:0
#define csr_AcsmCasPCfg_BITS   15:0
#define csr_AcsmCasPCfg_MSB  15
#define csr_AcsmCasPCfg_LSB  0
#define csr_AcsmCasPCfg_MASK 0xffff
#define csr_SequenceReg0b69s2_RANGE  8:0
#define csr_SequenceReg0b69s2_BITS   8:0
#define csr_SequenceReg0b69s2_MSB  8
#define csr_SequenceReg0b69s2_LSB  0
#define csr_SequenceReg0b69s2_MASK 0x1ff
#define csr_DfiInitCompleteShadow_RANGE  0:0
#define csr_DfiInitCompleteShadow_BITS   0:0
#define csr_DfiInitCompleteShadow_MSB  0
#define csr_DfiInitCompleteShadow_LSB  0
#define csr_DfiInitCompleteShadow_MASK 0x1
#define csr_AcsmCtrl10_RANGE  15:0
#define csr_AcsmCtrl10_BITS   15:0
#define csr_AcsmCtrl10_MSB  15
#define csr_AcsmCtrl10_LSB  0
#define csr_AcsmCtrl10_MASK 0xffff
#define csr_AcsmCasPSeed_RANGE  15:0
#define csr_AcsmCasPSeed_BITS   15:0
#define csr_AcsmCasPSeed_MSB  15
#define csr_AcsmCasPSeed_LSB  0
#define csr_AcsmCasPSeed_MASK 0xffff
#define csr_DfiFreqRatio_RANGE  1:0
#define csr_DfiFreqRatio_BITS   1:0
#define csr_DfiFreqRatio_MSB  1
#define csr_DfiFreqRatio_LSB  0
#define csr_DfiFreqRatio_MASK 0x3
#define csr_SequenceReg0b70s0_RANGE  15:0
#define csr_SequenceReg0b70s0_BITS   15:0
#define csr_SequenceReg0b70s0_MSB  15
#define csr_SequenceReg0b70s0_LSB  0
#define csr_SequenceReg0b70s0_MASK 0xffff
#define csr_AcsmCtrl11_RANGE  15:0
#define csr_AcsmCtrl11_BITS   15:0
#define csr_AcsmCtrl11_MSB  15
#define csr_AcsmCtrl11_LSB  0
#define csr_AcsmCtrl11_MASK 0xffff
#define csr_AcsmRasAdrInc_RANGE  7:0
#define csr_AcsmRasAdrInc_BITS   7:0
#define csr_AcsmRasAdrInc_MSB  7
#define csr_AcsmRasAdrInc_LSB  0
#define csr_AcsmRasAdrInc_MASK 0xff
#define csr_AcsmCasAdrInc_RANGE  15:8
#define csr_AcsmCasAdrInc_BITS   7:0
#define csr_AcsmCasAdrInc_MSB  15
#define csr_AcsmCasAdrInc_LSB  8
#define csr_AcsmCasAdrInc_MASK 0xff00
#define csr_RxFifoChecks_RANGE  0:0
#define csr_RxFifoChecks_BITS   0:0
#define csr_RxFifoChecks_MSB  0
#define csr_RxFifoChecks_LSB  0
#define csr_RxFifoChecks_MASK 0x1
#define csr_DoFrequentRxFifoChecks_RANGE  0:0
#define csr_DoFrequentRxFifoChecks_BITS   0:0
#define csr_DoFrequentRxFifoChecks_MSB  0
#define csr_DoFrequentRxFifoChecks_LSB  0
#define csr_DoFrequentRxFifoChecks_MASK 0x1
#define csr_SequenceReg0b70s1_RANGE  15:0
#define csr_SequenceReg0b70s1_BITS   15:0
#define csr_SequenceReg0b70s1_MSB  15
#define csr_SequenceReg0b70s1_LSB  0
#define csr_SequenceReg0b70s1_MASK 0xffff
#define csr_AcsmCtrl12_RANGE  11:0
#define csr_AcsmCtrl12_BITS   11:0
#define csr_AcsmCtrl12_MSB  11
#define csr_AcsmCtrl12_LSB  0
#define csr_AcsmCtrl12_MASK 0xfff
#define csr_AcsmBnkPCfg_RANGE  3:0
#define csr_AcsmBnkPCfg_BITS   3:0
#define csr_AcsmBnkPCfg_MSB  3
#define csr_AcsmBnkPCfg_LSB  0
#define csr_AcsmBnkPCfg_MASK 0xf
#define csr_AcsmBnkPSeed_RANGE  7:4
#define csr_AcsmBnkPSeed_BITS   3:0
#define csr_AcsmBnkPSeed_MSB  7
#define csr_AcsmBnkPSeed_LSB  4
#define csr_AcsmBnkPSeed_MASK 0xf0
#define csr_AcsmBnkAdrInc_RANGE  11:8
#define csr_AcsmBnkAdrInc_BITS   3:0
#define csr_AcsmBnkAdrInc_MSB  11
#define csr_AcsmBnkAdrInc_LSB  8
#define csr_AcsmBnkAdrInc_MASK 0xf00
#define csr_SequenceReg0b70s2_RANGE  8:0
#define csr_SequenceReg0b70s2_BITS   8:0
#define csr_SequenceReg0b70s2_MSB  8
#define csr_SequenceReg0b70s2_LSB  0
#define csr_SequenceReg0b70s2_MASK 0x1ff
#define csr_AcsmCtrl13_RANGE  3:0
#define csr_AcsmCtrl13_BITS   3:0
#define csr_AcsmCtrl13_MSB  3
#define csr_AcsmCtrl13_LSB  0
#define csr_AcsmCtrl13_MASK 0xf
#define csr_AcsmCkeEnb_RANGE  3:0
#define csr_AcsmCkeEnb_BITS   3:0
#define csr_AcsmCkeEnb_MSB  3
#define csr_AcsmCkeEnb_LSB  0
#define csr_AcsmCkeEnb_MASK 0xf
#define csr_SequenceReg0b71s0_RANGE  15:0
#define csr_SequenceReg0b71s0_BITS   15:0
#define csr_SequenceReg0b71s0_MSB  15
#define csr_SequenceReg0b71s0_LSB  0
#define csr_SequenceReg0b71s0_MASK 0xffff
#define csr_AcsmCtrl14_RANGE  3:0
#define csr_AcsmCtrl14_BITS   3:0
#define csr_AcsmCtrl14_MSB  3
#define csr_AcsmCtrl14_LSB  0
#define csr_AcsmCtrl14_MASK 0xf
#define csr_AcsmRasPCfgUp_RANGE  3:0
#define csr_AcsmRasPCfgUp_BITS   3:0
#define csr_AcsmRasPCfgUp_MSB  3
#define csr_AcsmRasPCfgUp_LSB  0
#define csr_AcsmRasPCfgUp_MASK 0xf
#define csr_MTestDtoCtrl_RANGE  0:0
#define csr_MTestDtoCtrl_BITS   0:0
#define csr_MTestDtoCtrl_MSB  0
#define csr_MTestDtoCtrl_LSB  0
#define csr_MTestDtoCtrl_MASK 0x1
#define csr_MTESTdtoEn_RANGE  0:0
#define csr_MTESTdtoEn_BITS   0:0
#define csr_MTESTdtoEn_MSB  0
#define csr_MTESTdtoEn_LSB  0
#define csr_MTESTdtoEn_MASK 0x1
#define csr_Seq0BFixedAddrBits_RANGE  6:0
#define csr_Seq0BFixedAddrBits_BITS   6:0
#define csr_Seq0BFixedAddrBits_MSB  6
#define csr_Seq0BFixedAddrBits_LSB  0
#define csr_Seq0BFixedAddrBits_MASK 0x7f
#define csr_Seq0BChipletBits_RANGE  3:0
#define csr_Seq0BChipletBits_BITS   3:0
#define csr_Seq0BChipletBits_MSB  3
#define csr_Seq0BChipletBits_LSB  0
#define csr_Seq0BChipletBits_MASK 0xf
#define csr_Seq0BPstateBits_RANGE  6:4
#define csr_Seq0BPstateBits_BITS   2:0
#define csr_Seq0BPstateBits_MSB  6
#define csr_Seq0BPstateBits_LSB  4
#define csr_Seq0BPstateBits_MASK 0x70
#define csr_SequenceReg0b71s1_RANGE  15:0
#define csr_SequenceReg0b71s1_BITS   15:0
#define csr_SequenceReg0b71s1_MSB  15
#define csr_SequenceReg0b71s1_LSB  0
#define csr_SequenceReg0b71s1_MASK 0xffff
#define csr_AcsmCtrl15_RANGE  3:0
#define csr_AcsmCtrl15_BITS   3:0
#define csr_AcsmCtrl15_MSB  3
#define csr_AcsmCtrl15_LSB  0
#define csr_AcsmCtrl15_MASK 0xf
#define csr_AcsmRasPSeedUp_RANGE  3:0
#define csr_AcsmRasPSeedUp_BITS   3:0
#define csr_AcsmRasPSeedUp_MSB  3
#define csr_AcsmRasPSeedUp_LSB  0
#define csr_AcsmRasPSeedUp_MASK 0xf
// Fields brought to you by the letter D
#define D_range 11:8
#define D_min 0
#define D_max 3
#define D0 0x0
#define D1 0x100
#define D2 0x200
#define D3 0x300
#define Dbrd 0xf00
// Fields brought to you by the letter L
#define L_range 11:8
#define L_min 0
#define L_max 13
#define L0 0x0
#define L1 0x100
#define L2 0x200
#define L3 0x300
#define L4 0x400
#define L5 0x500
#define L6 0x600
#define L7 0x700
#define L8 0x800
#define L9 0x900
#define L10 0xa00
#define L11 0xb00
#define L12 0xc00
#define L13 0xd00
#define Lbrd 0xf00
// Fields brought to you by the letter N
#define N_range 11:8
#define N_min 0
#define N_max 15
#define N0 0x0
#define N1 0x100
#define N2 0x200
#define N3 0x300
#define N4 0x400
#define N5 0x500
#define N6 0x600
#define N7 0x700
#define N8 0x800
#define N9 0x900
#define N10 0xa00
#define N11 0xb00
#define N12 0xc00
#define N13 0xd00
#define N14 0xe00
#define N15 0xf00
#define Nbrd 0xf00
// Fields brought to you by the letter P
#define P_range 22:20
#define P_min 0
#define P_max 3
#define P0 0x0
#define P1 0x100000
#define P2 0x200000
#define P3 0x300000
#define Pbrd 0x700000
// Fields brought to you by the letter Q
#define Q_range 22:20
#define Q_min 0
#define Q_max 3
#define Q0 0x0
#define Q1 0x100000
#define Q2 0x200000
#define Q3 0x300000
#define Qbrd 0x700000
// Fields brought to you by the letter Y
#define Y_range 27:24
#define Y_min 0
#define Y_max 
#define Y0 0x0
#define Ybrd 0xf000000
// Fields brought to you by the letter b
#define b_range 11:8
#define b_min 0
#define b_max 1
#define b0 0x0
#define b1 0x100
#define bbrd 0xf00
// Fields brought to you by the letter c
#define c_range 15:12
#define c_min 0
#define c_max 15
#define c0 0x0
#define c1 0x1000
#define c2 0x2000
#define c3 0x3000
#define c4 0x4000
#define c5 0x5000
#define c6 0x6000
#define c7 0x7000
#define c8 0x8000
#define c9 0x9000
#define c10 0xa000
#define c11 0xb000
#define c12 0xc000
#define c13 0xd000
#define c14 0xe000
#define c15 0xf000
#define cbrd 0xf000
#define B_range 15:12
#define B_min 0
#define B_max 15
#define B0 0x0
#define B1 0x1000
#define B2 0x2000
#define B3 0x3000
#define B4 0x4000
#define B5 0x5000
#define B6 0x6000
#define B7 0x7000
#define B8 0x8000
#define B9 0x9000
#define B10 0xa000
#define B11 0xb000
#define B12 0xc000
#define B13 0xd000
#define B14 0xe000
#define B15 0xf000
#define Bbrd 0xf000
// Fields brought to you by the letter i
#define i_range 11:8
#define i_min 0
#define i_max 8
#define i0 0x0
#define i1 0x100
#define i2 0x200
#define i3 0x300
#define i4 0x400
#define i5 0x500
#define i6 0x600
#define i7 0x700
#define i8 0x800
#define ibrd 0xf00
// Fields brought to you by the letter j
#define j_range 11:8
#define j_min 0
#define j_max 0
#define j0 0x0
#define jbrd 0xf00
// Fields brought to you by the letter m
#define m_range 11:8
#define m_min 0
#define m_max 8
#define m0 0x0
#define m1 0x100
#define m2 0x200
#define m3 0x300
#define m4 0x400
#define m5 0x500
#define m6 0x600
#define m7 0x700
#define m8 0x800
#define mbrd 0xf00
// Fields brought to you by the letter p
#define p_range 22:20
#define p_min 0
#define p_max 3
#define p0 0x0
#define p1 0x100000
#define p2 0x200000
#define p3 0x300000
#define pbrd 0x700000
// Fields brought to you by the letter r
#define r_range 11:8
#define r_min 0
#define r_max 8
#define r0 0x0
#define r1 0x100
#define r2 0x200
#define r3 0x300
#define r4 0x400
#define r5 0x500
#define r6 0x600
#define r7 0x700
#define r8 0x800
#define rbrd 0xf00
// Fields brought to you by the letter t
#define t_range 19:16
#define t_min 0
#define t_max 15
#define t0 0x0
#define t1 0x10000
#define t2 0x20000
#define t3 0x30000
#define t4 0x40000
#define t5 0x50000
#define t6 0x60000
#define t7 0x70000
#define t8 0x80000
#define t9 0x90000
#define t10 0xa0000
#define t11 0xb0000
#define t12 0xc0000
#define t13 0xd0000
#define t14 0xe0000
#define t15 0xf0000
#define tbrd 0xf0000
// Fields brought to you by the letter u
#define u_range 11:8
#define u_min 0
#define u_max 1
#define u0 0x0
#define u1 0x100
#define ubrd 0xf00
#define tACSM 0x40000
#define tACSMbrd 0x4f000
#define tALL 0xf0000
#define tALLbrd 0xff000
#define tANIB 0x0
#define tANIBbrd 0xf000
#define tAPBONLY 0xd0000
#define tAPBONLYbrd 0xdf000
#define tDBYTE 0x10000
#define tDBYTEbrd 0x1f000
#define tDRTUB 0xc0000
#define tDRTUBbrd 0xcf000
#define tINITENG 0x90000
#define tINITENGbrd 0x9f000
#define tMASTER 0x20000
#define tMASTERbrd 0x2f000
#define tPPGC 0x70000
#define tPPGCbrd 0x7f000
#define tUCTL_MEM 0x50000
#define tUCTL_MEMbrd 0x5f000
#define DBYTE_NUM 9
#define ANIB_NUM 12
